powerpc/include/reg.h

13 			 asm volatile("mfspr %0," _str(rn) \
15 #define mtspr(rn, v)	asm volatile("mtspr " _str(rn) ",%0" : \
27 #define   MMCR0_PMAO   0x00000080
28 #define   MMCR0_PMAE   0x04000000
29 #define   MMCR0_FC     0x80000000
35 #define SPRN_BESCRR    802     /* Branch event status & control REset (1 bits set to 0) */
38 #define BESCR_PMEO     0x1     /* PMU Event-based exception Occurred */
39 #define BESCR_PME      (0x1ul << 32) /* PMU Event-based exception Enable */
54 #define SPRN_TEXASR     0x82    /* Transaction Exception and Status Register */
55 #define SPRN_TFIAR      0x81    /* Transaction Failure Inst Addr    */
56 #define SPRN_TFHAR      0x80    /* Transaction Failure Handler Addr */
57 #define SPRN_TAR        0x32f	/* Target Address Register */
59 #define PVR_VER(pvr)	(((pvr) >>  16) & 0xFFFF)
60 #define SPRN_PVR	0x11F
62 #define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
63 #define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
64 #define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
66 #define SPRN_DSCR_PRIV 0x11	/* Privilege State DSCR */
67 #define SPRN_DSCR      0x03	/* Data Stream Control Register */
72 				     "mtspr " __stringify(SPRN_AMR) ",%0;" \
78 #define TEXASR_FC	0xFE00000000000000
79 #define TEXASR_FP	0x0100000000000000
80 #define TEXASR_DA	0x0080000000000000
81 #define TEXASR_NO	0x0040000000000000
82 #define TEXASR_FO	0x0020000000000000
83 #define TEXASR_SIC	0x0010000000000000
84 #define TEXASR_NTC	0x0008000000000000
85 #define TEXASR_TC	0x0004000000000000
86 #define TEXASR_TIC	0x0002000000000000
87 #define TEXASR_IC	0x0001000000000000
88 #define TEXASR_IFC	0x0000800000000000
89 #define TEXASR_ABT	0x0000000100000000
90 #define TEXASR_SPD	0x0000000080000000
91 #define TEXASR_HV	0x0000000020000000
92 #define TEXASR_PR	0x0000000010000000
93 #define TEXASR_FS	0x0000000008000000
94 #define TEXASR_TE	0x0000000004000000
95 #define TEXASR_ROT	0x0000000002000000
109 #define VSX_XX1(xs, ra, rb)	(((xs) & 0x1f) << 21 | ((ra) << 16) |  \
111 #define STXVD2X(xs, ra, rb)	.long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
112 #define LXVD2X(xs, ra, rb)	.long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
135 		"lfd 0, 0(%[" #_asm_symbol_name_addr "]);" \
136 		"lfd 1, 0(%[" #_asm_symbol_name_addr "]);" \
137 		"lfd 2, 0(%[" #_asm_symbol_name_addr "]);" \
138 		"lfd 3, 0(%[" #_asm_symbol_name_addr "]);" \
139 		"lfd 4, 0(%[" #_asm_symbol_name_addr "]);" \
140 		"lfd 5, 0(%[" #_asm_symbol_name_addr "]);" \
141 		"lfd 6, 0(%[" #_asm_symbol_name_addr "]);" \
142 		"lfd 7, 0(%[" #_asm_symbol_name_addr "]);" \
143 		"lfd 8, 0(%[" #_asm_symbol_name_addr "]);" \
144 		"lfd 9, 0(%[" #_asm_symbol_name_addr "]);" \
145 		"lfd 10, 0(%[" #_asm_symbol_name_addr "]);" \
146 		"lfd 11, 0(%[" #_asm_symbol_name_addr "]);" \
147 		"lfd 12, 0(%[" #_asm_symbol_name_addr "]);" \
148 		"lfd 13, 0(%[" #_asm_symbol_name_addr "]);" \
149 		"lfd 14, 0(%[" #_asm_symbol_name_addr "]);" \
150 		"lfd 15, 0(%[" #_asm_symbol_name_addr "]);" \
151 		"lfd 16, 0(%[" #_asm_symbol_name_addr "]);" \
152 		"lfd 17, 0(%[" #_asm_symbol_name_addr "]);" \
153 		"lfd 18, 0(%[" #_asm_symbol_name_addr "]);" \
154 		"lfd 19, 0(%[" #_asm_symbol_name_addr "]);" \
155 		"lfd 20, 0(%[" #_asm_symbol_name_addr "]);" \
156 		"lfd 21, 0(%[" #_asm_symbol_name_addr "]);" \
157 		"lfd 22, 0(%[" #_asm_symbol_name_addr "]);" \
158 		"lfd 23, 0(%[" #_asm_symbol_name_addr "]);" \
159 		"lfd 24, 0(%[" #_asm_symbol_name_addr "]);" \
160 		"lfd 25, 0(%[" #_asm_symbol_name_addr "]);" \
161 		"lfd 26, 0(%[" #_asm_symbol_name_addr "]);" \
162 		"lfd 27, 0(%[" #_asm_symbol_name_addr "]);" \
163 		"lfd 28, 0(%[" #_asm_symbol_name_addr "]);" \
164 		"lfd 29, 0(%[" #_asm_symbol_name_addr "]);" \
165 		"lfd 30, 0(%[" #_asm_symbol_name_addr "]);" \
166 		"lfd 31, 0(%[" #_asm_symbol_name_addr "]);"