Home
last modified time | relevance | path

Searched +full:- +full:uart (Results 1 – 25 of 1074) sorted by relevance

12345678910>>...43

/openbmc/linux/sound/drivers/
H A Dserial-u16550.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Added support for the Midiator MS-124T and for the MS-124W in
17 * More documentation can be found in serial-u16550.txt.
39 #define SNDRV_SERIAL_MS124T 1 /* Midiator MS-124T */
40 #define SNDRV_SERIAL_MS124W_SA 2 /* Midiator MS-124W in S/A mode */
41 #define SNDRV_SERIAL_MS124W_MB 3 /* Midiator MS-124W in M/B mode */
46 "MS-124T",
47 "MS-124W S/A",
48 "MS-124W M/B",
53 #define SNDRV_SERIAL_DROPBUFF 1 /* Non-blocking discard operation */
[all …]
/openbmc/qemu/hw/char/
H A Dgrlib_apbuart.c2 * QEMU GRLIB APB UART Emulator
4 * SPDX-License-Identifier: MIT
6 * Copyright (c) 2010-2024 AdaCore
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
34 #include "chardev/char-fe.h"
41 /* UART status register fields */
54 /* UART control register fields */
79 OBJECT_DECLARE_SIMPLE_TYPE(UART, GRLIB_APB_UART)
81 struct UART { struct
[all …]
/openbmc/u-boot/drivers/serial/
H A DKconfig11 Select a default baudrate, where "default" has a driver-specific
12 meaning of either setting the baudrate for the early debug UART
19 # non-dm serial code
32 In various cases, we need to specify which of the UART devices that
34 in U-Boot.
41 In very space-constrained devices even the full UART driver is too
42 large. In this case the debug UART can still be used in some cases.
43 This option enables the full UART in U-Boot, so if is it disabled,
44 the full UART driver will be omitted, thus saving space.
51 In very space-constrained devices even the full UART driver is too
[all …]
H A Dmcfuart.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
4 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
11 * Minimal serial functions needed to use one of the uart ports
21 #include <asm/uart.h>
27 static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate) in mcf_serial_init_common() argument
33 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ in mcf_serial_init_common()
34 writeb(UART_UCR_RESET_RX, &uart->ucr); in mcf_serial_init_common()
35 writeb(UART_UCR_RESET_TX, &uart->ucr); in mcf_serial_init_common()
36 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in mcf_serial_init_common()
[all …]
H A Dserial_s5p.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/uart.h>
33 u8 port_id; /* uart port number */
41 * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
62 static void __maybe_unused s5p_serial_init(struct s5p_uart *uart) in s5p_serial_init() argument
65 writel(0x3, &uart->ufcon); in s5p_serial_init()
66 writel(0, &uart->umcon); in s5p_serial_init()
68 writel(0x3, &uart->ulcon); in s5p_serial_init()
70 writel(0x245, &uart->ucon); in s5p_serial_init()
73 static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk, in s5p_serial_baud() argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dmediatek,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 - $ref: serial.yaml#
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
24 - items:
[all …]
H A Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
[all …]
H A Damlogic,meson-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
15 of SoCs, and can be present either in the "Always-On" power domain or the
16 "Everything-Else" power domain.
18 The particularity of the "Always-On" Serial Interface is that the hardware
[all …]
H A Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
[all …]
H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: serial.yaml#
14 - $ref: rs485.yaml#
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
[all …]
H A Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - items:
22 - const: samsung,exynosautov9-uart
[all …]
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter)
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
[all …]
H A Dsprd-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Spreadtrum serial UART
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - items:
19 - enum:
[all …]
H A Dbrcm,bcm7271-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
13 - $ref: serial.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
23 - enum:
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dmen_z135_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * MEN 16z135 High Speed UART
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
145 reg = ioread32(port->membase + addr); in men_z135_reg_set()
[all …]
H A Dtimbuart.c1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
[all …]
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_tegra.c1 // SPDX-License-Identifier: GPL-2.0+
31 status = p->serial_in(p, UART_LSR); in tegra_uart_handle_break()
35 p->serial_in(p, UART_RX); in tegra_uart_handle_break()
37 if (--tmout == 0) in tegra_uart_handle_break()
46 struct tegra_uart *uart; in tegra_uart_probe() local
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
52 if (!uart) in tegra_uart_probe()
53 return -ENOMEM; in tegra_uart_probe()
58 spin_lock_init(&port->lock); in tegra_uart_probe()
60 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | in tegra_uart_probe()
[all …]
H A D8250_core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
9 * Supports: ISA-compatible 8250/16550 ports
12 * userspace-configurable "phantom" ports
48 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
49 * is unsafe when used on edge-triggered interrupts.
63 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * line has been de-asserted.
117 spin_lock(&i->lock); in serial8250_interrupt()
119 l = i->head; in serial8250_interrupt()
[all …]
H A D8250_lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Serial port driver for NXP LPC18xx/43xx UART
43 if (rs485->flags & SER_RS485_ENABLED) { in lpc18xx_rs485_config()
47 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpc18xx_rs485_config()
51 if (rs485->delay_rts_after_send) { in lpc18xx_rs485_config()
52 baud_clk = port->uartclk / up->dl_read(up); in lpc18xx_rs485_config()
53 rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send in lpc18xx_rs485_config()
60 rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC) in lpc18xx_rs485_config()
80 offset = offset << p->regshift; in lpc18xx_uart_serial_out()
81 writel(value, p->membase + offset); in lpc18xx_uart_serial_out()
[all …]
H A D8250_ingenic.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
46 return readl(port->membase + (offset << 2)); in early_in()
51 writel(value, port->membase + (offset << 2)); in early_out()
68 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
92 struct uart_port *port = &dev->port; in ingenic_earlycon_setup_tail()
96 if (!dev->port.membase) in ingenic_earlycon_setup_tail()
[all …]
/openbmc/linux/include/uapi/linux/
H A Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
34 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
35 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
36 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
37 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
38 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
39 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
43 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dcps-vec-ns16550.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
46 * @a0: pointer to NULL-terminated ASCII string
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
[all …]
/openbmc/u-boot/board/astro/mcf5373l/
H A Dmcf5373l.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
5 * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
16 #include <asm/uart.h>
42 &sdp->cs0); in dram_init()
44 &sdp->cs1); in dram_init()
50 __raw_writel(0x33211530, &sdp->cfg1); in dram_init()
51 __raw_writel(0x56570000, &sdp->cfg2); in dram_init()
53 __raw_writel(0xE1462C02, &sdp->ctrl); in dram_init()
56 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
[all …]
/openbmc/openbmc/meta-bytedance/meta-g220a/recipes-phosphor/console/obmc-console/
H A Dobmc-console@.service3 BindsTo=dev-%i.device
4 After=dev-%i.device
7 ExecStartPre=/bin/sh -c 'echo -n "uart3" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.u…
8 ExecStartPre=/bin/sh -c 'echo -n "uart1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.u…
9 ExecStartPre=/bin/sh -c 'echo -n "io1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uar…
10 ExecStartPre=/bin/sh -c 'echo -n "uart4" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.u…
11 ExecStart=/usr/bin/env obmc-console-server --config {sysconfdir}/obmc-console.conf %i
12 ExecStopPost=/bin/sh -c 'echo -n "io1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uar…
13 ExecStopPost=/bin/sh -c 'echo -n "io3" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uar…
14 ExecStopPost=/bin/sh -c 'echo -n "io4" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uar…
[all …]
/openbmc/linux/arch/arm/include/debug/
H A Dtegra.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
12 * Portions based on mach-omap2's debug-macro.S
13 * Copyright (C) 1994-1999 Russell King
40 * Must be section-aligned since a section mapping is used early on.
41 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
[all …]

12345678910>>...43