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/openbmc/qemu/tests/qemu-iotests/
H A D142.out6 === Simple test for all cache modes ===
8 Testing: -drive file=TEST_DIR/t.qcow2,cache=none
9 QEMU X.Y.Z monitor - type 'help' for more information
12 Testing: -drive file=TEST_DIR/t.qcow2,cache=directsync
13 QEMU X.Y.Z monitor - type 'help' for more information
16 Testing: -drive file=TEST_DIR/t.qcow2,cache=writeback
17 QEMU X.Y.Z monitor - type 'help' for more information
20 Testing: -drive file=TEST_DIR/t.qcow2,cache=writethrough
21 QEMU X.Y.Z monitor - type 'help' for more information
24 Testing: -drive file=TEST_DIR/t.qcow2,cache=unsafe
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H A D157.out6 Testing: cache='writeback' wce=''
7 Cache mode: writeback
8 Testing: cache='writeback' wce=',write-cache=auto'
9 Cache mode: writeback
10 Testing: cache='writeback' wce=',write-cache=on'
11 Cache mode: writeback
12 Testing: cache='writeback' wce=',write-cache=off'
13 Cache mode: writethrough
14 Testing: cache='writethrough' wce=''
15 Cache mode: writethrough
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H A D1423 # Test for configuring cache modes of arbitrary nodes (requires O_DIRECT)
43 # We test all cache modes anyway, but O_DIRECT needs to be supported
51 if ! test -t 0; then
57 ) | $QEMU -nographic -monitor stdio -nodefaults "$@"
70 _make_test_img -b "$TEST_IMG.base" $size -F $IMGFMT
73 echo === Simple test for all cache modes ===
76 run_qemu -drive file="$TEST_IMG",cache=none
77 run_qemu -drive file="$TEST_IMG",cache=directsync
78 run_qemu -drive file="$TEST_IMG",cache=writeback
79 run_qemu -drive file="$TEST_IMG",cache=writethrough
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H A D1034 # Test case for qcow2 metadata cache size specification
44 _unsupported_imgopts 'refcount_bits=1[^0-9]' data_file
49 $QEMU_IO -c 'write -P 42 0 64k' "$TEST_IMG" | _filter_qemu_io
56 $QEMU_IO -c "open -o cache-size=1.25M,l2-cache-size=1M,refcount-cache-size=0.25M $TEST_IMG" \
58 # l2-cache-size may not exceed cache-size
59 $QEMU_IO -c "open -o cache-size=1M,l2-cache-size=2M $TEST_IMG" 2>&1 \
61 # refcount-cache-size may not exceed cache-size
62 $QEMU_IO -c "open -o cache-size=1M,refcount-cache-size=2M $TEST_IMG" 2>&1 \
66 $QEMU_IO -c "open -o cache-size=0,l2-cache-size=0,refcount-cache-size=0 $TEST_IMG" \
69 # Invalid cache entry sizes
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H A D103.out8 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
9 qemu-io: can't open device TEST_DIR/t.IMGFMT: l2-cache-size may not exceed cache-size
10 qemu-io: can't open device TEST_DIR/t.IMGFMT: refcount-cache-size may not exceed cache-size
11 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
12 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
13 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
14 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
33 === Testing minimal L2 cache and COW ===
H A D13744 # We are going to use lazy-refcounts
56 -c "reopen -o lazy-refcounts=on,pass-discard-request=on" \
57 -c "reopen -o lazy-refcounts=off,pass-discard-request=off" \
58 -c "reopen -o pass-discard-snapshot=on,pass-discard-other=on" \
59 -c "reopen -o pass-discard-snapshot=off,pass-discard-other=off" \
60 -c "reopen -o overlap-check=all" \
61 -c "reopen -o overlap-check=none" \
62 -c "reopen -o overlap-check=cached" \
63 -c "reopen -o overlap-check=constant" \
64 -c "reopen -o overlap-check.template=all" \
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/openbmc/qemu/migration/
H A Dpage_cache.c2 * Page cache for QEMU
3 * The cache is base on a hash of the page address
11 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
23 /* the page in cache will not be replaced in two cycles */
45 PageCache *cache; in cache_init() local
48 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
55 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
61 cache = g_try_malloc(sizeof(*cache)); in cache_init()
62 if (!cache) { in cache_init()
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H A Dpage_cache.h2 * Page cache for QEMU
3 * The cache is base on a hash of the page address
11 * See the COPYING file in the top-level directory.
18 /* Page cache for storing guest pages */
22 * cache_init: Initialize the page cache
25 * Returns new allocated cache or NULL on error
27 * @cache_size: cache size in bytes
28 * @page_size: cache page size
33 * cache_fini: free all cache resources
34 * @cache pointer to the PageCache struct
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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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/openbmc/qemu/include/exec/
H A Dmemory_ldst_cached.h.inc27 static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
30 assert(addr < cache->len && 2 <= cache->len - addr);
31 fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
32 if (likely(cache->ptr)) {
33 return LD_P(uw)(cache->ptr + addr);
35 return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
39 static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
42 assert(addr < cache->len && 4 <= cache->len - addr);
43 fuzz_dma_read_cb(cache->xlat + addr, 4, cache->mrs.mr);
44 if (likely(cache->ptr)) {
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/openbmc/u-boot/arch/x86/lib/
H A Dmrccache.c1 // SPDX-License-Identifier: GPL-2.0
21 struct mrc_data_container *cache) in next_mrc_block() argument
24 u32 mrc_size = sizeof(*cache) + cache->data_size; in next_mrc_block()
25 u8 *region_ptr = (u8 *)cache; in next_mrc_block()
27 if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { in next_mrc_block()
28 mrc_size &= ~(MRC_DATA_ALIGN - 1UL); in next_mrc_block()
37 static int is_mrc_cache(struct mrc_data_container *cache) in is_mrc_cache() argument
39 return cache && (cache->signature == MRC_DATA_SIGNATURE); in is_mrc_cache()
44 struct mrc_data_container *cache, *next; in mrccache_find_current() local
48 base_addr = entry->base + entry->offset; in mrccache_find_current()
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/openbmc/qemu/docs/
H A Dqcow2-cache.txt1 qcow2 L2/refcount cache configuration
3 Copyright (C) 2015, 2018-2020 Igalia, S.L.
7 later. See the COPYING file in the top-level directory.
10 ------------
12 performance significantly. However, setting the right cache sizes is
18 Please refer to the docs/interop/qcow2.rst file for an in-depth
23 --------
30 The 'qemu-img create' command supports specifying the size using the
33 qemu-img create -f qcow2 -o cluster_size=128K hd.qcow2 4G
37 -------------
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H A Dxbzrle.txt5 of VM downtime and the total live-migration time of Virtual machines.
15 be stored on the source. Those pages are stored in a dedicated cache
17 The larger the cache size the better the chances are that the page has already
18 been stored in the cache.
19 A small cache size will result in high cache miss rate.
20 Cache size can be changed before and during migration.
45 retrieving the old page content from the cache (default size of 64MB). The
55 XBZRLE has a sustained bandwidth of 2-2.5 GB/s for typical workloads making it
56 ideal for in-line, real-time encoding such as is needed for live-migration.
74 Cache update strategy
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/openbmc/u-boot/doc/
H A DREADME.arm-caches1 Disabling I-cache:
2 - Set CONFIG_SYS_ICACHE_OFF
4 Disabling D-cache:
5 - Set CONFIG_SYS_DCACHE_OFF
7 Enabling I-cache:
8 - Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable().
10 Enabling D-cache:
11 - Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable().
14 - Implement enable_caches() for your platform and enable the I-cache and
15 D-cache from this function. This function is called immediately
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H A DREADME.mips2 Notes for the MIPS architecture port of U-Boot
5 ----------
11 Embedded Debian -- Cross-development toolchains
17 ------------
19 * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
21 Cache will be disabled before entering the loaded ELF image without
22 writing back and invalidating cache lines. This leads to cache
23 incoherency in most cases, unless the code gets loaded after U-Boot
24 re-initializes the cache. The more common uImage 'bootm' command does
27 [workaround] To avoid this cache incoherency,
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/openbmc/qemu/contrib/plugins/
H A Dcache.c5 * See the COPYING file in the top-level directory.
12 #include <qemu-plugin.h>
37 * A CacheSet is a set of cache blocks. A memory block that maps to a set can be
43 * whether a block is in the cache or not by searching for its tag.
45 * In order to search for memory data in the cache, the set identifier and tag
81 } Cache; typedef
92 void (*update_hit)(Cache *cache, int set, int blk);
93 void (*update_miss)(Cache *cache, int set, int blk);
95 void (*metadata_init)(Cache *cache);
96 void (*metadata_destroy)(Cache *cache);
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/openbmc/qemu/block/
H A Dqed-l2-cache.c2 * QEMU Enhanced Disk Format L2 Cache
10 * See the COPYING.LIB file in the top-level directory.
15 * L2 table cache usage is as follows:
17 * An open image has one L2 table cache that is used to avoid accessing the
23 * table cache serves up recently referenced L2 tables.
25 * If there is a cache miss, that L2 table is read from the image file and
26 * committed to the cache. Subsequent accesses to that L2 table will be served
27 * from the cache until the table is evicted from the cache.
29 * L2 tables are also committed to the cache when new L2 tables are allocated
30 * in the image file. Since the L2 table cache is write-through, the new L2
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/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
12 /* Cache maintenance operation registers */
47 INVALIDATE_POU, /* i-cache invalidate by address */
48 INVALIDATE_POC, /* d-cache invalidate by address */
49 INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
50 FLUSH_POU, /* d-cache clean by address to the PoU */
51 FLUSH_POC, /* d-cache clean by address to the PoC */
52 FLUSH_SET_WAY, /* d-cache clean by sets/ways */
53 FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S1 /* SPDX-License-Identifier: GPL-2.0+ */
19 * Flush the whole D-cache.
21 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
23 * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
32 mov r10, #0 @ start clean at cache level 0
34 add r2, r10, r10, lsr #1 @ work out 3x current cache level
35 mov r1, r0, lsr r2 @ extract cache type bits from clidr
36 and r1, r1, #7 @ mask of the bits for current cache only
37 cmp r1, #2 @ see what cache we have at this level
38 blt skip @ skip if no cache, or just i-cache
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/openbmc/openbmc/poky/documentation/dev-manual/
H A Ddisk-space.rst1 .. SPDX-License-Identifier: CC-BY-SA-2.0-UK
17 "rm_work", see the :ref:`ref-classes-rm-work` class in the
20 When you inherit this class and build a ``core-image-sato`` image for a
21 ``qemux86-64`` machine from an Ubuntu 22.04 x86-64 system, you end up with a
26 Purging Obsolete Shared State Cache Files
29 After multiple build iterations, the Shared State (sstate) cache can contain
30 multiple cache files for a given package, consuming a substantial amount of
33 The following command is a quick way to purge all the cache files which
36 find build/sstate-cache -type f -mtime +$DAYS -delete
38 The above command relies on the fact that BitBake touches the sstate cache
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S7 #include <asm/cache.h>
23 # error "Invalid cache line size!"
27 * Most of this code is taken from 74xx_7xx/cache.S
32 * Invalidate L1 instruction cache.
35 /* use invalidate-all bit in HID0 */
43 * Invalidate L1 data cache.
53 * Flush data cache.
68 * Write any modified data cache blocks out to memory
69 * and invalidate the corresponding instruction cache blocks.
70 * This is a no-op on the 601.
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/openbmc/u-boot/arch/nds32/include/asm/
H A Dcache.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* cache */
33 /* I-cache sets (# of cache lines) per way */
35 /* I-cache ways */
39 /* D-cache sets (# of cache lines) per way */
41 /* D-cache ways */
45 /* I-cache line size */
48 /* D-cache line size */
53 * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
55 * specified an alternate cache line size.
/openbmc/qemu/qapi/
H A Dmachine-common.json1 # -*- Mode: Python -*-
5 # See the COPYING file in the top-level directory.
57 # topology settings (e.g., cache topology), and this special
58 # level means following the architecture-specific settings.
70 # combination of cache level and cache type.
72 # @l1d: L1 data cache.
74 # @l1i: L1 instruction cache.
76 # @l2: L2 (unified) cache.
78 # @l3: L3 (unified) cache
88 # Cache information for SMP system.
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcache.h2 * include/asm-ppc/cache.h
9 /* bytes per L1 cache line */
23 * Use the L1 data cache line size value for the minimum DMA buffer alignment
35 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
73 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
76 /* Cache control on the MPC8xx is provided through some additional
79 #define IC_CST 560 /* Instruction cache control/status */
81 #define IC_DAT 562 /* Read-only data register */
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dcache.S1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include <asm-offsets.h>
18 * flush or invalidate one level cache.
20 * x0: cache level
27 msr csselr_el1, x12 /* select cache level */
30 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
31 add x2, x2, #4 /* x2 <- log2(cache line size) */
33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
36 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
37 /* x12 <- cache level << 1 */
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