Lines Matching +full:- +full:cache

2 Notes for the MIPS architecture port of U-Boot
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11   Embedded Debian -- Cross-development toolchains
17 ------------
19   * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
21     Cache will be disabled before entering the loaded ELF image without
22     writing back and invalidating cache lines. This leads to cache
23     incoherency in most cases, unless the code gets loaded after U-Boot
24     re-initializes the cache. The more common uImage 'bootm' command does
27     [workaround] To avoid this cache incoherency,
29     2) fix dcache_disable() to do both flushing and disabling cache.
32     or override do_bootelf_exec() not to disable I-/D-caches, because most
33     Linux/MIPS ports don't re-enable caches after entering kernel_entry.
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38   * Probe CPU types, I-/D-cache and TLB size etc. automatically
40   * Secondary cache support missing
48   * Due to cache initialization issues, the DRAM on board must be
49     initialized in board specific assembler language before the cache init
50     code is run -- that is, initialize the DRAM in lowlevel_init().