Lines Matching +full:- +full:cache
1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include <asm-offsets.h>
18 * flush or invalidate one level cache.
20 * x0: cache level
27 msr csselr_el1, x12 /* select cache level */
30 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
31 add x2, x2, #4 /* x2 <- log2(cache line size) */
33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
36 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
37 /* x12 <- cache level << 1 */
38 /* x2 <- line length offset */
39 /* x3 <- number of cache ways - 1 */
40 /* x4 <- number of cache sets - 1 */
41 /* x5 <- bit position of #ways */
44 mov x6, x3 /* x6 <- working copy of #ways */
68 * flush or invalidate all data cache by SET/WAY.
76 and x11, x11, #0x7 /* x11 <- loc */
79 mov x0, #0 /* start flush at cache level 0 */
80 /* x0 <- cache level */
81 /* x10 <- clidr_el1 */
82 /* x11 <- loc */
83 /* x15 <- return address */
87 add x12, x12, x0 /* x0 <- tripled cache level */
89 and x12, x12, #7 /* x12 <- cache type */
91 b.lt skip /* skip if no cache or icache */
94 add x0, x0, #1 /* increment cache level */
126 * clean & invalidate data cache in the range
137 lsl x2, x2, x3 /* cache line size */
139 /* x2 <- minimal cache line size in cache system */
142 1: dc civac, x0 /* clean & invalidate data or unified cache */
153 * invalidate data cache in the range
163 lsl x2, x2, x3 /* cache line size */
165 /* x2 <- minimal cache line size in cache system */
168 1: dc ivac, x0 /* invalidate data or unified cache */