| /openbmc/linux/drivers/gpu/drm/exynos/ |
| H A D | regs-gsc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/drivers/gpu/drm/exynos/regs-gsc.h
7 * Register definition file for Samsung G-Scaler driver
13 /* G-Scaler enable */
33 /* G-Scaler S/W reset */
37 /* G-Scaler IRQ */
40 #define GSC_IRQ_STATUS_OR_FRM_DONE (1 << 16)
45 /* G-Scaler input control */
51 #define GSC_IN_ROT_MASK (7 << 16)
52 #define GSC_IN_ROT_270 (7 << 16)
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| /openbmc/linux/drivers/media/platform/samsung/exynos-gsc/ |
| H A D | gsc-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Register definition file for Samsung G-Scaler driver
12 /* G-Scaler enable */
18 /* G-Scaler S/W reset */
22 /* G-Scaler IRQ */
25 #define GSC_IRQ_STATUS_FRM_DONE_IRQ (1 << 16)
29 /* G-Scaler input control */
31 #define GSC_IN_ROT_MASK (7 << 16)
32 #define GSC_IN_ROT_270 (7 << 16)
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| /openbmc/linux/arch/x86/crypto/ |
| H A D | crct10dif-pcl-asm_64.S | 2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
50 # /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
68 movdqu \offset+16(buf), %xmm12
95 # Assumes len >= 16.
107 movdqu 16*0(buf), %xmm0
108 movdqu 16*1(buf), %xmm1
109 movdqu 16*2(buf), %xmm2
110 movdqu 16*3(buf), %xmm3
111 movdqu 16*4(buf), %xmm4
112 movdqu 16*5(buf), %xmm5
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| H A D | polyval-clmulni_asm.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This is an efficient implementation of POLYVAL using intel PCLMULQDQ-NI
16 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
20 * two-step process only requires 1 finite field reduction for every 8
45 .section .rodata.cst16.gstar, "aM", @progbits, 16
46 .align 16
54 * Performs schoolbook1_iteration on two lists of 128-bit polynomials of length
66 * Computes the product of two 128-bit polynomials at the memory locations
67 * specified by (MSG + 16*i) and (KEY_POWERS + 16*i) and XORs the components of
68 * the 256-bit product into LO, MI, HI.
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| H A D | sha256-ssse3-asm.S | 2 # Implement fast SHA-256 with SSSE3 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
58 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %xmm11 # shuffle xDxC -> DC00
104 g = %r10d define
115 _XFER_SIZE = 16
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| H A D | sha256-avx-asm.S | 2 # Implement fast SHA-256 with AVX1 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
40 # This code is described in an Intel White-Paper:
41 # "Fast SHA-256 Implementations on Intel Architecture Processors"
59 # Add reg to mem using reg-mem add and store
67 shld $(32-(\p1)), \p2, \p2
94 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
95 SHUF_DC00 = %xmm12 # shuffle xDxC -> DC00
111 g = %r10d define
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| /openbmc/linux/Documentation/dev-tools/kunit/ |
| H A D | kunit_suitememorydiagram.svg | 1 <?xml version="1.0" encoding="UTF-8"?>
3 <g transform="translate(-13.724 -17.943)">
4 <g fill="#dad4d4" fill-opacity=".91765" stroke="#1a1a1a">
9 </g>
10 <g>
12 …-family="sans-serif" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="328.…
13 </g>
14 <g transform="translate(0 -258.6)">
16 …-family="sans-serif" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="328.…
17 </g>
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| /openbmc/linux/arch/arm64/crypto/ |
| H A D | polyval-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
18 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
22 * two-step process only requires 1 finite field reduction for every 8
65 .arch armv8-a+crypto
72 * Computes the product of two 128-bit polynomials in X and Y and XORs the
73 * components of the 256-bit product into LO, MI, HI.
84 * Later, the 256-bit result can be extracted as:
96 ext v25.16b, X.16b, X.16b, #8
97 ext v26.16b, Y.16b, Y.16b, #8
98 eor v25.16b, v25.16b, X.16b
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| H A D | crct10dif-ce-core.S | 2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
69 .arch armv8-a+crypto
118 eor perm1.16b, perm1.16b, perm4.16b
120 ushr perm3.2d, perm1.2d, #16
128 tbl bd1.16b, {\bd\().16b}, perm1.16b
129 tbl bd2.16b, {\bd\().16b}, perm2.16b
130 tbl bd3.16b, {\bd\().16b}, perm3.16b
131 tbl bd4.16b, {\bd\().16b}, perm4.16b
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| /openbmc/linux/include/dt-bindings/memory/ |
| H A D | mt8186-memory-port.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
14 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
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| H A D | mt8195-memory-port.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
12 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
20 * modules dma-address-region larbs-ports
21 * disp 0 ~ 4G larb0/1/2/3
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
23 * cam/mdp 8G ~ 12G the other larbs.
24 * N/A 12G ~ 16G
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| /openbmc/linux/arch/arm/crypto/ |
| H A D | crct10dif-ce-core.S | 2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
118 vld1.64 {q11-q12}, [buf]!
155 // Assumes len >= 16.
167 vld1.64 {q0-q1}, [buf]!
168 vld1.64 {q2-q3}, [buf]!
169 vld1.64 {q4-q5}, [buf]!
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| /openbmc/qemu/hw/display/ |
| H A D | pl110_template.h | 45 #define FN(x, y) COPY_PIXEL(d, palette[(data >> (y + 7 - (x))) & 1]); in glue()
51 FN_8(16) in glue()
57 FN_8(16) in glue()
61 width -= 32; in glue()
73 #define FN(x, y) COPY_PIXEL(d, palette[(data >> (y + 6 - (x)*2)) & 3]); in glue()
79 FN_4(0, 16) in glue()
85 FN_4(0, 16) in glue()
89 width -= 16; in glue()
101 #define FN(x, y) COPY_PIXEL(d, palette[(data >> (y + 4 - (x)*4)) & 0xf]); in glue()
107 FN_2(0, 16) in glue()
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| /openbmc/u-boot/include/ |
| H A D | ipu_pixfmt.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
19 (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
31 #define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
32 #define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
33 #define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
34 #define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
35 #define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
36 #define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
37 #define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
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| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-srggb16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB16:
4 .. _v4l2-pix-fmt-sbggr16:
5 .. _v4l2-pix-fmt-sgbrg16:
6 .. _v4l2-pix-fmt-sgrbg16:
15 16-bit Bayer formats
22 These four pixel formats are raw sRGB / Bayer formats with 16 bits per
23 sample. Each sample is stored in a 16-bit word. Each n-pixel row contains
32 .. flat-table::
33 :header-rows: 0
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| H A D | metafmt-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
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| H A D | pixfmt-srggb12.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12:
4 .. _v4l2-pix-fmt-sbggr12:
5 .. _v4l2-pix-fmt-sgbrg12:
6 .. _v4l2-pix-fmt-sgrbg12:
17 12-bit Bayer formats expanded to 16 bits
24 colour. Each colour component is stored in a 16-bit word, with 4 unused
25 high bits filled with zeros. Each n-pixel row contains n/2 green samples
38 .. flat-table::
39 :header-rows: 0
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| H A D | pixfmt-srggb10.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10:
4 .. _v4l2-pix-fmt-sbggr10:
5 .. _v4l2-pix-fmt-sgbrg10:
6 .. _v4l2-pix-fmt-sgrbg10:
16 10-bit Bayer formats expanded to 16 bits
23 sample. Each sample is stored in a 16-bit word, with 6 unused
24 high bits filled with zeros. Each n-pixel row contains n/2 green samples and
37 .. flat-table::
38 :header-rows: 0
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
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| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | simple-framebuffer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
13 A simple frame-buffer describes a frame-buffer setup by firmware or
19 sub-nodes of the chosen node (*). Simplefb nodes must be named
41 interaction, then the chosen node stdout-path property should point
46 It is advised that devicetree files contain pre-filled, disabled
48 mode information and enable them. This way if e.g. later on support
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| /openbmc/qemu/include/standard-headers/drm/ |
| H A D | drm_fourcc.h | 38 * further describe the buffer's format - for example tiling or compression.
41 * ----------------
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * may preserve meaning - such as number of planes - from the fourcc code,
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75 * - Kernel and user-space drivers: for drivers it's important that modifiers
79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92 * -----------------------
97 * upstream in-kernel or open source userspace user does not apply.
105 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
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| /openbmc/linux/include/uapi/drm/ |
| H A D | drm_fourcc.h | 39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
106 ((__u32)(c) << 16) | ((__u32)(d) << 24))
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| /openbmc/linux/crypto/ |
| H A D | sm3.c | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * SM3 secure hash, as specified by OSCCA GM/T 0004-2012 SM3 and described
4 * at https://datatracker.ietf.org/doc/html/draft-sca-cfrg-sm3-02
7 * Copyright (C) 2017 Gilad Ben-Yossef <gilad@benyossef.com>
35 * Transform the message X which consists of 16 32-bit-words. See
36 * GM/T 004-2012 for details.
38 #define R(i, a, b, c, d, e, f, g, h, t, w1, w2) \ argument
43 h += GG ## i(e, f, g) + ss1 + (w1); \
49 #define R1(a, b, c, d, e, f, g, h, t, w1, w2) \ argument
50 R(1, a, b, c, d, e, f, g, h, t, w1, w2)
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
49 {"TC58NVG2S0H 4G 3.3V 8-bit",
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| /openbmc/qemu/tcg/ |
| H A D | tcg-op-gvec.c | 22 #include "tcg/tcg-temp-internal.h"
23 #include "tcg/tcg-op-common.h"
24 #include "tcg/tcg-op-gvec-common.h"
25 #include "tcg/tcg-gvec-desc.h"
44 case 16: in check_size_align()
54 max_align = maxsz >= 16 ? 15 : 7; in check_size_align()
99 * values from the caller will not be detected, e.g. if the in simd_desc()
101 * incorrectly passes us 1 << (SIMD_DATA_BITS - 1). in simd_desc()
106 oprsz = (oprsz / 8) - 1; in simd_desc()
107 maxsz = (maxsz / 8) - 1; in simd_desc()
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