Lines Matching +full:- +full:16 +full:g

1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
12  * MM IOMMU supports 16GB dma address. We separate it to four ranges:
13  * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16  * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
20  * modules    dma-address-region	larbs-ports
21  * disp         0 ~ 4G                  larb0/1/2/3
22  * vcodec      4G ~ 8G                  larb19/20/21/22/23/24
23  * cam/mdp     8G ~ 12G                 the other larbs.
24  * N/A         12G ~ 16G
29  * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30  * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
116 #define M4U_PORT_L9_IMG_TNCSTO_T1_A		MTK_M4U_ID(9, 16)
138 #define M4U_PORT_L10_IMG_IMG4O_D1_A		MTK_M4U_ID(10, 16)
203 #define M4U_PORT_L16_CAM_IMGO_R1		MTK_M4U_ID(16, 0)
204 #define M4U_PORT_L16_CAM_CQI_R1			MTK_M4U_ID(16, 1)
205 #define M4U_PORT_L16_CAM_CQI_R2			MTK_M4U_ID(16, 2)
206 #define M4U_PORT_L16_CAM_BPCI_R1		MTK_M4U_ID(16, 3)
207 #define M4U_PORT_L16_CAM_LSCI_R1		MTK_M4U_ID(16, 4)
208 #define M4U_PORT_L16_CAM_RAWI_R2		MTK_M4U_ID(16, 5)
209 #define M4U_PORT_L16_CAM_RAWI_R3		MTK_M4U_ID(16, 6)
210 #define M4U_PORT_L16_CAM_UFDI_R2		MTK_M4U_ID(16, 7)
211 #define M4U_PORT_L16_CAM_UFDI_R3		MTK_M4U_ID(16, 8)
212 #define M4U_PORT_L16_CAM_RAWI_R4		MTK_M4U_ID(16, 9)
213 #define M4U_PORT_L16_CAM_RAWI_R5		MTK_M4U_ID(16, 10)
214 #define M4U_PORT_L16_CAM_AAI_R1			MTK_M4U_ID(16, 11)
215 #define M4U_PORT_L16_CAM_FHO_R1			MTK_M4U_ID(16, 12)
216 #define M4U_PORT_L16_CAM_AAO_R1			MTK_M4U_ID(16, 13)
217 #define M4U_PORT_L16_CAM_TSFSO_R1		MTK_M4U_ID(16, 14)
218 #define M4U_PORT_L16_CAM_FLKO_R1		MTK_M4U_ID(16, 15)
252 #define M4U_PORT_L19_VENC_NBM_WDMA_LITE		MTK_M4U_ID(19, 16)
281 #define M4U_PORT_L20_VENC_NBM_WDMA_LITE		MTK_M4U_ID(20, 16)
392 #define IOMMU_PORT_INFRA_PCIE1			MTK_IFAIOMMU_PERI_ID(16)