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Searched defs:XCHAL_RESET_VECTOR1_VADDR (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h318 #define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 macro
/openbmc/qemu/target/xtensa/
H A Doverlay_tool.h80 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h340 #define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h339 #define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h338 #define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h398 #define XCHAL_RESET_VECTOR1_VADDR 0x40000080 macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h374 #define XCHAL_RESET_VECTOR1_VADDR 0xFFFF1000 macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h390 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h389 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h368 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h390 #define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h430 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h473 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h494 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h473 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h472 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h472 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h508 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h529 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h611 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 macro