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Searched defs:XCHAL_RESET_VECTOR0_VADDR (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h316 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/
H A Doverlay_tool.h76 #define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h338 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h337 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h336 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h396 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h372 #define XCHAL_RESET_VECTOR0_VADDR 0x5FFE0000 macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h388 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h387 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h366 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h388 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h428 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h471 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h492 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h471 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h470 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h470 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h506 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h527 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h609 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 macro