[update] refactor PHY training result dump

[update] add configs for DDR4_800 and 1600

[update] overwrite phy refresh setting according to
the current speed

[update] DDR4 can run on 1600

fpga: rename Aspeed FPGA Kconfig

use generic Kconfig name for Aspeed FPGA support

fpga: add AST2600 support

1. add Kconfig option for ast2600 FPGA support
2. guard the ast2600 FPGA-dedicated code with the new option
> FPGA timer init
> FPGA sdram init

Merge branch 'ryan_port' into aspeed-dev-v2019.04

[update] revise ast2600 default DRAM config

[update] set default GUC 1600M setting
as the default DDR PHY table

[update] copy MRS to PHY registers

[update] add PHY tables

update wdt for ast2500/ast2600

[update] speed up dram init time

[update] calculate DRAM size even if
SDRAM is initialized

[update] check handshake bit for SDRAM init
on ast2500

[update] examin strap to know if SDRAM has
been initialized.

1. for ast2600, check if SCU100[6]==1 (SDRAM has been initialized) or
not.
2. refactor format

update ast2600 sdram enable reset

update for reset and clk

[update] ast2600 SDRAM C driver ready.

[update] add sdrammc test mode and FPGA settings

[update] revise PHY data struct. Use address offset instead of array.

[update] revise DDR4 init flow

[update] refine ast2600 sdram phy init

[update] add ast2600 sdrammc common init

[update] rename SDRAM_PCR to MCR34 (follow the naming rule in datasheet)