1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 * 9 * Synced from Linux v4.19 10 */ 11 12 #include <common.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/sizes.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/spi-nor.h> 21 #include <spi-mem.h> 22 #include <spi.h> 23 24 #include "sf_internal.h" 25 26 /* Define max times to check status register before we give up. */ 27 28 /* 29 * For everything but full-chip erase; probably could be much smaller, but kept 30 * around for safety for now 31 */ 32 33 #define HZ CONFIG_SYS_HZ 34 35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 36 37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op 38 *op, void *buf) 39 { 40 if (op->data.dir == SPI_MEM_DATA_IN) 41 op->data.buf.in = buf; 42 else 43 op->data.buf.out = buf; 44 return spi_mem_exec_op(nor->spi, op); 45 } 46 47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) 48 { 49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), 50 SPI_MEM_OP_NO_ADDR, 51 SPI_MEM_OP_NO_DUMMY, 52 SPI_MEM_OP_DATA_IN(len, NULL, 1)); 53 int ret; 54 55 ret = spi_nor_read_write_reg(nor, &op, val); 56 if (ret < 0) 57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret, 58 code); 59 60 return ret; 61 } 62 63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) 64 { 65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), 66 SPI_MEM_OP_NO_ADDR, 67 SPI_MEM_OP_NO_DUMMY, 68 SPI_MEM_OP_DATA_OUT(len, NULL, 1)); 69 70 return spi_nor_read_write_reg(nor, &op, buf); 71 } 72 73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 74 u_char *buf) 75 { 76 struct spi_mem_op op = 77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 80 SPI_MEM_OP_DATA_IN(len, buf, 1)); 81 size_t remaining = len; 82 int ret; 83 84 /* get transfer protocols. */ 85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 87 op.dummy.buswidth = op.addr.buswidth; 88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 89 90 /* convert the dummy cycles to the number of bytes */ 91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 92 93 while (remaining) { 94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 95 ret = spi_mem_adjust_op_size(nor->spi, &op); 96 if (ret) 97 return ret; 98 99 ret = spi_mem_exec_op(nor->spi, &op); 100 if (ret) 101 return ret; 102 103 op.addr.val += op.data.nbytes; 104 remaining -= op.data.nbytes; 105 op.data.buf.in += op.data.nbytes; 106 } 107 108 return len; 109 } 110 111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 112 const u_char *buf) 113 { 114 struct spi_mem_op op = 115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 117 SPI_MEM_OP_NO_DUMMY, 118 SPI_MEM_OP_DATA_OUT(len, buf, 1)); 119 size_t remaining = len; 120 int ret; 121 122 /* get transfer protocols. */ 123 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 124 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 125 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 126 127 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 128 op.addr.nbytes = 0; 129 130 while (remaining) { 131 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 132 ret = spi_mem_adjust_op_size(nor->spi, &op); 133 if (ret) 134 return ret; 135 136 ret = spi_mem_exec_op(nor->spi, &op); 137 if (ret) 138 return ret; 139 140 op.addr.val += op.data.nbytes; 141 remaining -= op.data.nbytes; 142 op.data.buf.out += op.data.nbytes; 143 } 144 145 return len; 146 } 147 148 /* 149 * Read the status register, returning its value in the location 150 * Return the status register value. 151 * Returns negative if error occurred. 152 */ 153 static int read_sr(struct spi_nor *nor) 154 { 155 int ret; 156 u8 val; 157 158 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); 159 if (ret < 0) { 160 pr_debug("error %d reading SR\n", (int)ret); 161 return ret; 162 } 163 164 return val; 165 } 166 167 /* 168 * Read the flag status register, returning its value in the location 169 * Return the status register value. 170 * Returns negative if error occurred. 171 */ 172 static int read_fsr(struct spi_nor *nor) 173 { 174 int ret; 175 u8 val; 176 177 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); 178 if (ret < 0) { 179 pr_debug("error %d reading FSR\n", ret); 180 return ret; 181 } 182 183 return val; 184 } 185 186 /* 187 * Read configuration register, returning its value in the 188 * location. Return the configuration register value. 189 * Returns negative if error occurred. 190 */ 191 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 192 static int read_cr(struct spi_nor *nor) 193 { 194 int ret; 195 u8 val; 196 197 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); 198 if (ret < 0) { 199 dev_dbg(nor->dev, "error %d reading CR\n", ret); 200 return ret; 201 } 202 203 return val; 204 } 205 #endif 206 207 /* 208 * Write status register 1 byte 209 * Returns negative if error occurred. 210 */ 211 static int write_sr(struct spi_nor *nor, u8 val) 212 { 213 nor->cmd_buf[0] = val; 214 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); 215 } 216 217 /* 218 * Set write enable latch with Write Enable command. 219 * Returns negative if error occurred. 220 */ 221 static int write_enable(struct spi_nor *nor) 222 { 223 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); 224 } 225 226 /* 227 * Send write disable instruction to the chip. 228 */ 229 static int write_disable(struct spi_nor *nor) 230 { 231 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); 232 } 233 234 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 235 { 236 return mtd->priv; 237 } 238 239 #ifndef CONFIG_SPI_FLASH_BAR 240 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 241 { 242 size_t i; 243 244 for (i = 0; i < size; i++) 245 if (table[i][0] == opcode) 246 return table[i][1]; 247 248 /* No conversion found, keep input op code. */ 249 return opcode; 250 } 251 252 static u8 spi_nor_convert_3to4_read(u8 opcode) 253 { 254 static const u8 spi_nor_3to4_read[][2] = { 255 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 256 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 257 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 258 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 259 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 260 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 261 262 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 263 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 264 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 265 }; 266 267 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 268 ARRAY_SIZE(spi_nor_3to4_read)); 269 } 270 271 static u8 spi_nor_convert_3to4_program(u8 opcode) 272 { 273 static const u8 spi_nor_3to4_program[][2] = { 274 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 275 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 276 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 277 }; 278 279 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 280 ARRAY_SIZE(spi_nor_3to4_program)); 281 } 282 283 static u8 spi_nor_convert_3to4_erase(u8 opcode) 284 { 285 static const u8 spi_nor_3to4_erase[][2] = { 286 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 287 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 288 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 289 }; 290 291 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 292 ARRAY_SIZE(spi_nor_3to4_erase)); 293 } 294 295 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, 296 const struct flash_info *info) 297 { 298 /* Do some manufacturer fixups first */ 299 switch (JEDEC_MFR(info)) { 300 case SNOR_MFR_SPANSION: 301 /* No small sector erase for 4-byte command set */ 302 nor->erase_opcode = SPINOR_OP_SE; 303 nor->mtd.erasesize = info->sector_size; 304 break; 305 306 default: 307 break; 308 } 309 310 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 311 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 312 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 313 } 314 #endif /* !CONFIG_SPI_FLASH_BAR */ 315 316 /* Enable/disable 4-byte addressing mode. */ 317 static int set_4byte(struct spi_nor *nor, const struct flash_info *info, 318 int enable) 319 { 320 int status; 321 bool need_wren = false; 322 u8 cmd; 323 324 switch (JEDEC_MFR(info)) { 325 case SNOR_MFR_ST: 326 case SNOR_MFR_MICRON: 327 /* Some Micron need WREN command; all will accept it */ 328 need_wren = true; 329 case SNOR_MFR_MACRONIX: 330 case SNOR_MFR_WINBOND: 331 case SNOR_MFR_GIGADEVICE: 332 if (need_wren) 333 write_enable(nor); 334 335 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 336 status = nor->write_reg(nor, cmd, NULL, 0); 337 if (need_wren) 338 write_disable(nor); 339 340 if (!status && !enable && 341 JEDEC_MFR(info) == SNOR_MFR_WINBOND) { 342 /* 343 * On Winbond W25Q256FV, leaving 4byte mode causes 344 * the Extended Address Register to be set to 1, so all 345 * 3-byte-address reads come from the second 16M. 346 * We must clear the register to enable normal behavior. 347 */ 348 write_enable(nor); 349 nor->cmd_buf[0] = 0; 350 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1); 351 write_disable(nor); 352 } 353 354 return status; 355 default: 356 /* Spansion style */ 357 nor->cmd_buf[0] = enable << 7; 358 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); 359 } 360 } 361 362 static int spi_nor_sr_ready(struct spi_nor *nor) 363 { 364 int sr = read_sr(nor); 365 366 if (sr < 0) 367 return sr; 368 369 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) { 370 if (sr & SR_E_ERR) 371 dev_dbg(nor->dev, "Erase Error occurred\n"); 372 else 373 dev_dbg(nor->dev, "Programming Error occurred\n"); 374 375 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); 376 return -EIO; 377 } 378 379 return !(sr & SR_WIP); 380 } 381 382 static int spi_nor_fsr_ready(struct spi_nor *nor) 383 { 384 int fsr = read_fsr(nor); 385 386 if (fsr < 0) 387 return fsr; 388 389 if (fsr & (FSR_E_ERR | FSR_P_ERR)) { 390 if (fsr & FSR_E_ERR) 391 dev_dbg(nor->dev, "Erase operation failed.\n"); 392 else 393 dev_dbg(nor->dev, "Program operation failed.\n"); 394 395 if (fsr & FSR_PT_ERR) 396 dev_dbg(nor->dev, 397 "Attempted to modify a protected sector.\n"); 398 399 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); 400 return -EIO; 401 } 402 403 return fsr & FSR_READY; 404 } 405 406 static int spi_nor_ready(struct spi_nor *nor) 407 { 408 int sr, fsr; 409 410 sr = spi_nor_sr_ready(nor); 411 if (sr < 0) 412 return sr; 413 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 414 if (fsr < 0) 415 return fsr; 416 return sr && fsr; 417 } 418 419 /* 420 * Service routine to read status register until ready, or timeout occurs. 421 * Returns non-zero if error. 422 */ 423 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 424 unsigned long timeout) 425 { 426 unsigned long timebase; 427 int ret; 428 429 timebase = get_timer(0); 430 431 while (get_timer(timebase) < timeout) { 432 ret = spi_nor_ready(nor); 433 if (ret < 0) 434 return ret; 435 if (ret) 436 return 0; 437 } 438 439 dev_err(nor->dev, "flash operation timed out\n"); 440 441 return -ETIMEDOUT; 442 } 443 444 static int spi_nor_wait_till_ready(struct spi_nor *nor) 445 { 446 return spi_nor_wait_till_ready_with_timeout(nor, 447 DEFAULT_READY_WAIT_JIFFIES); 448 } 449 450 #ifdef CONFIG_SPI_FLASH_BAR 451 /* 452 * This "clean_bar" is necessary in a situation when one was accessing 453 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 454 * 455 * After it the BA24 bit shall be cleared to allow access to correct 456 * memory region after SW reset (by calling "reset" command). 457 * 458 * Otherwise, the BA24 bit may be left set and then after reset, the 459 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 460 */ 461 static int clean_bar(struct spi_nor *nor) 462 { 463 u8 cmd, bank_sel = 0; 464 465 if (nor->bank_curr == 0) 466 return 0; 467 cmd = nor->bank_write_cmd; 468 nor->bank_curr = 0; 469 write_enable(nor); 470 471 return nor->write_reg(nor, cmd, &bank_sel, 1); 472 } 473 474 static int write_bar(struct spi_nor *nor, u32 offset) 475 { 476 u8 cmd, bank_sel; 477 int ret; 478 479 bank_sel = offset / SZ_16M; 480 if (bank_sel == nor->bank_curr) 481 goto bar_end; 482 483 cmd = nor->bank_write_cmd; 484 write_enable(nor); 485 ret = nor->write_reg(nor, cmd, &bank_sel, 1); 486 if (ret < 0) { 487 debug("SF: fail to write bank register\n"); 488 return ret; 489 } 490 491 bar_end: 492 nor->bank_curr = bank_sel; 493 return nor->bank_curr; 494 } 495 496 static int read_bar(struct spi_nor *nor, const struct flash_info *info) 497 { 498 u8 curr_bank = 0; 499 int ret; 500 501 switch (JEDEC_MFR(info)) { 502 case SNOR_MFR_SPANSION: 503 nor->bank_read_cmd = SPINOR_OP_BRRD; 504 nor->bank_write_cmd = SPINOR_OP_BRWR; 505 break; 506 default: 507 nor->bank_read_cmd = SPINOR_OP_RDEAR; 508 nor->bank_write_cmd = SPINOR_OP_WREAR; 509 } 510 511 ret = nor->read_reg(nor, nor->bank_read_cmd, 512 &curr_bank, 1); 513 if (ret) { 514 debug("SF: fail to read bank addr register\n"); 515 return ret; 516 } 517 nor->bank_curr = curr_bank; 518 519 return 0; 520 } 521 #endif 522 523 /* 524 * Initiate the erasure of a single sector 525 */ 526 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 527 { 528 u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; 529 int i; 530 531 if (nor->erase) 532 return nor->erase(nor, addr); 533 534 /* 535 * Default implementation, if driver doesn't have a specialized HW 536 * control 537 */ 538 for (i = nor->addr_width - 1; i >= 0; i--) { 539 buf[i] = addr & 0xff; 540 addr >>= 8; 541 } 542 543 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); 544 } 545 546 /* 547 * Erase an address range on the nor chip. The address range may extend 548 * one or more erase sectors. Return an error is there is a problem erasing. 549 */ 550 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 551 { 552 struct spi_nor *nor = mtd_to_spi_nor(mtd); 553 u32 addr, len, rem; 554 int ret; 555 556 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 557 (long long)instr->len); 558 559 div_u64_rem(instr->len, mtd->erasesize, &rem); 560 if (rem) 561 return -EINVAL; 562 563 addr = instr->addr; 564 len = instr->len; 565 566 while (len) { 567 #ifdef CONFIG_SPI_FLASH_BAR 568 ret = write_bar(nor, addr); 569 if (ret < 0) 570 return ret; 571 #endif 572 write_enable(nor); 573 574 ret = spi_nor_erase_sector(nor, addr); 575 if (ret) 576 goto erase_err; 577 578 addr += mtd->erasesize; 579 len -= mtd->erasesize; 580 581 ret = spi_nor_wait_till_ready(nor); 582 if (ret) 583 goto erase_err; 584 } 585 586 erase_err: 587 #ifdef CONFIG_SPI_FLASH_BAR 588 ret = clean_bar(nor); 589 #endif 590 write_disable(nor); 591 592 return ret; 593 } 594 595 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 596 /* Write status register and ensure bits in mask match written values */ 597 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) 598 { 599 int ret; 600 601 write_enable(nor); 602 ret = write_sr(nor, status_new); 603 if (ret) 604 return ret; 605 606 ret = spi_nor_wait_till_ready(nor); 607 if (ret) 608 return ret; 609 610 ret = read_sr(nor); 611 if (ret < 0) 612 return ret; 613 614 return ((ret & mask) != (status_new & mask)) ? -EIO : 0; 615 } 616 617 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 618 uint64_t *len) 619 { 620 struct mtd_info *mtd = &nor->mtd; 621 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 622 int shift = ffs(mask) - 1; 623 int pow; 624 625 if (!(sr & mask)) { 626 /* No protection */ 627 *ofs = 0; 628 *len = 0; 629 } else { 630 pow = ((sr & mask) ^ mask) >> shift; 631 *len = mtd->size >> pow; 632 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) 633 *ofs = 0; 634 else 635 *ofs = mtd->size - *len; 636 } 637 } 638 639 /* 640 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 641 * @locked is false); 0 otherwise 642 */ 643 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len, 644 u8 sr, bool locked) 645 { 646 loff_t lock_offs; 647 uint64_t lock_len; 648 649 if (!len) 650 return 1; 651 652 stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 653 654 if (locked) 655 /* Requested range is a sub-range of locked range */ 656 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 657 else 658 /* Requested range does not overlap with locked range */ 659 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 660 } 661 662 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 663 u8 sr) 664 { 665 return stm_check_lock_status_sr(nor, ofs, len, sr, true); 666 } 667 668 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 669 u8 sr) 670 { 671 return stm_check_lock_status_sr(nor, ofs, len, sr, false); 672 } 673 674 /* 675 * Lock a region of the flash. Compatible with ST Micro and similar flash. 676 * Supports the block protection bits BP{0,1,2} in the status register 677 * (SR). Does not support these features found in newer SR bitfields: 678 * - SEC: sector/block protect - only handle SEC=0 (block protect) 679 * - CMP: complement protect - only support CMP=0 (range is not complemented) 680 * 681 * Support for the following is provided conditionally for some flash: 682 * - TB: top/bottom protect 683 * 684 * Sample table portion for 8MB flash (Winbond w25q64fw): 685 * 686 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 687 * -------------------------------------------------------------------------- 688 * X | X | 0 | 0 | 0 | NONE | NONE 689 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 690 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 691 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 692 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 693 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 694 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 695 * X | X | 1 | 1 | 1 | 8 MB | ALL 696 * ------|-------|-------|-------|-------|---------------|------------------- 697 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 698 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 699 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 700 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 701 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 702 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 703 * 704 * Returns negative on errors, 0 on success. 705 */ 706 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 707 { 708 struct mtd_info *mtd = &nor->mtd; 709 int status_old, status_new; 710 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 711 u8 shift = ffs(mask) - 1, pow, val; 712 loff_t lock_len; 713 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 714 bool use_top; 715 716 status_old = read_sr(nor); 717 if (status_old < 0) 718 return status_old; 719 720 /* If nothing in our range is unlocked, we don't need to do anything */ 721 if (stm_is_locked_sr(nor, ofs, len, status_old)) 722 return 0; 723 724 /* If anything below us is unlocked, we can't use 'bottom' protection */ 725 if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 726 can_be_bottom = false; 727 728 /* If anything above us is unlocked, we can't use 'top' protection */ 729 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 730 status_old)) 731 can_be_top = false; 732 733 if (!can_be_bottom && !can_be_top) 734 return -EINVAL; 735 736 /* Prefer top, if both are valid */ 737 use_top = can_be_top; 738 739 /* lock_len: length of region that should end up locked */ 740 if (use_top) 741 lock_len = mtd->size - ofs; 742 else 743 lock_len = ofs + len; 744 745 /* 746 * Need smallest pow such that: 747 * 748 * 1 / (2^pow) <= (len / size) 749 * 750 * so (assuming power-of-2 size) we do: 751 * 752 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 753 */ 754 pow = ilog2(mtd->size) - ilog2(lock_len); 755 val = mask - (pow << shift); 756 if (val & ~mask) 757 return -EINVAL; 758 /* Don't "lock" with no region! */ 759 if (!(val & mask)) 760 return -EINVAL; 761 762 status_new = (status_old & ~mask & ~SR_TB) | val; 763 764 /* Disallow further writes if WP pin is asserted */ 765 status_new |= SR_SRWD; 766 767 if (!use_top) 768 status_new |= SR_TB; 769 770 /* Don't bother if they're the same */ 771 if (status_new == status_old) 772 return 0; 773 774 /* Only modify protection if it will not unlock other areas */ 775 if ((status_new & mask) < (status_old & mask)) 776 return -EINVAL; 777 778 return write_sr_and_check(nor, status_new, mask); 779 } 780 781 /* 782 * Unlock a region of the flash. See stm_lock() for more info 783 * 784 * Returns negative on errors, 0 on success. 785 */ 786 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 787 { 788 struct mtd_info *mtd = &nor->mtd; 789 int status_old, status_new; 790 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 791 u8 shift = ffs(mask) - 1, pow, val; 792 loff_t lock_len; 793 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 794 bool use_top; 795 796 status_old = read_sr(nor); 797 if (status_old < 0) 798 return status_old; 799 800 /* If nothing in our range is locked, we don't need to do anything */ 801 if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 802 return 0; 803 804 /* If anything below us is locked, we can't use 'top' protection */ 805 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 806 can_be_top = false; 807 808 /* If anything above us is locked, we can't use 'bottom' protection */ 809 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 810 status_old)) 811 can_be_bottom = false; 812 813 if (!can_be_bottom && !can_be_top) 814 return -EINVAL; 815 816 /* Prefer top, if both are valid */ 817 use_top = can_be_top; 818 819 /* lock_len: length of region that should remain locked */ 820 if (use_top) 821 lock_len = mtd->size - (ofs + len); 822 else 823 lock_len = ofs; 824 825 /* 826 * Need largest pow such that: 827 * 828 * 1 / (2^pow) >= (len / size) 829 * 830 * so (assuming power-of-2 size) we do: 831 * 832 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 833 */ 834 pow = ilog2(mtd->size) - order_base_2(lock_len); 835 if (lock_len == 0) { 836 val = 0; /* fully unlocked */ 837 } else { 838 val = mask - (pow << shift); 839 /* Some power-of-two sizes are not supported */ 840 if (val & ~mask) 841 return -EINVAL; 842 } 843 844 status_new = (status_old & ~mask & ~SR_TB) | val; 845 846 /* Don't protect status register if we're fully unlocked */ 847 if (lock_len == 0) 848 status_new &= ~SR_SRWD; 849 850 if (!use_top) 851 status_new |= SR_TB; 852 853 /* Don't bother if they're the same */ 854 if (status_new == status_old) 855 return 0; 856 857 /* Only modify protection if it will not lock other areas */ 858 if ((status_new & mask) > (status_old & mask)) 859 return -EINVAL; 860 861 return write_sr_and_check(nor, status_new, mask); 862 } 863 864 /* 865 * Check if a region of the flash is (completely) locked. See stm_lock() for 866 * more info. 867 * 868 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 869 * negative on errors. 870 */ 871 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 872 { 873 int status; 874 875 status = read_sr(nor); 876 if (status < 0) 877 return status; 878 879 return stm_is_locked_sr(nor, ofs, len, status); 880 } 881 #endif /* CONFIG_SPI_FLASH_STMICRO */ 882 883 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 884 { 885 int tmp; 886 u8 id[SPI_NOR_MAX_ID_LEN]; 887 const struct flash_info *info; 888 889 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); 890 if (tmp < 0) { 891 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 892 return ERR_PTR(tmp); 893 } 894 895 info = spi_nor_ids; 896 for (; info->name; info++) { 897 if (info->id_len) { 898 if (!memcmp(info->id, id, info->id_len)) 899 return info; 900 } 901 } 902 903 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 904 id[0], id[1], id[2]); 905 return ERR_PTR(-ENODEV); 906 } 907 908 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 909 size_t *retlen, u_char *buf) 910 { 911 struct spi_nor *nor = mtd_to_spi_nor(mtd); 912 int ret; 913 914 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 915 916 while (len) { 917 loff_t addr = from; 918 size_t read_len = len; 919 920 #ifdef CONFIG_SPI_FLASH_BAR 921 u32 remain_len; 922 923 ret = write_bar(nor, addr); 924 if (ret < 0) 925 return log_ret(ret); 926 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr; 927 928 if (len < remain_len) 929 read_len = len; 930 else 931 read_len = remain_len; 932 #endif 933 934 ret = nor->read(nor, addr, read_len, buf); 935 if (ret == 0) { 936 /* We shouldn't see 0-length reads */ 937 ret = -EIO; 938 goto read_err; 939 } 940 if (ret < 0) 941 goto read_err; 942 943 *retlen += ret; 944 buf += ret; 945 from += ret; 946 len -= ret; 947 } 948 ret = 0; 949 950 read_err: 951 #ifdef CONFIG_SPI_FLASH_BAR 952 ret = clean_bar(nor); 953 #endif 954 return ret; 955 } 956 957 #ifdef CONFIG_SPI_FLASH_SST 958 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, 959 size_t *retlen, const u_char *buf) 960 { 961 size_t actual; 962 int ret = 0; 963 964 for (actual = 0; actual < len; actual++) { 965 nor->program_opcode = SPINOR_OP_BP; 966 967 write_enable(nor); 968 /* write one byte. */ 969 ret = nor->write(nor, to, 1, buf + actual); 970 if (ret < 0) 971 goto sst_write_err; 972 ret = spi_nor_wait_till_ready(nor); 973 if (ret) 974 goto sst_write_err; 975 to++; 976 } 977 978 sst_write_err: 979 write_disable(nor); 980 return ret; 981 } 982 983 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 984 size_t *retlen, const u_char *buf) 985 { 986 struct spi_nor *nor = mtd_to_spi_nor(mtd); 987 struct spi_slave *spi = nor->spi; 988 size_t actual; 989 int ret; 990 991 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 992 if (spi->mode & SPI_TX_BYTE) 993 return sst_write_byteprogram(nor, to, len, retlen, buf); 994 995 write_enable(nor); 996 997 nor->sst_write_second = false; 998 999 actual = to % 2; 1000 /* Start write from odd address. */ 1001 if (actual) { 1002 nor->program_opcode = SPINOR_OP_BP; 1003 1004 /* write one byte. */ 1005 ret = nor->write(nor, to, 1, buf); 1006 if (ret < 0) 1007 goto sst_write_err; 1008 ret = spi_nor_wait_till_ready(nor); 1009 if (ret) 1010 goto sst_write_err; 1011 } 1012 to += actual; 1013 1014 /* Write out most of the data here. */ 1015 for (; actual < len - 1; actual += 2) { 1016 nor->program_opcode = SPINOR_OP_AAI_WP; 1017 1018 /* write two bytes. */ 1019 ret = nor->write(nor, to, 2, buf + actual); 1020 if (ret < 0) 1021 goto sst_write_err; 1022 ret = spi_nor_wait_till_ready(nor); 1023 if (ret) 1024 goto sst_write_err; 1025 to += 2; 1026 nor->sst_write_second = true; 1027 } 1028 nor->sst_write_second = false; 1029 1030 write_disable(nor); 1031 ret = spi_nor_wait_till_ready(nor); 1032 if (ret) 1033 goto sst_write_err; 1034 1035 /* Write out trailing byte if it exists. */ 1036 if (actual != len) { 1037 write_enable(nor); 1038 1039 nor->program_opcode = SPINOR_OP_BP; 1040 ret = nor->write(nor, to, 1, buf + actual); 1041 if (ret < 0) 1042 goto sst_write_err; 1043 ret = spi_nor_wait_till_ready(nor); 1044 if (ret) 1045 goto sst_write_err; 1046 write_disable(nor); 1047 actual += 1; 1048 } 1049 sst_write_err: 1050 *retlen += actual; 1051 return ret; 1052 } 1053 #endif 1054 /* 1055 * Write an address range to the nor chip. Data must be written in 1056 * FLASH_PAGESIZE chunks. The address range may be any size provided 1057 * it is within the physical boundaries. 1058 */ 1059 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1060 size_t *retlen, const u_char *buf) 1061 { 1062 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1063 size_t page_offset, page_remain, i; 1064 ssize_t ret; 1065 1066 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1067 1068 for (i = 0; i < len; ) { 1069 ssize_t written; 1070 loff_t addr = to + i; 1071 1072 /* 1073 * If page_size is a power of two, the offset can be quickly 1074 * calculated with an AND operation. On the other cases we 1075 * need to do a modulus operation (more expensive). 1076 * Power of two numbers have only one bit set and we can use 1077 * the instruction hweight32 to detect if we need to do a 1078 * modulus (do_div()) or not. 1079 */ 1080 if (hweight32(nor->page_size) == 1) { 1081 page_offset = addr & (nor->page_size - 1); 1082 } else { 1083 u64 aux = addr; 1084 1085 page_offset = do_div(aux, nor->page_size); 1086 } 1087 /* the size of data remaining on the first page */ 1088 page_remain = min_t(size_t, 1089 nor->page_size - page_offset, len - i); 1090 1091 #ifdef CONFIG_SPI_FLASH_BAR 1092 ret = write_bar(nor, addr); 1093 if (ret < 0) 1094 return ret; 1095 #endif 1096 write_enable(nor); 1097 ret = nor->write(nor, addr, page_remain, buf + i); 1098 if (ret < 0) 1099 goto write_err; 1100 written = ret; 1101 1102 ret = spi_nor_wait_till_ready(nor); 1103 if (ret) 1104 goto write_err; 1105 *retlen += written; 1106 i += written; 1107 if (written != page_remain) { 1108 ret = -EIO; 1109 goto write_err; 1110 } 1111 } 1112 1113 write_err: 1114 #ifdef CONFIG_SPI_FLASH_BAR 1115 ret = clean_bar(nor); 1116 #endif 1117 return ret; 1118 } 1119 1120 #ifdef CONFIG_SPI_FLASH_MACRONIX 1121 /** 1122 * macronix_quad_enable() - set QE bit in Status Register. 1123 * @nor: pointer to a 'struct spi_nor' 1124 * 1125 * Set the Quad Enable (QE) bit in the Status Register. 1126 * 1127 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. 1128 * 1129 * Return: 0 on success, -errno otherwise. 1130 */ 1131 static int macronix_quad_enable(struct spi_nor *nor) 1132 { 1133 int ret, val; 1134 1135 val = read_sr(nor); 1136 if (val < 0) 1137 return val; 1138 if (val & SR_QUAD_EN_MX) 1139 return 0; 1140 1141 write_enable(nor); 1142 1143 write_sr(nor, val | SR_QUAD_EN_MX); 1144 1145 ret = spi_nor_wait_till_ready(nor); 1146 if (ret) 1147 return ret; 1148 1149 ret = read_sr(nor); 1150 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { 1151 dev_err(nor->dev, "Macronix Quad bit not set\n"); 1152 return -EINVAL; 1153 } 1154 1155 return 0; 1156 } 1157 #endif 1158 1159 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1160 /* 1161 * Write status Register and configuration register with 2 bytes 1162 * The first byte will be written to the status register, while the 1163 * second byte will be written to the configuration register. 1164 * Return negative if error occurred. 1165 */ 1166 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 1167 { 1168 int ret; 1169 1170 write_enable(nor); 1171 1172 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); 1173 if (ret < 0) { 1174 dev_dbg(nor->dev, 1175 "error while writing configuration register\n"); 1176 return -EINVAL; 1177 } 1178 1179 ret = spi_nor_wait_till_ready(nor); 1180 if (ret) { 1181 dev_dbg(nor->dev, 1182 "timeout while writing configuration register\n"); 1183 return ret; 1184 } 1185 1186 return 0; 1187 } 1188 1189 /** 1190 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. 1191 * @nor: pointer to a 'struct spi_nor' 1192 * 1193 * Set the Quad Enable (QE) bit in the Configuration Register. 1194 * This function should be used with QSPI memories supporting the Read 1195 * Configuration Register (35h) instruction. 1196 * 1197 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1198 * memories. 1199 * 1200 * Return: 0 on success, -errno otherwise. 1201 */ 1202 static int spansion_read_cr_quad_enable(struct spi_nor *nor) 1203 { 1204 u8 sr_cr[2]; 1205 int ret; 1206 1207 /* Check current Quad Enable bit value. */ 1208 ret = read_cr(nor); 1209 if (ret < 0) { 1210 dev_dbg(dev, "error while reading configuration register\n"); 1211 return -EINVAL; 1212 } 1213 1214 if (ret & CR_QUAD_EN_SPAN) 1215 return 0; 1216 1217 sr_cr[1] = ret | CR_QUAD_EN_SPAN; 1218 1219 /* Keep the current value of the Status Register. */ 1220 ret = read_sr(nor); 1221 if (ret < 0) { 1222 dev_dbg(dev, "error while reading status register\n"); 1223 return -EINVAL; 1224 } 1225 sr_cr[0] = ret; 1226 1227 ret = write_sr_cr(nor, sr_cr); 1228 if (ret) 1229 return ret; 1230 1231 /* Read back and check it. */ 1232 ret = read_cr(nor); 1233 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { 1234 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); 1235 return -EINVAL; 1236 } 1237 1238 return 0; 1239 } 1240 1241 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1242 /** 1243 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. 1244 * @nor: pointer to a 'struct spi_nor' 1245 * 1246 * Set the Quad Enable (QE) bit in the Configuration Register. 1247 * This function should be used with QSPI memories not supporting the Read 1248 * Configuration Register (35h) instruction. 1249 * 1250 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1251 * memories. 1252 * 1253 * Return: 0 on success, -errno otherwise. 1254 */ 1255 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) 1256 { 1257 u8 sr_cr[2]; 1258 int ret; 1259 1260 /* Keep the current value of the Status Register. */ 1261 ret = read_sr(nor); 1262 if (ret < 0) { 1263 dev_dbg(nor->dev, "error while reading status register\n"); 1264 return -EINVAL; 1265 } 1266 sr_cr[0] = ret; 1267 sr_cr[1] = CR_QUAD_EN_SPAN; 1268 1269 return write_sr_cr(nor, sr_cr); 1270 } 1271 1272 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ 1273 #endif /* CONFIG_SPI_FLASH_SPANSION */ 1274 1275 struct spi_nor_read_command { 1276 u8 num_mode_clocks; 1277 u8 num_wait_states; 1278 u8 opcode; 1279 enum spi_nor_protocol proto; 1280 }; 1281 1282 struct spi_nor_pp_command { 1283 u8 opcode; 1284 enum spi_nor_protocol proto; 1285 }; 1286 1287 enum spi_nor_read_command_index { 1288 SNOR_CMD_READ, 1289 SNOR_CMD_READ_FAST, 1290 SNOR_CMD_READ_1_1_1_DTR, 1291 1292 /* Dual SPI */ 1293 SNOR_CMD_READ_1_1_2, 1294 SNOR_CMD_READ_1_2_2, 1295 SNOR_CMD_READ_2_2_2, 1296 SNOR_CMD_READ_1_2_2_DTR, 1297 1298 /* Quad SPI */ 1299 SNOR_CMD_READ_1_1_4, 1300 SNOR_CMD_READ_1_4_4, 1301 SNOR_CMD_READ_4_4_4, 1302 SNOR_CMD_READ_1_4_4_DTR, 1303 1304 /* Octo SPI */ 1305 SNOR_CMD_READ_1_1_8, 1306 SNOR_CMD_READ_1_8_8, 1307 SNOR_CMD_READ_8_8_8, 1308 SNOR_CMD_READ_1_8_8_DTR, 1309 1310 SNOR_CMD_READ_MAX 1311 }; 1312 1313 enum spi_nor_pp_command_index { 1314 SNOR_CMD_PP, 1315 1316 /* Quad SPI */ 1317 SNOR_CMD_PP_1_1_4, 1318 SNOR_CMD_PP_1_4_4, 1319 SNOR_CMD_PP_4_4_4, 1320 1321 /* Octo SPI */ 1322 SNOR_CMD_PP_1_1_8, 1323 SNOR_CMD_PP_1_8_8, 1324 SNOR_CMD_PP_8_8_8, 1325 1326 SNOR_CMD_PP_MAX 1327 }; 1328 1329 struct spi_nor_flash_parameter { 1330 u64 size; 1331 u32 page_size; 1332 1333 struct spi_nor_hwcaps hwcaps; 1334 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 1335 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 1336 1337 int (*quad_enable)(struct spi_nor *nor); 1338 }; 1339 1340 static void 1341 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1342 u8 num_mode_clocks, 1343 u8 num_wait_states, 1344 u8 opcode, 1345 enum spi_nor_protocol proto) 1346 { 1347 read->num_mode_clocks = num_mode_clocks; 1348 read->num_wait_states = num_wait_states; 1349 read->opcode = opcode; 1350 read->proto = proto; 1351 } 1352 1353 static void 1354 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 1355 u8 opcode, 1356 enum spi_nor_protocol proto) 1357 { 1358 pp->opcode = opcode; 1359 pp->proto = proto; 1360 } 1361 1362 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1363 /* 1364 * Serial Flash Discoverable Parameters (SFDP) parsing. 1365 */ 1366 1367 /** 1368 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 1369 * @nor: pointer to a 'struct spi_nor' 1370 * @addr: offset in the SFDP area to start reading data from 1371 * @len: number of bytes to read 1372 * @buf: buffer where the SFDP data are copied into (dma-safe memory) 1373 * 1374 * Whatever the actual numbers of bytes for address and dummy cycles are 1375 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 1376 * followed by a 3-byte address and 8 dummy clock cycles. 1377 * 1378 * Return: 0 on success, -errno otherwise. 1379 */ 1380 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 1381 size_t len, void *buf) 1382 { 1383 u8 addr_width, read_opcode, read_dummy; 1384 int ret; 1385 1386 read_opcode = nor->read_opcode; 1387 addr_width = nor->addr_width; 1388 read_dummy = nor->read_dummy; 1389 1390 nor->read_opcode = SPINOR_OP_RDSFDP; 1391 nor->addr_width = 3; 1392 nor->read_dummy = 8; 1393 1394 while (len) { 1395 ret = nor->read(nor, addr, len, (u8 *)buf); 1396 if (!ret || ret > len) { 1397 ret = -EIO; 1398 goto read_err; 1399 } 1400 if (ret < 0) 1401 goto read_err; 1402 1403 buf += ret; 1404 addr += ret; 1405 len -= ret; 1406 } 1407 ret = 0; 1408 1409 read_err: 1410 nor->read_opcode = read_opcode; 1411 nor->addr_width = addr_width; 1412 nor->read_dummy = read_dummy; 1413 1414 return ret; 1415 } 1416 1417 struct sfdp_parameter_header { 1418 u8 id_lsb; 1419 u8 minor; 1420 u8 major; 1421 u8 length; /* in double words */ 1422 u8 parameter_table_pointer[3]; /* byte address */ 1423 u8 id_msb; 1424 }; 1425 1426 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 1427 #define SFDP_PARAM_HEADER_PTP(p) \ 1428 (((p)->parameter_table_pointer[2] << 16) | \ 1429 ((p)->parameter_table_pointer[1] << 8) | \ 1430 ((p)->parameter_table_pointer[0] << 0)) 1431 1432 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 1433 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 1434 1435 #define SFDP_SIGNATURE 0x50444653U 1436 #define SFDP_JESD216_MAJOR 1 1437 #define SFDP_JESD216_MINOR 0 1438 #define SFDP_JESD216A_MINOR 5 1439 #define SFDP_JESD216B_MINOR 6 1440 1441 struct sfdp_header { 1442 u32 signature; /* Ox50444653U <=> "SFDP" */ 1443 u8 minor; 1444 u8 major; 1445 u8 nph; /* 0-base number of parameter headers */ 1446 u8 unused; 1447 1448 /* Basic Flash Parameter Table. */ 1449 struct sfdp_parameter_header bfpt_header; 1450 }; 1451 1452 /* Basic Flash Parameter Table */ 1453 1454 /* 1455 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 1456 * They are indexed from 1 but C arrays are indexed from 0. 1457 */ 1458 #define BFPT_DWORD(i) ((i) - 1) 1459 #define BFPT_DWORD_MAX 16 1460 1461 /* The first version of JESB216 defined only 9 DWORDs. */ 1462 #define BFPT_DWORD_MAX_JESD216 9 1463 1464 /* 1st DWORD. */ 1465 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 1466 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 1467 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 1468 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 1469 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 1470 #define BFPT_DWORD1_DTR BIT(19) 1471 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 1472 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 1473 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 1474 1475 /* 5th DWORD. */ 1476 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 1477 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 1478 1479 /* 11th DWORD. */ 1480 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 1481 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 1482 1483 /* 15th DWORD. */ 1484 1485 /* 1486 * (from JESD216 rev B) 1487 * Quad Enable Requirements (QER): 1488 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 1489 * reads based on instruction. DQ3/HOLD# functions are hold during 1490 * instruction phase. 1491 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 1492 * two data bytes where bit 1 of the second byte is one. 1493 * [...] 1494 * Writing only one byte to the status register has the side-effect of 1495 * clearing status register 2, including the QE bit. The 100b code is 1496 * used if writing one byte to the status register does not modify 1497 * status register 2. 1498 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 1499 * one data byte where bit 6 is one. 1500 * [...] 1501 * - 011b: QE is bit 7 of status register 2. It is set via Write status 1502 * register 2 instruction 3Eh with one data byte where bit 7 is one. 1503 * [...] 1504 * The status register 2 is read using instruction 3Fh. 1505 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 1506 * two data bytes where bit 1 of the second byte is one. 1507 * [...] 1508 * In contrast to the 001b code, writing one byte to the status 1509 * register does not modify status register 2. 1510 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 1511 * Read Status instruction 05h. Status register2 is read using 1512 * instruction 35h. QE is set via Writ Status instruction 01h with 1513 * two data bytes where bit 1 of the second byte is one. 1514 * [...] 1515 */ 1516 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 1517 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 1518 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 1519 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 1520 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 1521 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 1522 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 1523 1524 struct sfdp_bfpt { 1525 u32 dwords[BFPT_DWORD_MAX]; 1526 }; 1527 1528 /* Fast Read settings. */ 1529 1530 static void 1531 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 1532 u16 half, 1533 enum spi_nor_protocol proto) 1534 { 1535 read->num_mode_clocks = (half >> 5) & 0x07; 1536 read->num_wait_states = (half >> 0) & 0x1f; 1537 read->opcode = (half >> 8) & 0xff; 1538 read->proto = proto; 1539 } 1540 1541 struct sfdp_bfpt_read { 1542 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 1543 u32 hwcaps; 1544 1545 /* 1546 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 1547 * whether the Fast Read x-y-z command is supported. 1548 */ 1549 u32 supported_dword; 1550 u32 supported_bit; 1551 1552 /* 1553 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 1554 * encodes the op code, the number of mode clocks and the number of wait 1555 * states to be used by Fast Read x-y-z command. 1556 */ 1557 u32 settings_dword; 1558 u32 settings_shift; 1559 1560 /* The SPI protocol for this Fast Read x-y-z command. */ 1561 enum spi_nor_protocol proto; 1562 }; 1563 1564 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 1565 /* Fast Read 1-1-2 */ 1566 { 1567 SNOR_HWCAPS_READ_1_1_2, 1568 BFPT_DWORD(1), BIT(16), /* Supported bit */ 1569 BFPT_DWORD(4), 0, /* Settings */ 1570 SNOR_PROTO_1_1_2, 1571 }, 1572 1573 /* Fast Read 1-2-2 */ 1574 { 1575 SNOR_HWCAPS_READ_1_2_2, 1576 BFPT_DWORD(1), BIT(20), /* Supported bit */ 1577 BFPT_DWORD(4), 16, /* Settings */ 1578 SNOR_PROTO_1_2_2, 1579 }, 1580 1581 /* Fast Read 2-2-2 */ 1582 { 1583 SNOR_HWCAPS_READ_2_2_2, 1584 BFPT_DWORD(5), BIT(0), /* Supported bit */ 1585 BFPT_DWORD(6), 16, /* Settings */ 1586 SNOR_PROTO_2_2_2, 1587 }, 1588 1589 /* Fast Read 1-1-4 */ 1590 { 1591 SNOR_HWCAPS_READ_1_1_4, 1592 BFPT_DWORD(1), BIT(22), /* Supported bit */ 1593 BFPT_DWORD(3), 16, /* Settings */ 1594 SNOR_PROTO_1_1_4, 1595 }, 1596 1597 /* Fast Read 1-4-4 */ 1598 { 1599 SNOR_HWCAPS_READ_1_4_4, 1600 BFPT_DWORD(1), BIT(21), /* Supported bit */ 1601 BFPT_DWORD(3), 0, /* Settings */ 1602 SNOR_PROTO_1_4_4, 1603 }, 1604 1605 /* Fast Read 4-4-4 */ 1606 { 1607 SNOR_HWCAPS_READ_4_4_4, 1608 BFPT_DWORD(5), BIT(4), /* Supported bit */ 1609 BFPT_DWORD(7), 16, /* Settings */ 1610 SNOR_PROTO_4_4_4, 1611 }, 1612 }; 1613 1614 struct sfdp_bfpt_erase { 1615 /* 1616 * The half-word at offset <shift> in DWORD <dwoard> encodes the 1617 * op code and erase sector size to be used by Sector Erase commands. 1618 */ 1619 u32 dword; 1620 u32 shift; 1621 }; 1622 1623 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 1624 /* Erase Type 1 in DWORD8 bits[15:0] */ 1625 {BFPT_DWORD(8), 0}, 1626 1627 /* Erase Type 2 in DWORD8 bits[31:16] */ 1628 {BFPT_DWORD(8), 16}, 1629 1630 /* Erase Type 3 in DWORD9 bits[15:0] */ 1631 {BFPT_DWORD(9), 0}, 1632 1633 /* Erase Type 4 in DWORD9 bits[31:16] */ 1634 {BFPT_DWORD(9), 16}, 1635 }; 1636 1637 static int spi_nor_hwcaps_read2cmd(u32 hwcaps); 1638 1639 /** 1640 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 1641 * @nor: pointer to a 'struct spi_nor' 1642 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 1643 * the Basic Flash Parameter Table length and version 1644 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1645 * filled 1646 * 1647 * The Basic Flash Parameter Table is the main and only mandatory table as 1648 * defined by the SFDP (JESD216) specification. 1649 * It provides us with the total size (memory density) of the data array and 1650 * the number of address bytes for Fast Read, Page Program and Sector Erase 1651 * commands. 1652 * For Fast READ commands, it also gives the number of mode clock cycles and 1653 * wait states (regrouped in the number of dummy clock cycles) for each 1654 * supported instruction op code. 1655 * For Page Program, the page size is now available since JESD216 rev A, however 1656 * the supported instruction op codes are still not provided. 1657 * For Sector Erase commands, this table stores the supported instruction op 1658 * codes and the associated sector sizes. 1659 * Finally, the Quad Enable Requirements (QER) are also available since JESD216 1660 * rev A. The QER bits encode the manufacturer dependent procedure to be 1661 * executed to set the Quad Enable (QE) bit in some internal register of the 1662 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 1663 * sending any Quad SPI command to the memory. Actually, setting the QE bit 1664 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 1665 * and IO3 hence enabling 4 (Quad) I/O lines. 1666 * 1667 * Return: 0 on success, -errno otherwise. 1668 */ 1669 static int spi_nor_parse_bfpt(struct spi_nor *nor, 1670 const struct sfdp_parameter_header *bfpt_header, 1671 struct spi_nor_flash_parameter *params) 1672 { 1673 struct mtd_info *mtd = &nor->mtd; 1674 struct sfdp_bfpt bfpt; 1675 size_t len; 1676 int i, cmd, err; 1677 u32 addr; 1678 u16 half; 1679 1680 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 1681 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 1682 return -EINVAL; 1683 1684 /* Read the Basic Flash Parameter Table. */ 1685 len = min_t(size_t, sizeof(bfpt), 1686 bfpt_header->length * sizeof(u32)); 1687 addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 1688 memset(&bfpt, 0, sizeof(bfpt)); 1689 err = spi_nor_read_sfdp(nor, addr, len, &bfpt); 1690 if (err < 0) 1691 return err; 1692 1693 /* Fix endianness of the BFPT DWORDs. */ 1694 for (i = 0; i < BFPT_DWORD_MAX; i++) 1695 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); 1696 1697 /* Number of address bytes. */ 1698 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 1699 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 1700 nor->addr_width = 3; 1701 break; 1702 1703 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 1704 nor->addr_width = 4; 1705 break; 1706 1707 default: 1708 break; 1709 } 1710 1711 /* Flash Memory Density (in bits). */ 1712 params->size = bfpt.dwords[BFPT_DWORD(2)]; 1713 if (params->size & BIT(31)) { 1714 params->size &= ~BIT(31); 1715 1716 /* 1717 * Prevent overflows on params->size. Anyway, a NOR of 2^64 1718 * bits is unlikely to exist so this error probably means 1719 * the BFPT we are reading is corrupted/wrong. 1720 */ 1721 if (params->size > 63) 1722 return -EINVAL; 1723 1724 params->size = 1ULL << params->size; 1725 } else { 1726 params->size++; 1727 } 1728 params->size >>= 3; /* Convert to bytes. */ 1729 1730 /* Fast Read settings. */ 1731 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 1732 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 1733 struct spi_nor_read_command *read; 1734 1735 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 1736 params->hwcaps.mask &= ~rd->hwcaps; 1737 continue; 1738 } 1739 1740 params->hwcaps.mask |= rd->hwcaps; 1741 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 1742 read = ¶ms->reads[cmd]; 1743 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 1744 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 1745 } 1746 1747 /* Sector Erase settings. */ 1748 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 1749 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 1750 u32 erasesize; 1751 u8 opcode; 1752 1753 half = bfpt.dwords[er->dword] >> er->shift; 1754 erasesize = half & 0xff; 1755 1756 /* erasesize == 0 means this Erase Type is not supported. */ 1757 if (!erasesize) 1758 continue; 1759 1760 erasesize = 1U << erasesize; 1761 opcode = (half >> 8) & 0xff; 1762 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 1763 if (erasesize == SZ_4K) { 1764 nor->erase_opcode = opcode; 1765 mtd->erasesize = erasesize; 1766 break; 1767 } 1768 #endif 1769 if (!mtd->erasesize || mtd->erasesize < erasesize) { 1770 nor->erase_opcode = opcode; 1771 mtd->erasesize = erasesize; 1772 } 1773 } 1774 1775 /* Stop here if not JESD216 rev A or later. */ 1776 if (bfpt_header->length < BFPT_DWORD_MAX) 1777 return 0; 1778 1779 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 1780 params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 1781 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 1782 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 1783 params->page_size = 1U << params->page_size; 1784 1785 /* Quad Enable Requirements. */ 1786 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 1787 case BFPT_DWORD15_QER_NONE: 1788 params->quad_enable = NULL; 1789 break; 1790 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1791 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 1792 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 1793 params->quad_enable = spansion_no_read_cr_quad_enable; 1794 break; 1795 #endif 1796 #ifdef CONFIG_SPI_FLASH_MACRONIX 1797 case BFPT_DWORD15_QER_SR1_BIT6: 1798 params->quad_enable = macronix_quad_enable; 1799 break; 1800 #endif 1801 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1802 case BFPT_DWORD15_QER_SR2_BIT1: 1803 params->quad_enable = spansion_read_cr_quad_enable; 1804 break; 1805 #endif 1806 default: 1807 return -EINVAL; 1808 } 1809 1810 return 0; 1811 } 1812 1813 /** 1814 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 1815 * @nor: pointer to a 'struct spi_nor' 1816 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1817 * filled 1818 * 1819 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 1820 * specification. This is a standard which tends to supported by almost all 1821 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 1822 * runtime the main parameters needed to perform basic SPI flash operations such 1823 * as Fast Read, Page Program or Sector Erase commands. 1824 * 1825 * Return: 0 on success, -errno otherwise. 1826 */ 1827 static int spi_nor_parse_sfdp(struct spi_nor *nor, 1828 struct spi_nor_flash_parameter *params) 1829 { 1830 const struct sfdp_parameter_header *param_header, *bfpt_header; 1831 struct sfdp_parameter_header *param_headers = NULL; 1832 struct sfdp_header header; 1833 size_t psize; 1834 int i, err; 1835 1836 /* Get the SFDP header. */ 1837 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); 1838 if (err < 0) 1839 return err; 1840 1841 /* Check the SFDP header version. */ 1842 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 1843 header.major != SFDP_JESD216_MAJOR) 1844 return -EINVAL; 1845 1846 /* 1847 * Verify that the first and only mandatory parameter header is a 1848 * Basic Flash Parameter Table header as specified in JESD216. 1849 */ 1850 bfpt_header = &header.bfpt_header; 1851 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 1852 bfpt_header->major != SFDP_JESD216_MAJOR) 1853 return -EINVAL; 1854 1855 /* 1856 * Allocate memory then read all parameter headers with a single 1857 * Read SFDP command. These parameter headers will actually be parsed 1858 * twice: a first time to get the latest revision of the basic flash 1859 * parameter table, then a second time to handle the supported optional 1860 * tables. 1861 * Hence we read the parameter headers once for all to reduce the 1862 * processing time. Also we use kmalloc() instead of devm_kmalloc() 1863 * because we don't need to keep these parameter headers: the allocated 1864 * memory is always released with kfree() before exiting this function. 1865 */ 1866 if (header.nph) { 1867 psize = header.nph * sizeof(*param_headers); 1868 1869 param_headers = kmalloc(psize, GFP_KERNEL); 1870 if (!param_headers) 1871 return -ENOMEM; 1872 1873 err = spi_nor_read_sfdp(nor, sizeof(header), 1874 psize, param_headers); 1875 if (err < 0) { 1876 dev_err(dev, "failed to read SFDP parameter headers\n"); 1877 goto exit; 1878 } 1879 } 1880 1881 /* 1882 * Check other parameter headers to get the latest revision of 1883 * the basic flash parameter table. 1884 */ 1885 for (i = 0; i < header.nph; i++) { 1886 param_header = ¶m_headers[i]; 1887 1888 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 1889 param_header->major == SFDP_JESD216_MAJOR && 1890 (param_header->minor > bfpt_header->minor || 1891 (param_header->minor == bfpt_header->minor && 1892 param_header->length > bfpt_header->length))) 1893 bfpt_header = param_header; 1894 } 1895 1896 err = spi_nor_parse_bfpt(nor, bfpt_header, params); 1897 if (err) 1898 goto exit; 1899 1900 /* Parse other parameter headers. */ 1901 for (i = 0; i < header.nph; i++) { 1902 param_header = ¶m_headers[i]; 1903 1904 switch (SFDP_PARAM_HEADER_ID(param_header)) { 1905 case SFDP_SECTOR_MAP_ID: 1906 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n"); 1907 break; 1908 1909 default: 1910 break; 1911 } 1912 1913 if (err) 1914 goto exit; 1915 } 1916 1917 exit: 1918 kfree(param_headers); 1919 return err; 1920 } 1921 #else 1922 static int spi_nor_parse_sfdp(struct spi_nor *nor, 1923 struct spi_nor_flash_parameter *params) 1924 { 1925 return -EINVAL; 1926 } 1927 #endif /* SPI_FLASH_SFDP_SUPPORT */ 1928 1929 static int spi_nor_init_params(struct spi_nor *nor, 1930 const struct flash_info *info, 1931 struct spi_nor_flash_parameter *params) 1932 { 1933 /* Set legacy flash parameters as default. */ 1934 memset(params, 0, sizeof(*params)); 1935 1936 /* Set SPI NOR sizes. */ 1937 params->size = info->sector_size * info->n_sectors; 1938 params->page_size = info->page_size; 1939 1940 /* (Fast) Read settings. */ 1941 params->hwcaps.mask |= SNOR_HWCAPS_READ; 1942 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 1943 0, 0, SPINOR_OP_READ, 1944 SNOR_PROTO_1_1_1); 1945 1946 if (!(info->flags & SPI_NOR_NO_FR)) { 1947 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 1948 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 1949 0, 8, SPINOR_OP_READ_FAST, 1950 SNOR_PROTO_1_1_1); 1951 } 1952 1953 if (info->flags & SPI_NOR_DUAL_READ) { 1954 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 1955 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 1956 0, 8, SPINOR_OP_READ_1_1_2, 1957 SNOR_PROTO_1_1_2); 1958 } 1959 1960 if (info->flags & SPI_NOR_QUAD_READ) { 1961 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 1962 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 1963 0, 8, SPINOR_OP_READ_1_1_4, 1964 SNOR_PROTO_1_1_4); 1965 } 1966 1967 /* Page Program settings. */ 1968 params->hwcaps.mask |= SNOR_HWCAPS_PP; 1969 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 1970 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 1971 1972 if (info->flags & SPI_NOR_QUAD_READ) { 1973 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 1974 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 1975 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 1976 } 1977 1978 /* Select the procedure to set the Quad Enable bit. */ 1979 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | 1980 SNOR_HWCAPS_PP_QUAD)) { 1981 switch (JEDEC_MFR(info)) { 1982 #ifdef CONFIG_SPI_FLASH_MACRONIX 1983 case SNOR_MFR_MACRONIX: 1984 params->quad_enable = macronix_quad_enable; 1985 break; 1986 #endif 1987 case SNOR_MFR_ST: 1988 case SNOR_MFR_MICRON: 1989 break; 1990 1991 default: 1992 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1993 /* Kept only for backward compatibility purpose. */ 1994 params->quad_enable = spansion_read_cr_quad_enable; 1995 #endif 1996 break; 1997 } 1998 } 1999 2000 /* Override the parameters with data read from SFDP tables. */ 2001 nor->addr_width = 0; 2002 nor->mtd.erasesize = 0; 2003 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 2004 !(info->flags & SPI_NOR_SKIP_SFDP)) { 2005 struct spi_nor_flash_parameter sfdp_params; 2006 2007 memcpy(&sfdp_params, params, sizeof(sfdp_params)); 2008 if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 2009 nor->addr_width = 0; 2010 nor->mtd.erasesize = 0; 2011 } else { 2012 memcpy(params, &sfdp_params, sizeof(*params)); 2013 } 2014 } 2015 2016 return 0; 2017 } 2018 2019 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2020 { 2021 size_t i; 2022 2023 for (i = 0; i < size; i++) 2024 if (table[i][0] == (int)hwcaps) 2025 return table[i][1]; 2026 2027 return -EINVAL; 2028 } 2029 2030 static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2031 { 2032 static const int hwcaps_read2cmd[][2] = { 2033 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2034 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2035 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2036 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2037 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2038 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2039 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2040 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2041 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2042 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2043 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2044 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2045 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2046 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2047 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2048 }; 2049 2050 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2051 ARRAY_SIZE(hwcaps_read2cmd)); 2052 } 2053 2054 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2055 { 2056 static const int hwcaps_pp2cmd[][2] = { 2057 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2058 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2059 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2060 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2061 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2062 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2063 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2064 }; 2065 2066 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2067 ARRAY_SIZE(hwcaps_pp2cmd)); 2068 } 2069 2070 static int spi_nor_select_read(struct spi_nor *nor, 2071 const struct spi_nor_flash_parameter *params, 2072 u32 shared_hwcaps) 2073 { 2074 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2075 const struct spi_nor_read_command *read; 2076 2077 if (best_match < 0) 2078 return -EINVAL; 2079 2080 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2081 if (cmd < 0) 2082 return -EINVAL; 2083 2084 read = ¶ms->reads[cmd]; 2085 nor->read_opcode = read->opcode; 2086 nor->read_proto = read->proto; 2087 2088 /* 2089 * In the spi-nor framework, we don't need to make the difference 2090 * between mode clock cycles and wait state clock cycles. 2091 * Indeed, the value of the mode clock cycles is used by a QSPI 2092 * flash memory to know whether it should enter or leave its 0-4-4 2093 * (Continuous Read / XIP) mode. 2094 * eXecution In Place is out of the scope of the mtd sub-system. 2095 * Hence we choose to merge both mode and wait state clock cycles 2096 * into the so called dummy clock cycles. 2097 */ 2098 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2099 return 0; 2100 } 2101 2102 static int spi_nor_select_pp(struct spi_nor *nor, 2103 const struct spi_nor_flash_parameter *params, 2104 u32 shared_hwcaps) 2105 { 2106 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2107 const struct spi_nor_pp_command *pp; 2108 2109 if (best_match < 0) 2110 return -EINVAL; 2111 2112 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2113 if (cmd < 0) 2114 return -EINVAL; 2115 2116 pp = ¶ms->page_programs[cmd]; 2117 nor->program_opcode = pp->opcode; 2118 nor->write_proto = pp->proto; 2119 return 0; 2120 } 2121 2122 static int spi_nor_select_erase(struct spi_nor *nor, 2123 const struct flash_info *info) 2124 { 2125 struct mtd_info *mtd = &nor->mtd; 2126 2127 /* Do nothing if already configured from SFDP. */ 2128 if (mtd->erasesize) 2129 return 0; 2130 2131 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 2132 /* prefer "small sector" erase if possible */ 2133 if (info->flags & SECT_4K) { 2134 nor->erase_opcode = SPINOR_OP_BE_4K; 2135 mtd->erasesize = 4096; 2136 } else if (info->flags & SECT_4K_PMC) { 2137 nor->erase_opcode = SPINOR_OP_BE_4K_PMC; 2138 mtd->erasesize = 4096; 2139 } else 2140 #endif 2141 { 2142 nor->erase_opcode = SPINOR_OP_SE; 2143 mtd->erasesize = info->sector_size; 2144 } 2145 return 0; 2146 } 2147 2148 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, 2149 const struct spi_nor_flash_parameter *params, 2150 const struct spi_nor_hwcaps *hwcaps) 2151 { 2152 u32 ignored_mask, shared_mask; 2153 bool enable_quad_io; 2154 int err; 2155 2156 /* 2157 * Keep only the hardware capabilities supported by both the SPI 2158 * controller and the SPI flash memory. 2159 */ 2160 shared_mask = hwcaps->mask & params->hwcaps.mask; 2161 2162 /* SPI n-n-n protocols are not supported yet. */ 2163 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | 2164 SNOR_HWCAPS_READ_4_4_4 | 2165 SNOR_HWCAPS_READ_8_8_8 | 2166 SNOR_HWCAPS_PP_4_4_4 | 2167 SNOR_HWCAPS_PP_8_8_8); 2168 if (shared_mask & ignored_mask) { 2169 dev_dbg(nor->dev, 2170 "SPI n-n-n protocols are not supported yet.\n"); 2171 shared_mask &= ~ignored_mask; 2172 } 2173 2174 /* Select the (Fast) Read command. */ 2175 err = spi_nor_select_read(nor, params, shared_mask); 2176 if (err) { 2177 dev_dbg(nor->dev, 2178 "can't select read settings supported by both the SPI controller and memory.\n"); 2179 return err; 2180 } 2181 2182 /* Select the Page Program command. */ 2183 err = spi_nor_select_pp(nor, params, shared_mask); 2184 if (err) { 2185 dev_dbg(nor->dev, 2186 "can't select write settings supported by both the SPI controller and memory.\n"); 2187 return err; 2188 } 2189 2190 /* Select the Sector Erase command. */ 2191 err = spi_nor_select_erase(nor, info); 2192 if (err) { 2193 dev_dbg(nor->dev, 2194 "can't select erase settings supported by both the SPI controller and memory.\n"); 2195 return err; 2196 } 2197 2198 /* Enable Quad I/O if needed. */ 2199 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || 2200 spi_nor_get_protocol_width(nor->write_proto) == 4); 2201 if (enable_quad_io && params->quad_enable) 2202 nor->quad_enable = params->quad_enable; 2203 else 2204 nor->quad_enable = NULL; 2205 2206 return 0; 2207 } 2208 2209 static int spi_nor_init(struct spi_nor *nor) 2210 { 2211 int err; 2212 2213 /* 2214 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up 2215 * with the software protection bits set 2216 */ 2217 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || 2218 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || 2219 JEDEC_MFR(nor->info) == SNOR_MFR_SST || 2220 nor->info->flags & SPI_NOR_HAS_LOCK) { 2221 write_enable(nor); 2222 write_sr(nor, 0); 2223 spi_nor_wait_till_ready(nor); 2224 } 2225 2226 if (nor->quad_enable) { 2227 err = nor->quad_enable(nor); 2228 if (err) { 2229 dev_dbg(nor->dev, "quad mode not supported\n"); 2230 return err; 2231 } 2232 } 2233 2234 if (nor->addr_width == 4 && 2235 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION)) { 2236 /* 2237 * If the RESET# pin isn't hooked up properly, or the system 2238 * otherwise doesn't perform a reset command in the boot 2239 * sequence, it's impossible to 100% protect against unexpected 2240 * reboots (e.g., crashes). Warn the user (or hopefully, system 2241 * designer) that this is bad. 2242 */ 2243 if (nor->flags & SNOR_F_BROKEN_RESET) 2244 printf("enabling reset hack; may not recover from unexpected reboots\n"); 2245 set_4byte(nor, nor->info, 1); 2246 } 2247 2248 return 0; 2249 } 2250 2251 int spi_nor_scan(struct spi_nor *nor) 2252 { 2253 struct spi_nor_flash_parameter params; 2254 const struct flash_info *info = NULL; 2255 struct mtd_info *mtd = &nor->mtd; 2256 struct spi_nor_hwcaps hwcaps = { 2257 .mask = SNOR_HWCAPS_READ | 2258 SNOR_HWCAPS_READ_FAST | 2259 SNOR_HWCAPS_PP, 2260 }; 2261 struct spi_slave *spi = nor->spi; 2262 int ret; 2263 2264 /* Reset SPI protocol for all commands. */ 2265 nor->reg_proto = SNOR_PROTO_1_1_1; 2266 nor->read_proto = SNOR_PROTO_1_1_1; 2267 nor->write_proto = SNOR_PROTO_1_1_1; 2268 nor->read = spi_nor_read_data; 2269 nor->write = spi_nor_write_data; 2270 nor->read_reg = spi_nor_read_reg; 2271 nor->write_reg = spi_nor_write_reg; 2272 2273 if (spi->mode & SPI_RX_QUAD) { 2274 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2275 2276 if (spi->mode & SPI_TX_QUAD) 2277 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | 2278 SNOR_HWCAPS_PP_1_1_4 | 2279 SNOR_HWCAPS_PP_1_4_4); 2280 } else if (spi->mode & SPI_RX_DUAL) { 2281 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2282 2283 if (spi->mode & SPI_TX_DUAL) 2284 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; 2285 } 2286 2287 info = spi_nor_read_id(nor); 2288 if (IS_ERR_OR_NULL(info)) 2289 return -ENOENT; 2290 /* Parse the Serial Flash Discoverable Parameters table. */ 2291 ret = spi_nor_init_params(nor, info, ¶ms); 2292 if (ret) 2293 return ret; 2294 2295 if (!mtd->name) 2296 mtd->name = info->name; 2297 mtd->priv = nor; 2298 mtd->type = MTD_NORFLASH; 2299 mtd->writesize = 1; 2300 mtd->flags = MTD_CAP_NORFLASH; 2301 mtd->size = params.size; 2302 mtd->_erase = spi_nor_erase; 2303 mtd->_read = spi_nor_read; 2304 2305 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 2306 /* NOR protection support for STmicro/Micron chips and similar */ 2307 if (JEDEC_MFR(info) == SNOR_MFR_ST || 2308 JEDEC_MFR(info) == SNOR_MFR_MICRON || 2309 JEDEC_MFR(info) == SNOR_MFR_SST || 2310 info->flags & SPI_NOR_HAS_LOCK) { 2311 nor->flash_lock = stm_lock; 2312 nor->flash_unlock = stm_unlock; 2313 nor->flash_is_locked = stm_is_locked; 2314 } 2315 #endif 2316 2317 #ifdef CONFIG_SPI_FLASH_SST 2318 /* sst nor chips use AAI word program */ 2319 if (info->flags & SST_WRITE) 2320 mtd->_write = sst_write; 2321 else 2322 #endif 2323 mtd->_write = spi_nor_write; 2324 2325 if (info->flags & USE_FSR) 2326 nor->flags |= SNOR_F_USE_FSR; 2327 if (info->flags & SPI_NOR_HAS_TB) 2328 nor->flags |= SNOR_F_HAS_SR_TB; 2329 if (info->flags & NO_CHIP_ERASE) 2330 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2331 if (info->flags & USE_CLSR) 2332 nor->flags |= SNOR_F_USE_CLSR; 2333 2334 if (info->flags & SPI_NOR_NO_ERASE) 2335 mtd->flags |= MTD_NO_ERASE; 2336 2337 nor->page_size = params.page_size; 2338 mtd->writebufsize = nor->page_size; 2339 2340 /* Some devices cannot do fast-read, no matter what DT tells us */ 2341 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW)) 2342 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2343 2344 /* 2345 * Configure the SPI memory: 2346 * - select op codes for (Fast) Read, Page Program and Sector Erase. 2347 * - set the number of dummy cycles (mode cycles + wait states). 2348 * - set the SPI protocols for register and memory accesses. 2349 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). 2350 */ 2351 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); 2352 if (ret) 2353 return ret; 2354 2355 if (nor->addr_width) { 2356 /* already configured from SFDP */ 2357 } else if (info->addr_width) { 2358 nor->addr_width = info->addr_width; 2359 } else if (mtd->size > SZ_16M) { 2360 #ifndef CONFIG_SPI_FLASH_BAR 2361 /* enable 4-byte addressing if the device exceeds 16MiB */ 2362 nor->addr_width = 4; 2363 spi_nor_set_4byte_opcodes(nor, info); 2364 #else 2365 /* Configure the BAR - discover bank cmds and read current bank */ 2366 nor->addr_width = 3; 2367 ret = read_bar(nor, info); 2368 if (ret < 0) 2369 return ret; 2370 #endif 2371 } else { 2372 nor->addr_width = 3; 2373 } 2374 2375 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 2376 dev_dbg(dev, "address width is too large: %u\n", 2377 nor->addr_width); 2378 return -EINVAL; 2379 } 2380 2381 /* Send all the required SPI flash commands to initialize device */ 2382 nor->info = info; 2383 ret = spi_nor_init(nor); 2384 if (ret) 2385 return ret; 2386 2387 nor->name = mtd->name; 2388 nor->size = mtd->size; 2389 nor->erase_size = mtd->erasesize; 2390 nor->sector_size = mtd->erasesize; 2391 2392 #ifndef CONFIG_SPL_BUILD 2393 printf("SF: Detected %s with page size ", nor->name); 2394 print_size(nor->page_size, ", erase size "); 2395 print_size(nor->erase_size, ", total "); 2396 print_size(nor->size, ""); 2397 puts("\n"); 2398 #endif 2399 2400 return 0; 2401 } 2402 2403 /* U-Boot specific functions, need to extend MTD to support these */ 2404 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) 2405 { 2406 int sr = read_sr(nor); 2407 2408 if (sr < 0) 2409 return sr; 2410 2411 return (sr >> 2) & 7; 2412 } 2413