sdhci: ast2600: HS200 support porting

- Change eMMC clock src from HPLL to MPLL if SCU300[11] is set.
- Parse device related properties when they exist.
- Add "sdhci_hs200" property for HS200 supp

sdhci: ast2600: HS200 support porting

- Change eMMC clock src from HPLL to MPLL if SCU300[11] is set.
- Parse device related properties when they exist.
- Add "sdhci_hs200" property for HS200 support.
- Add "max-frequency" for assigning different frequency,
e.g., 100MHz.

Change-Id: Iad4ec6c54f26afd3d6db78cb5485ff6cabbf7dd3
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>

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mmc: SD: Add property for timing phase and drive type

Config appropriate timing phase and drive type during
probe or attach eMMC/SD.

spl: ast2600: Reduce SPL image size

AST2600 A1 secure boot places BL1 image (i.e. SPL) into
a 64KB SRAM for verification and execution. This patch
mainly reduce the SPL image size.

Within the 64KB

spl: ast2600: Reduce SPL image size

AST2600 A1 secure boot places BL1 image (i.e. SPL) into
a 64KB SRAM for verification and execution. This patch
mainly reduce the SPL image size.

Within the 64KB space, 6KB space is reserved for the secure
boot image signature, key, and SPL stack/heap. Hence, the
SPL image size has the 58KB limitation and is enforced by
the linker script.

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add define for spl build not used

add 8bit support

add for sd card gpio

add support for bus-width from dts

add sdhci support gpio switch

add emmc/sd in ast2600

add sdhci for ast2500

mmc: correct the HS400 initialization process

After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates th

mmc: correct the HS400 initialization process

After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.

During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true for two reasons. First,
make sure in the function mmc_set_card_speed(), after switch to HS
mode, first config the clock rate, then read the EXT_CSD, avoid
receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue
the MMC_CMD_SWITCH command, it need to wait a bit then switch bus
properties.

Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>

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mmc: tmio: Clamp SD_SECCNT to 16bit values on 16bit IP

On 16bit variants of the TMIO SD IP, the SECCNT register can only be
programmed to 16bit values, while on the 32bit and 64bit variants it
can b

mmc: tmio: Clamp SD_SECCNT to 16bit values on 16bit IP

On 16bit variants of the TMIO SD IP, the SECCNT register can only be
programmed to 16bit values, while on the 32bit and 64bit variants it
can be programmed to 32bit values. The SECCNT register indicates the
maximum number of blocks in a continuous transfer. Hence, limit the
maximum continuous transfer block count to 65535 blocks on 16bit
variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit
variants.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

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mmc: sh_mmcif: Set default MMCIF clock rate

Set MMCIF clock rate to 97.5 MHz, which is the default according
to Gen2 datasheet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhi

mmc: sh_mmcif: Set default MMCIF clock rate

Set MMCIF clock rate to 97.5 MHz, which is the default according
to Gen2 datasheet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>

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mmc: Align MMC_TRACE with tiny printf

The tiny printf implementation only supports %x format specifier,
it does not support %X . Since it makes little difference whether
the debug output prints hex

mmc: Align MMC_TRACE with tiny printf

The tiny printf implementation only supports %x format specifier,
it does not support %X . Since it makes little difference whether
the debug output prints hex numbers in capitals or not, change it
to %x and make the MMC_TRACE output work with tiny printf too.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>

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mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8

According to latest specification rev.0026 and after confirmation with
HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on
H3

mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8

According to latest specification rev.0026 and after confirmation with
HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on
H3 ES2.0 SoC. Make it so.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

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mmc: tmio: Clear BUSWIDTH bit when WMODE bit is set

According to latest specification rev.0026, when HOST_MODE bit 0
(WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear
HOST_MODE bit 8

mmc: tmio: Clear BUSWIDTH bit when WMODE bit is set

According to latest specification rev.0026, when HOST_MODE bit 0
(WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear
HOST_MODE bit 8 in such case and align the code with Linux and
avoid possible unforeseen issues.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

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mmc: dwmmc: Poll for iDMAC TX/RX interrupt

Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.

Signed-off-by: Ley Foon Tan <ley.foon.ta

mmc: dwmmc: Poll for iDMAC TX/RX interrupt

Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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mmc: tmio: sdhi: Configure DT2FF register for HS400 mode

The DT2FF register must be configured differently for HS400 mode
and for HS200/SDR104 mode. Configure the DT2FF register according
to the rec

mmc: tmio: sdhi: Configure DT2FF register for HS400 mode

The DT2FF register must be configured differently for HS400 mode
and for HS200/SDR104 mode. Configure the DT2FF register according
to the recommended datasheet settings for each mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

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mmc: tmio: Configure HOST_MODE WMODE according to bus width

Set the HOST_MODE register WMODE bit according to the SDHI bus width,
that is 0 for 64bit bus and 1 for 16/32bit bus.

Signed-off-by: Mare

mmc: tmio: Configure HOST_MODE WMODE according to bus width

Set the HOST_MODE register WMODE bit according to the SDHI bus width,
that is 0 for 64bit bus and 1 for 16/32bit bus.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

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mmc: Downgrade SD/MMC from UHS/HS200/HS400 modes before boot

Older kernel versions or systems which do not connect eMMC reset line
properly may not be able to handle situations where either the eMMC

mmc: Downgrade SD/MMC from UHS/HS200/HS400 modes before boot

Older kernel versions or systems which do not connect eMMC reset line
properly may not be able to handle situations where either the eMMC
is left in HS200/HS400 mode or SD card in UHS modes by the bootloader
and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card
to non-UHS mode before booting the kernel to allow such older kernels
to work with modern U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>

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mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds

Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.

Signed-off-by: Abel Vesa

mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds

Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>

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mmc: omap_hsmmc: Use regulator_set_enable_if_allowed for enabling regulator

Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while enabling io regulators. This way the dri

mmc: omap_hsmmc: Use regulator_set_enable_if_allowed for enabling regulator

Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while enabling io regulators. This way the driver doesn't see an error
when disabling an always-on regulator and when enabling is not supported.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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samsung: mmc: Drop old MMC init code

Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remo

samsung: mmc: Drop old MMC init code

Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>

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mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929)

Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions
(SPRZ426D - November 2014 - Revised February 2018 [1]) m

mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929)

Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions
(SPRZ426D - November 2014 - Revised February 2018 [1]) mentions
unexpected tuning pattern errors. A small failure band may be present
in the tuning range which may be missed by the current algorithm.
Furthermore, the failure bands vary with temperature leading to
different optimum tuning values for different temperatures.

As suggested in the related Application Report (SPRACA9B - October 2017
- Revised July 2018 [2]), tuning should be done in two stages.
In stage 1, assign the optimum ratio in the maximum pass window for the
current temperature. In stage 2, if the chosen value is close to the
small failure band, move away from it in the appropriate direction.

References:
[1] http://www.ti.com/lit/pdf/sprz426
[2] http://www.ti.com/lit/pdf/SPRACA9

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>

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mmc: Do not poll using CMD13 when changing timing

When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.

mmc: Do not poll using CMD13 when changing timing

When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.

Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>

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