1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <misc.h> 9 #include <reset.h> 10 #include <reset-uclass.h> 11 #include <wdt.h> 12 #include <asm/io.h> 13 #include <asm/arch/wdt.h> 14 #include <asm/arch/scu_ast2500.h> 15 16 struct ast2500_reset_priv { 17 /* WDT used to perform resets. */ 18 struct udevice *wdt; 19 struct ast2500_scu *scu; 20 }; 21 22 static int ast2500_reset_deassert(struct reset_ctl *reset_ctl) 23 { 24 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); 25 struct ast2500_scu *scu = priv->scu; 26 int ret = 0; 27 28 debug("ast2500_reset_deassert reset_ctl->id %ld \n", reset_ctl->id); 29 30 if(reset_ctl->id >= 32) 31 clrbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); 32 else 33 clrbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); 34 35 return ret; 36 } 37 38 static int ast2500_reset_assert(struct reset_ctl *reset_ctl) 39 { 40 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); 41 struct ast2500_scu *scu = priv->scu; 42 // u32 reset_mode, reset_mask; 43 // bool reset_sdram; 44 int ret = 0; 45 46 debug("ast2500_reset_assert reset_ctl->id %ld \n", reset_ctl->id); 47 /* 48 * To reset SDRAM, a specifal flag in SYSRESET register 49 * needs to be enabled first 50 */ 51 #if 0 52 reset_mode = ast_reset_mode_from_flags(reset_ctl->id); 53 reset_mask = ast_reset_mask_from_flags(reset_ctl->id); 54 reset_sdram = reset_mode == WDT_CTRL_RESET_SOC && 55 (reset_mask & WDT_RESET_SDRAM); 56 57 if (reset_sdram) { 58 ast_scu_unlock(priv->scu); 59 setbits_le32(&priv->scu->sysreset_ctrl1, 60 SCU_SYSRESET_SDRAM_WDT); 61 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 62 clrbits_le32(&priv->scu->sysreset_ctrl1, 63 SCU_SYSRESET_SDRAM_WDT); 64 ast_scu_lock(priv->scu); 65 } else { 66 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 67 } 68 #endif 69 if(reset_ctl->id >= 32) 70 setbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); 71 else 72 setbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); 73 74 return ret; 75 } 76 77 78 static int ast2500_reset_request(struct reset_ctl *reset_ctl) 79 { 80 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, 81 reset_ctl->dev, reset_ctl->id); 82 83 return 0; 84 } 85 86 static int ast2500_reset_probe(struct udevice *dev) 87 { 88 struct ast2500_reset_priv *priv = dev_get_priv(dev); 89 struct udevice *clk_dev; 90 int ret = 0; 91 92 /* find SCU base address from clock device */ 93 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 94 &clk_dev); 95 if (ret) { 96 debug("clock device not found\n"); 97 return ret; 98 } 99 100 priv->scu = devfdt_get_addr_ptr(clk_dev); 101 if (IS_ERR(priv->scu)) { 102 debug("%s(): can't get SCU\n", __func__); 103 return PTR_ERR(priv->scu); 104 } 105 106 return 0; 107 } 108 109 static int ast2500_ofdata_to_platdata(struct udevice *dev) 110 { 111 struct ast2500_reset_priv *priv = dev_get_priv(dev); 112 int ret; 113 114 ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt", 115 &priv->wdt); 116 if (ret) { 117 debug("%s: can't find WDT for reset controller", __func__); 118 return ret; 119 } 120 121 return 0; 122 } 123 124 static const struct udevice_id aspeed_reset_ids[] = { 125 { .compatible = "aspeed,ast2500-reset" }, 126 { } 127 }; 128 129 struct reset_ops aspeed_reset_ops = { 130 .rst_assert = ast2500_reset_assert, 131 .rst_deassert = ast2500_reset_deassert, 132 .request = ast2500_reset_request, 133 }; 134 135 U_BOOT_DRIVER(aspeed_reset) = { 136 .name = "aspeed_reset", 137 .id = UCLASS_RESET, 138 .of_match = aspeed_reset_ids, 139 .probe = ast2500_reset_probe, 140 .ops = &aspeed_reset_ops, 141 .ofdata_to_platdata = ast2500_ofdata_to_platdata, 142 .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv), 143 }; 144