| dc619924 | 05-Dec-2018 |
Lukasz Majewski <lukma@denx.de> |
ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code
This patch extends the vf610 DDR memory controller code to support SW
leveling.
Signed-off-by: Lukasz Majewski <lukma@denx
ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code
This patch extends the vf610 DDR memory controller code to support SW
leveling.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
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| 9382f73b | 18-Jan-2019 |
Peng Fan <peng.fan@nxp.com> |
imx8: cpu: restrict checking ROM passover info for revA
Passover info only for revA.
move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
get_cpu_rev in SPL.
Add a CONFIG_SPL_BUILD
imx8: cpu: restrict checking ROM passover info for revA
Passover info only for revA.
move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
get_cpu_rev in SPL.
Add a CONFIG_SPL_BUILD for passover usage, no need to execute it again
in normal U-Boot stage. Also if still checking passover info in normal
U-Boot stage, need to make the passover code executed after
arch_cpu_init_dm.
So to make it easy and clean, only execute the code for SPL stage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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| 528915c7 | 04-Jan-2019 |
Ye Li <ye.li@nxp.com> |
imx: Fix potential lmb memory overwritten by stack
At default, u-boot reserves the memory from SP - 4KB to DRAM end for
lmb in arch_lmb_reserve. So lmb won't allocate any memory from it.
But we foun
imx: Fix potential lmb memory overwritten by stack
At default, u-boot reserves the memory from SP - 4KB to DRAM end for
lmb in arch_lmb_reserve. So lmb won't allocate any memory from it.
But we found the 4K gap for SP is not enough now, because some FDT
updating operations are added in our u-boot before jumping to kernel,
which needs larger stack. This causes the lmb allocated memory is overwritten
by stack.
Fix the issue by implementing the board_lmb_reserve to reserve from
SP - 16KB to memory end for lmb.
Signed-off-by: Ye Li <ye.li@nxp.com>
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| 04b24965 | 21-Dec-2018 |
Peng Fan <peng.fan@nxp.com> |
imx8: scu: use dedicated MU for SPL
SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And w
imx8: scu: use dedicated MU for SPL
SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And we could not replace the one
in dts with MU0_A, because MU0_A is reserved in secure world.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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| bab289cb | 11-Dec-2018 |
Fabio Estevam <festevam@gmail.com> |
mx7: Do not call lcdif_power_down() in the SPL case
Like it was done on imx6 in commit 9236269de57d ("imx: mx6: Fix
implementantion reset_misc")
Do not call lcdif_power_down() in the SPL case to fi
mx7: Do not call lcdif_power_down() in the SPL case
Like it was done on imx6 in commit 9236269de57d ("imx: mx6: Fix
implementantion reset_misc")
Do not call lcdif_power_down() in the SPL case to fix the following
build error:
LD spl/u-boot-spl
MKIMAGE u-boot.img
arch/arm/mach-imx/built-in.o: In function `reset_misc':
/home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372: undefined reference to `lcdif_power_down'
scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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| d4a0c098 | 28-Dec-2018 |
Fabio Estevam <festevam@gmail.com> |
imx8m: clock: Fix oscillator values
OSC_27M_CLK should return 27MHz and OSC_32K_CLK should return
32768Hz to reflect the reality.
This also keeps the values in sync with the Linux clock tree.
Sign
imx8m: clock: Fix oscillator values
OSC_27M_CLK should return 27MHz and OSC_32K_CLK should return
32768Hz to reflect the reality.
This also keeps the values in sync with the Linux clock tree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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| 81653478 | 04-Dec-2018 |
Stefan Agner <stefan.agner@toradex.com> |
ARM: vf610: ddrmc: do not write CR79 by default
The current value CTLUPD_AREF(0) is the reset value of the register,
so there is no need to write a value. If needed, the register can be
written usin
ARM: vf610: ddrmc: do not write CR79 by default
The current value CTLUPD_AREF(0) is the reset value of the register,
so there is no need to write a value. If needed, the register can be
written using board specific CR settings.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
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| 52c2c97e | 04-Dec-2018 |
Stefan Agner <stefan.agner@toradex.com> |
ARM: vf610: ddrmc: fix initialization completion detection
The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
proba
ARM: vf610: ddrmc: fix initialization completion detection
The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
probably did not affect real operations since at that stage typically
none of the other bits are set.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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