Fix smbios-mdrv2 CI build

The phosphor-dbus-interface type for memorySizeInKB changed
from uint32_t to size_t.

https://gerrit.openbmc-project.xyz/c/openbmc/phosphor-dbus-interfaces/+/41870

This up

Fix smbios-mdrv2 CI build

The phosphor-dbus-interface type for memorySizeInKB changed
from uint32_t to size_t.

https://gerrit.openbmc-project.xyz/c/openbmc/phosphor-dbus-interfaces/+/41870

This updates smbios-mdrv2 with that change to fix the CI build.

The phosphor-dbus-interface name for Common::UUID changed
from uUID to uuid. This updates smbios-mdrv2 with that change
to fix the CI build.

Change-Id: I37994e7b36ea8182c01386d804ff2de1e682fdd8
Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

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Retry PIROM reads to workaround possible failures

PIROM is supposed to be reliable and available in all power states, but
some CPUs have bugs which can cause reads to return invalid data in some
sma

Retry PIROM reads to workaround possible failures

PIROM is supposed to be reliable and available in all power states, but
some CPUs have bugs which can cause reads to return invalid data in some
small time windows. The root causes are complicated, so although the BMC
could technically detect these windows it would take a lot of work.
Instead, this commit just adds logic to read the SSpec from PIROM
multiple times and consider it a success when two reads return the same
data. This relies on the reasonable assumption that the corrupted data
will most likely not look like a valid SSpec, and that it's very
unlikely to hit the invalid window multiple times.

This code still only modifies two D-Bus properties, but now those values
are determined at (potentially) different times, so the property setting
functions are rewritten to work with a global property list. As the
property values are determined, they are added to the list, and are
re-processed as needed (e.g. object/interface gets readded).

Tested: (On 1-CPU platform without working PIROM interface)
- Modified readSSpec to return spoofed value, AC cycled and verified
it was set on target object/interface. Also warm reset host (which
reinitializes D-Bus objects due to SMBIOS tables being resent), and
verified properties are set again.
- Restarted target service (smbios-mdrv2) and verified this service
restarts and re-sets all target properties.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: I963a2c145f1b97b05046da795af97bd7028bc807

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Get Present property for Dimms

From smbios file, for physically not present dimms details are filled
as "NO DIMM". Using which populating Present property under
xyz.openbmc_project.Inventory.Item in

Get Present property for Dimms

From smbios file, for physically not present dimms details are filled
as "NO DIMM". Using which populating Present property under
xyz.openbmc_project.Inventory.Item interface with
true/false that indicates presence of dimms and making manufacturer
value empty for no dimm presence.

Tested:
Checked property is filled via dbus call.

Signed-off-by: Joshi-Mansi <mansi.joshi@linux.intel.com>
Change-Id: I84b05aeef3f77353fee1b663d39f3451c8faa337

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Defer PPIN read until BIOS enables it

On platforms with AST2600 BMC, we now boot fast enough to read the PPIN
over PECI before the BIOS has a chance to enable it (by default it is
not readable). Thi

Defer PPIN read until BIOS enables it

On platforms with AST2600 BMC, we now boot fast enough to read the PPIN
over PECI before the BIOS has a chance to enable it (by default it is
not readable). This commit delays the RdPkgConfig until BIOS is done
with POST.

Without this change, a value of 0 is read (and 0x90 CC - but that's
ignored), which causes us to drop it.

This also removes some unnecessary phosphor namespacing.

Tested:
- Booted from AC cycle, confirmed from journal logs that cpuinfoapp
delays an extra minute before running through getProcessorInfo. PPIN
is now set into SerialNumber D-Bus property and shown on Redfish.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: Ie3e8c668c6b24b42ced22fd9e103d1518702d78a

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Add utility code to monitor host state

For SST (and possibly other PECI users), we need to know when CPU is not
available (to avoid using PECI), and when BIOS is booting (to avoid race
condition on

Add utility code to monitor host state

For SST (and possibly other PECI users), we need to know when CPU is not
available (to avoid using PECI), and when BIOS is booting (to avoid race
condition on configuring SST).

Subscribes to CurrentHostState to determine S5/S0 state, and also
CoreBiosDone to determine if BIOS is done.

Tested: as part of child change
Ie6eed8ab23bff289e01d6d125402a5509d3a9110

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: I6a2ce21193d91a7efe53f7e48bcd57e685c903ff

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Get i2c addresses from configuration files.

Different platforms have different bus topology.
Use the peci address and i2c address specified in
json file to read data from cpu.

Tested:
Update basebo

Get i2c addresses from configuration files.

Different platforms have different bus topology.
Use the peci address and i2c address specified in
json file to read data from cpu.

Tested:
Update baseboard json file:
{
"Address": "0x30",
"Bus": 0,
"CpuID": 1,
"Name": "CPU 1",
"PresenceGpio": [
{
"Name": "CPU1_PRESENCE",
"Polarity": "Low"
}
],
"PiromI2cBus": 13,
"PiromI2cAddress": "0x50",
"Type": "XeonCPU"
}
Verified that correct bus addresses are used.

Signed-off-by: Zhikui Ren <zhikui.ren@intel.com>
Change-Id: Ib133958af8349b43c2f8f73c32d1aaa0d5bf52eb

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cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (

cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (PP), each with accompanying Base Frequency (BF)
information.

Discovery is started immediately, but if no CPUs are found or any
unexpected PECI error is encountered, discovery is aborted and scheduled
for periodic retries until complete.

The profile data is published on D-Bus using two predefined interfaces:
- xyz.openbmc_project.Control.Processor.CurrentOperationConfig, which
is implemented on each "cpu" object in the inventory, and contains
mutable properties for OOB configuration (modifiying properties not
supported yet).
- xyz.openbmc_project.Inventory.Item.Cpu.OperationConfig, which is
implemented on separate "config" objects and contains the readonly
properties for each performance profile.

Tested:
- Profiled performance of PECI operations via code instrumentation
(takes ~2 min per CPU on ast2500 during BMC boot, ~2 sec during BMC idle).
- Validated Redfish output against Linux driver using included python
tool.
- Injected PECI failures in code to test error handling, and tested
with Linux OS idling on host to make sure WOP is working.

Change-Id: I0d8ae79655dfd2880cf3bae6abe600597740df7c
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Fix issue on null ptr in funciton positionToString

Error message is as below:
smbiosmdrv2app[5607]: terminate called after throwing an instance of 'std::logic_error'
smbiosmdrv2app[5607]: what():

Fix issue on null ptr in funciton positionToString

Error message is as below:
smbiosmdrv2app[5607]: terminate called after throwing an instance of 'std::logic_error'
smbiosmdrv2app[5607]: what(): basic_string::_M_construct null not valid
systemd[1]: smbios-mdrv2.service: Main process exited, code=dumped, status=6/ABRT
systemd[1]: smbios-mdrv2.service: Failed with result 'core-dump'.

Have to check ptr is not null before using.

Tested:
When target prt is null return empty string, not crash app.

Change-Id: I5bc4c2681150fd1a7aeb0a2dc7b5d19e5b54dab0
Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>

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Move downstream package to upstream

Use upstream cpu interface

Signed-off-by: Zhikui Ren <zhikui.ren@intel.com>
Change-Id: I490482b212df4b73cbdedaba0bc5fefa229a5489

Fix some build failure issue

Fix some issues which will make build failure.
Also format the code with latest clang-format.

Tested:
Power cycle the system and after BIOS finish post, correct DIMM an

Fix some build failure issue

Fix some issues which will make build failure.
Also format the code with latest clang-format.

Tested:
Power cycle the system and after BIOS finish post, correct DIMM and CPU
information and UUID can show in Redfish.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: I5833a89842bc0969829d10fed262cf43d31d8c3f

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Add system dbus service for MDR V2

Add BIOS version and UUID in smbios table and provide dbus
interface for redfish to get these information.

Tested:
DC cycle the system and waiting for BIOS enteri

Add system dbus service for MDR V2

Add BIOS version and UUID in smbios table and provide dbus
interface for redfish to get these information.

Tested:
DC cycle the system and waiting for BIOS entering setup page.
Redfish should be able to show correct UUID.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: I0d364f27488d3efa24e4a9dde97086f09e94d2a2

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Add DIMM dbus service for MDR V2

Add all DIMM information in smbios table and provide dbus
interface for redfish to get DIMM information.

Tested:
DC cycle the system and waiting for BIOS entring se

Add DIMM dbus service for MDR V2

Add all DIMM information in smbios table and provide dbus
interface for redfish to get DIMM information.

Tested:
DC cycle the system and waiting for BIOS entring setup page.
Correct DIMM information should show in Redfish.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: I8c2678c5d40f4d1fde81292b21aa94e80b0ab586

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Add CPU dbus service for MDR V2

Add all CPU information in smbios table and provide dbus
interface for redfish to get CPU information.

Tested:
DC cycle system and waiting for BIOS entering setup pa

Add CPU dbus service for MDR V2

Add all CPU information in smbios table and provide dbus
interface for redfish to get CPU information.

Tested:
DC cycle system and waiting for BIOS entering setup page.
Check CPU information in Redfish, Redfish should show correct CPU
information.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: I8e6f803c516267de094a01fb1b1fa7d2420d2474

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Add synchronization function for MDR V2

Add synchronization function to sync smbios dir data with BMC
through dbus interface. Also add function to read smbios table
from flash file to memory.

Signe

Add synchronization function for MDR V2

Add synchronization function to sync smbios dir data with BMC
through dbus interface. Also add function to read smbios table
from flash file to memory.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: I14a6c958531463ed1c6e28811f0829fdcad310de

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Add dbus service to support MDR V2 ipmi command

Add send and get DataInfo function for MDR V2 ipmi
command store and get data through dbus interface.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux

Add dbus service to support MDR V2 ipmi command

Add send and get DataInfo function for MDR V2 ipmi
command store and get data through dbus interface.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: Ic069e4670e69de1fb92b4123da6be6588ac45244

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Add some header files of MDR

To start the work of ManagedDataRegion, add some header files to
the repo.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: I9dfad809d47f37f04ca6b8

Add some header files of MDR

To start the work of ManagedDataRegion, add some header files to
the repo.

Signed-off-by: Cheng C Yang <cheng.c.yang@linux.intel.com>
Change-Id: I9dfad809d47f37f04ca6b8a7ca2e809cae79c012

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