smbios-mdr: Add TPM Device Information

Type 43 of SMBIOS records defines the data structure to expose
TPM Device information. Add patch which displays the TPM Device
information on dbus.
Introduced

smbios-mdr: Add TPM Device Information

Type 43 of SMBIOS records defines the data structure to expose
TPM Device information. Add patch which displays the TPM Device
information on dbus.
Introduced `TPM_DBUS` meson option which will be disabled by default
When enabled, the TPM information is populated on DBUS.

Tested:

TPM information is available under dbus tree of smbios-mdr
```
:~# busctl tree xyz.openbmc_project.Smbios.MDR_V2
`- /xyz
`- /xyz/openbmc_project
|- /xyz/openbmc_project/Smbios
| `- /xyz/openbmc_project/Smbios/MDR_V2
|- /xyz/openbmc_project/inventory
| `- /xyz/openbmc_project/inventory/system
| `- /xyz/openbmc_project/inventory/system/chassis
| |- /xyz/openbmc_project/inventory/system/chassis/motherboard/bios
| `- /xyz/openbmc_project/inventory/system/chassis/motherboard/tpm
```

Change-Id: Icd42f4f043bf5a970f4829e5d318568360fe4b59
Signed-off-by: Prithvi Pai <ppai@nvidia.com>

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smbios-mdr:Add support to toggle pcieslot presence

In the current state, the PCIeslot presence is always hardcoded to
`true`, since the PCIeSlots are always embedded on the board. But the
slot prese

smbios-mdr:Add support to toggle pcieslot presence

In the current state, the PCIeslot presence is always hardcoded to
`true`, since the PCIeSlots are always embedded on the board. But the
slot presence is not really useful. Since we are already getting the
current usage of the slot in the SMBIOS Type 9 structure we could use
the "Available"/"Occupied" status in the current usage field to
indicate the drive presence.

Modify the slot presence code to only mark "true" if the current usage
of the slot is "Occupied" & make it "false" if it is anything other
than that.

Tested By:
1. Enabled the meson option via the meta-ibm layer by adding
PACKAGECONFIG:append = "slot-drive-presence"
2. Post the SMBIOS transfer, could see the presence of the slot being
toggled with respect to the current occupancy of the slot.

Change-Id: I57e6f48dc501e7e1625a5389ea1e989c5e585824
Signed-off-by: Manojkiran Eda <manojkiran.eda@gmail.com>

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pcieslot: Add slottype by length support

Add necessary support needed to display the fulllength & halflength
slottypes on dbus.

Tested By:
1. Once coreboot/u-root transfers the smbios tables, I cou

pcieslot: Add slottype by length support

Add necessary support needed to display the fulllength & halflength
slottypes on dbus.

Tested By:
1. Once coreboot/u-root transfers the smbios tables, I could see that
the PCIeSlot types also show the fulllength & halflength slots on
dbus & also confirmed the same on the openbmc webUI.

Change-Id: Iaf47f3525c86a82f5b57ac8cf05b9cb12b44f5cc
Signed-off-by: Manojkiran Eda <manojkiran.eda@gmail.com>

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Add asset tag support for processor

Type 4 (processor information), has assetTag field at 21h
address, pick the string from the offset and host the assettag
property.

Tested by:
1. After the smbios

Add asset tag support for processor

Type 4 (processor information), has assetTag field at 21h
address, pick the string from the offset and host the assettag
property.

Tested by:
1. After the smbios table transfer from coreboot/u-root the CPU dbus
objects reflects the assettag information as well successfully.

Change-Id: I2492446f31a6a15fa19672b09c2cb0d5b919ff64
Signed-off-by: Manojkiran Eda <manojkiran.eda@gmail.com>

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clang-format: update latest spec and reformat

Copy the latest format file from the docs repository and apply.

Change-Id: I1ece44942d482015c870eb78f9f386e5487a963f
Signed-off-by: Patrick Williams <p

clang-format: update latest spec and reformat

Copy the latest format file from the docs repository and apply.

Change-Id: I1ece44942d482015c870eb78f9f386e5487a963f
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>

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Add SMBIOS version 3.8 to supported version list

Added latest SMBIOS release version v3.8 (which is backward compatible)
to supported version list, without introducing new v3.8 structures.

Tested:

Add SMBIOS version 3.8 to supported version list

Added latest SMBIOS release version v3.8 (which is backward compatible)
to supported version list, without introducing new v3.8 structures.

Tested:
SMBIOS table on test system sending
SMBIOS in v3.8 properly exposed on D-Bus

Signed-off-by: Jan Sowinski <jan.sowinski@intel.com>
Signed-off-by: Jayaprakash Mutyala <mutyalax.jayaprakash@intel.com>
Change-Id: I9910c8f8c12f1ee1380ff4c5e9c67687189da5d9

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Enable MemoryLocation properties to be customized

-Enable MemoryLocation properties to be customized by a json table.
Example of memoryLocationTable.json:
{
"<MemoryDeviceLocator>": {
"Mem

Enable MemoryLocation properties to be customized

-Enable MemoryLocation properties to be customized by a json table.
Example of memoryLocationTable.json:
{
"<MemoryDeviceLocator>": {
"MemoryController": 1,
"Socket":48,
"Slot":0,
"Channel":0
}
}

-Add attribute "memoryController", "slot", "channel", "socket" in
MemoryLocation.

Tested:

memoryLocationTable.json:
{
"DIMM4": {
"MemoryController": 1,
"Socket":48,
"Slot":0,
"Channel":0
}
}

with the change:
curl -k -X GET http://${bmc}/redfish/v1/Systems/system/Memory/dimm1
{
"@odata.id": "/redfish/v1/Systems/system/Memory/dimm1",
"@odata.type": "#Memory.v1_11_0.Memory",
"AllowedSpeedsMHz": [],
"BaseModuleType": "RDIMM",
"BusWidthBits": 80,
"CapacityMiB": 49152,
"DataWidthBits": 64,
"ErrorCorrection": "SingleBitECC",
"FirmwareRevision": "0",
"Id": "dimm1",
"Location": {
"PartLocation": {
"LocationType": "Slot",
"ServiceLabel": "DIMM4"
}
},
"Manufacturer": "",
"MemoryDeviceType": "DDR5",
"MemoryLocation": {
"Channel": 0,
"MemoryController": 1,
"Slot": 0,
"Socket": 48
}

without the change:

curl -k -X GET http://${bmc}/redfish/v1/Systems/system/Memory/dimm1
{
"@odata.id": "/redfish/v1/Systems/system/Memory/dimm1",
"@odata.type": "#Memory.v1_11_0.Memory",
"AllowedSpeedsMHz": [],
"BaseModuleType": "RDIMM",
"BusWidthBits": 80,
"CapacityMiB": 49152,
"DataWidthBits": 64,
"ErrorCorrection": "SingleBitECC",
"FirmwareRevision": "0",
"Id": "dimm1",
"Location": {
"PartLocation": {
"LocationType": "Slot",
"ServiceLabel": "DIMM4"
}
},
"Manufacturer": "",
"MemoryDeviceType": "DDR5",
"MemoryLocation": {
"Channel": 0,
"MemoryController": 0,
"Slot": 0,
"Socket": 0
}

Change-Id: Ic5ff09715a619907f06d06af33aa0d1755c8b4f3
Signed-off-by: Tony Lee <tony.lee@quantatw.com>

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Enable support for SMBIOS version 3.7

Currently, SMBIOS-MDR supports up to version 3.5, and the changes
introduced in versions 3.6 and 3.7 are largely supported as well.
Therefore, enable the suppor

Enable support for SMBIOS version 3.7

Currently, SMBIOS-MDR supports up to version 3.5, and the changes
introduced in versions 3.6 and 3.7 are largely supported as well.
Therefore, enable the supported version to 3.7.

Tested:
The implementation was verified using EDK2, which supports
SMBIOS version 3.7, ensuring that all SMBIOS data is correctly populated
on D-Bus.

Change-Id: I61d3667d6ecf5635750022153ab30a54530ef2d3
Signed-off-by: Quang Nguyen <quangnguyen@os.amperecomputing.com>

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Enable support for SMBIOS version 3.0

SMBIOS 3.2 is essentially a superset of SMBIOS 3.0. The changes from
SMBIOS 3.0 to 3.2 added new structures and fields to accommodate more
recent hardware featu

Enable support for SMBIOS version 3.0

SMBIOS 3.2 is essentially a superset of SMBIOS 3.0. The changes from
SMBIOS 3.0 to 3.2 added new structures and fields to accommodate more
recent hardware features and capabilities, but they did not remove or
fundamentally alter any pre-existing structures from 3.0. This means
that:

- SMBIOS 3.2 remains backward-compatible with SMBIOS 3.0. Any software
or system expecting information from SMBIOS 3.0 should still be able
to interpret the data in SMBIOS 3.2 without issues.

Since we already support 3.2, its safe to assume that the code can also
parse the smbios table version 3.0 without any issues. Hence adding 3.0
in the list of supported versions.

Tested By:
Tested this change by sending the SMBIOS 3.0 tables from coreboot to
BMC via IPMI, and the smbios app seems to parse the data successfully
and host the dbus objects of CPU's and DIMM's.

Change-Id: I2af595ed49b7c697abb6d19331470ad17e060836
Signed-off-by: Manojkiran Eda <manojkiran.eda@gmail.com>

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clang-format: re-format for clang-18

clang-format-18 isn't compatible with the clang-format-17 output, so we
need to reformat the code with the latest version. The way clang-18
handles lambda forma

clang-format: re-format for clang-18

clang-format-18 isn't compatible with the clang-format-17 output, so we
need to reformat the code with the latest version. The way clang-18
handles lambda formatting also changed, so we have made changes to the
organization default style format to better handle lambda formatting.

See I5e08687e696dd240402a2780158664b7113def0e for updated style.
See Iea0776aaa7edd483fa395e23de25ebf5a6288f71 for clang-18 enablement.

Change-Id: I1210c7b95e65a82cc5675ada03441af6727a3930
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>

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cpuinfoapp: Make PECI features optional

Add a feature flag `cpuinfo-peci` to optionally disable the features in
cpuinfoapp that rely on PECI (PPIN, SST), to support configurations that
want I2C-base

cpuinfoapp: Make PECI features optional

Add a feature flag `cpuinfo-peci` to optionally disable the features in
cpuinfoapp that rely on PECI (PPIN, SST), to support configurations that
want I2C-based SSPEC detection but don't want to use libpeci.

Tested: Disabled `cpuinfo-peci` and verified SSPEC was still written
into the Model property.

Change-Id: Ie3ab9214d9d6ab238a61933de3e3856eca298fa8
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Add assoc-trim-path option and Board match

When a custom object path is being used (not the default object path
that comes from IPMI), allow the Board interface to be a valid
interface for associati

Add assoc-trim-path option and Board match

When a custom object path is being used (not the default object path
that comes from IPMI), allow the Board interface to be a valid
interface for associating the Inventory object with, not just the
System interface.

The purpose is to support large systems of the blade server style,
which have CPU and DIMM attached to a Board that is itself attached to
a System, not attached to the System directly.

Adding the assoc-trim-path option, disabled by default, to drop the
rightmost path component when setting up this association. This
bypasses the Board and associates the CPU and DIMM directly with the
underlying System.

Cleaning up the systemInfoUpdate() function, to correct a logic error
in which the match rule would not be set up for later if an exception
happened the first time. Also sleeping, to work around a race condition
with Object Mapper.

Tested: I tested it both with and without the assoc-trim-path option,
and it seemed to have the desired effect. With this option enabled, I
was able to attach CPU and DIMM to the proper System, even though there
was a Board object in the hierarchy between them.

Change-Id: Ibb5302e01b9d1b0453bdb14092ede594a9e71415
Signed-off-by: Josh Lehan <krellan@google.com>

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Enable support for SMBIOS version 3.4

As the currently supported 3.5 standard is a superset of 3.4, according
to a glance at the https://www.dmtf.org/standards/smbios spec, enabling
support for 3.4

Enable support for SMBIOS version 3.4

As the currently supported 3.5 standard is a superset of 3.4, according
to a glance at the https://www.dmtf.org/standards/smbios spec, enabling
support for 3.4 should be as straightforward as simply adding it to
this allowlist of supported versions.

This change is inspired by the proposed
https://github.com/openbmc/smbios-mdr/issues/6 which suggests a similar
change for 3.1 version. The only reason I am not adding 3.1 at the same
time here, is that I only have a 3.4 SMBIOS in the machine I am testing
now.

Tested: The SMBIOS from my host is no longer needlessly rejected for
being of 3.4 version.

Change-Id: I29bcb872377c87088b2ed4fc0ec90a03d89c15d8
Signed-off-by: Josh Lehan <krellan@google.com>

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Increase timeout to 2-sec for syncing SMBIOS data

MDRv2 (Send Data Set Done) command, sent from bios to BMC
is taking more time in some cases.
The timeout should be 2 sec instead of 0.02 sec.

Teste

Increase timeout to 2-sec for syncing SMBIOS data

MDRv2 (Send Data Set Done) command, sent from bios to BMC
is taking more time in some cases.
The timeout should be 2 sec instead of 0.02 sec.

Tested:
While sending mdr2 command from bios to BMC timeout is not seen.

Change-Id: I6f8a6109ea20f1ca1a1b00d497bd362934f14290
Signed-off-by: Yaswanth Reddy M <yaswanthx.reddy.munukuru@intel.com>

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Clean up some buffer allocations

While investigating some memory corruption, I found two bugs: the
backing store the SMBIOS data gets loaded into was left uninitialized,
and the buffer used for the

Clean up some buffer allocations

While investigating some memory corruption, I found two bugs: the
backing store the SMBIOS data gets loaded into was left uninitialized,
and the buffer used for the version check was allocated using a pointer
where a size should have been used instead.

Tested: While I can not say for sure this solves the corruption, it
seems to make it much less frequent, during my testing. I am not saying
it is gone, but I can no longer reproduce it.

Change-Id: Ic5d28a0d55cfb179c1bd73e95df2a6bf119f6d8c
Signed-off-by: Josh Lehan <krellan@google.com>

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sst: Don't always wake idle CPU

Some parts of SST are important (initial discovery, appliedConfig
change) and should use wake-on-PECI to ensure success even if the CPU is
in an idle PkgC state. Othe

sst: Don't always wake idle CPU

Some parts of SST are important (initial discovery, appliedConfig
change) and should use wake-on-PECI to ensure success even if the CPU is
in an idle PkgC state. Other parts are not important enough to justify
increasing the CPU power draw. Add a WakePolicy parameter to the
SSTInterface infrastructure to use a different policy in different
contexts.

Change-Id: I91435cc0357ab60ca4656e1bc51286e046ae3809
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Refactor MDRV2 class to allow more than one

Refactored the main MDRV2 class to allow more than one object of this
class to exist at the same time. All hardcoded paths have been made
parameters to th

Refactor MDRV2 class to allow more than one

Refactored the main MDRV2 class to allow more than one object of this
class to exist at the same time. All hardcoded paths have been made
parameters to the constructor, so that they can be varied at runtime as
needed, to avoid overlap.

Also did some necessary internal cleanups to facilitate this.

Tested: Created multiple copies of the MDRV2 object at the same time,
it worked, all appeared on D-Bus, under distinct object paths and
inventory paths. Destructed the MDRV2 object, it disappeared from
D-Bus, constructed it again, it came back.

https://gist.github.com/Krellan/6930bc2ed1ac16b93afcc3a12c02e545

Change-Id: Icd1ebf50086b526cf0cff149eb8ddc59da78f0a9
Signed-off-by: Josh Lehan <krellan@google.com>

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Add CPU functional property

ProcessorSummary in bmcweb always shows disable. Because bmcweb depends
on `xyz.openbmc_project.State.Decorator.OperationalStatus` interface
and `Functional` property to

Add CPU functional property

ProcessorSummary in bmcweb always shows disable. Because bmcweb depends
on `xyz.openbmc_project.State.Decorator.OperationalStatus` interface
and `Functional` property to return CPU functional state.
In this change, include the interface into smbios-mdr and re-add the
property `Functional` removed by smbios-mdr/+/36177

Tested:
```
GET /redfish/v1/Systems/system/
"ProcessorSummary": {
"CoreCount": 112,
"Count": 2,
"Status": {
"Health": "OK",
"HealthRollup": "OK",
"State": "Enabled"
}

busctl introspect xyz.openbmc_project.Smbios.MDR_V2 /xyz/openbmc_project/inventory/system/chassis/motherboard/cpu0
xyz.openbmc_project.State.Decorator.OperationalStatus interface - - -
.Functional property b true emits-change writable
```

Change-Id: I1b4d239ce02d2634a54afb98e4b5e72923fda4fb
Signed-off-by: David Wang <davidwang@quantatw.com>

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Initialize first byte in IPMI cache file

In the IPMI cache file, the first byte of this file was always
essentially random, because it was in a structure that had this field
uninitialized. Fixing it

Initialize first byte in IPMI cache file

In the IPMI cache file, the first byte of this file was always
essentially random, because it was in a structure that had this field
uninitialized. Fixing it, by arbitrarily choosing the value 0x01.

Added a new constant "mdrDirVersion" for this, and also added a similar
constant for "smbiosDirVersion" (which was being initialized, but to a
magic number directly in the code, not a constant).

Tested: Cache files now appear consistently.

Change-Id: I1f13ae973965b1a7105e2ac054ae30c52f45e2a9
Signed-off-by: Josh Lehan <krellan@google.com>

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Entered remaining CPU family text strings

The table of CPU family text strings was incomplete, missing many
entries, of processors both historical and bleeding-edge. Added the
missing entries, as pe

Entered remaining CPU family text strings

The table of CPU family text strings was incomplete, missing many
entries, of processors both historical and bleeding-edge. Added the
missing entries, as per Table 23 of DSP0134 3.7.0 spec.

Following the consistent format of whatever spelling and capitalization
the entry had in the spec, but with the dropping of special marketing
characters like (C), (R), (TM).

Tested: My CPU no longer shows up as "Unknown Processor Family".

Change-Id: I499cb516de27bf4adec7d034030c3d9c19c2c833
Signed-off-by: Josh Lehan <krellan@google.com>

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Change MemoryInfo.attributes type to uint8_t

PDI changed the type of `attributes` from uint8_t to size_t.
However the SMBIOS spec only reserved 1 byte for this field.
So we need to keep `attribute`

Change MemoryInfo.attributes type to uint8_t

PDI changed the type of `attributes` from uint8_t to size_t.
However the SMBIOS spec only reserved 1 byte for this field.
So we need to keep `attribute` in 1 byte otherwise the field after
`attribute` will be shifted.

Tested:
Before
.MemorySizeInKB property u 1258291200

After
.MemorySizeInKB property u 33554432

Change-Id: I1e2bfa78d4259c7b86a471ed880f2c5ca923bc66
Signed-off-by: Michael Shen <gpgpgp@google.com>

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Fix compilation warnings

Various small issues:
* Member initialization order
* Comparison of different signedness
* Unused parameters
* Unused variable

Change-Id: Ie59db239b4216ad089f7cf0f289e6ed3d

Fix compilation warnings

Various small issues:
* Member initialization order
* Comparison of different signedness
* Unused parameters
* Unused variable

Change-Id: Ie59db239b4216ad089f7cf0f289e6ed3d6ac8e18
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Populate MemoryTotalWidth property

The "MemoryTotalWidth" property did not display correct information
from the smbios file. Add function to transfer "totalWidth" type and
return data in sdbusplus f

Populate MemoryTotalWidth property

The "MemoryTotalWidth" property did not display correct information
from the smbios file. Add function to transfer "totalWidth" type and
return data in sdbusplus format.

Tested:
Before
```
root@qbmc:root@qbmc:~# busctl introspect xyz.openbmc_project.Smbios.MDR_V2 /xyz/openbmc_project/inventory/system/chassis/motherboard/dimm0 xyz.openbmc_project.Inventory.Item.Dimm
NAME TYPE SIGNATURE RESULT/VALUE FLAGS
.AllowedSpeedsMT property aq 0 emits-change writable
.CASLatencies property q 0 emits-change writable
.ECC property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.FormFactor property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MaxMemorySpeedInMhz property q 4800 emits-change writable
.MemoryAttributes property y 2 emits-change writable
.MemoryConfiguredSpeedInMhz property q 4800 emits-change writable
.MemoryDataWidth property q 64 emits-change writable
.MemoryDeviceLocator property s "DIMM0" emits-change writable
.MemoryMedia property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MemorySizeInKB property t 33554432 emits-change writable
.MemoryTotalWidth property q 0 emits-change writable
.MemoryType property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MemoryTypeDetail property s "SynchronousUnbuffered" emits-change writable
.RevisionCode property q 0 emits-change writable
```
After patching, MemoryTotalWidth property get correct value.
```
root@qbmc:~# busctl introspect xyz.openbmc_project.Smbios.MDR_V2 /xyz/openbmc_project/inventory/system/chassis/motherboard/dimm0 xyz.openbmc_project.Inventory.Item.Dimm
NAME TYPE SIGNATURE RESULT/VALUE FLAGS
.AllowedSpeedsMT property aq 0 emits-change writable
.CASLatencies property q 0 emits-change writable
.ECC property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.FormFactor property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MaxMemorySpeedInMhz property q 4800 emits-change writable
.MemoryAttributes property y 2 emits-change writable
.MemoryConfiguredSpeedInMhz property q 4800 emits-change writable
.MemoryDataWidth property q 64 emits-change writable
.MemoryDeviceLocator property s "DIMM0" emits-change writable
.MemoryMedia property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MemorySizeInKB property t 33554432 emits-change writable
.MemoryTotalWidth property q 72 emits-change writable
.MemoryType property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MemoryTypeDetail property s "SynchronousUnbuffered" emits-change writable
.RevisionCode property q 0 emits-change writable
```

Change-Id: I355ef057d7d28e4507d7c91eb45ab2453ed1923e
Signed-off-by: Joseph Fu <joseph.fu@quantatw.com>

show more ...

Populate Memory attributes

Add support to populate MemoryMedia, Slot and Socket attribute values
to dbus attributes.

Tested:
Memory attributes MemoryMedia,Slot and Socket are populated in dbus
thro

Populate Memory attributes

Add support to populate MemoryMedia, Slot and Socket attribute values
to dbus attributes.

Tested:
Memory attributes MemoryMedia,Slot and Socket are populated in dbus
through busctl command
Command:
busctl introspect xyz.openbmc_project.Smbios.MDR_V2
/xyz/openbmc_project/inventory/system/chassis/motherboard/dimm0
Response:
NAME TYPE SIGNATURE RESULT/VALUE FLAGS
....

xyz.openbmc_project.Inventory.Decorator.LocationCode interface - - -
.LocationCode property s "BANK 0 CPU0_DIMM_A" emits-change writable
xyz.openbmc_project.Inventory.Item interface - - -
.Present property b true emits-change writable
.PrettyName property s "" emits-change writable
xyz.openbmc_project.Inventory.Item.Dimm interface - - -

.MemoryAttributes property u 8388610 emits-change writable
.MemoryConfiguredSpeedInMhz property q 19460 emits-change writable
.MemoryDataWidth property q 64 emits-change writable
.MemoryDeviceLocator property s "BANK 0 CPU0_DIMM_A" emits-change writable
.MemoryMedia property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MemorySizeInKB property u 1468006400 emits-change writable
.MemoryTotalWidth property q 0 emits-change writable
.MemoryType property s "xyz.openbmc_project.Inventory.Item.D... emits-change writable
.MemoryTypeDetail property s "SynchronousRegistered" emits-change writable
.RevisionCode property q 0 emits-change writable
xyz.openbmc_project.Inventory.Item.Dimm.MemoryLocation interface - - -
.Channel property y 0 emits-change writable
.MemoryController property y 0 emits-change writable
.Slot property y 65 emits-change writable
.Socket property y 1 emits-change writable
.....

Signed-off-by: poram srinivasa rao <poramx.srinivasa.rao@intel.com>
Signed-off-by: Jayaprakash Mutyala <mutyalax.jayaprakash@intel.com>
Change-Id: Iabc2a58642167344711550b669ed4f207fb39d45

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Change the byte of the MemoryAttributes attribute to the size type

We prefer to use size_t type instead of byte type in PDI[1]

[1] https://gerrit.openbmc.org/c/openbmc/phosphor-dbus-interfaces/+/63

Change the byte of the MemoryAttributes attribute to the size type

We prefer to use size_t type instead of byte type in PDI[1]

[1] https://gerrit.openbmc.org/c/openbmc/phosphor-dbus-interfaces/+/63799

Signed-off-by: George Liu <liuxiwei@inspur.com>
Change-Id: I211a7cd553338995170407fa583d8926a6c98f53

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