1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \ 29 a1, a2, a3, a4, a5, a6) { \ 30 .targno = (no), \ 31 .flags = (fl), \ 32 .type = (typ), \ 33 .group = (grp), \ 34 .size = (sz), \ 35 }, 36 #define XTREG_END { .targno = -1 }, 37 38 #ifndef XCHAL_HAVE_DEPBITS 39 #define XCHAL_HAVE_DEPBITS 0 40 #endif 41 42 #ifndef XCHAL_HAVE_DIV32 43 #define XCHAL_HAVE_DIV32 0 44 #endif 45 46 #ifndef XCHAL_UNALIGNED_LOAD_HW 47 #define XCHAL_UNALIGNED_LOAD_HW 0 48 #endif 49 50 #ifndef XCHAL_HAVE_VECBASE 51 #define XCHAL_HAVE_VECBASE 0 52 #define XCHAL_VECBASE_RESET_VADDR 0 53 #endif 54 55 #ifndef XCHAL_RESET_VECTOR0_VADDR 56 #define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR 57 #endif 58 59 #ifndef XCHAL_RESET_VECTOR1_VADDR 60 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR 61 #endif 62 63 #ifndef XCHAL_HW_VERSION 64 #define XCHAL_HW_VERSION (XCHAL_HW_VERSION_MAJOR * 100 \ 65 + XCHAL_HW_VERSION_MINOR) 66 #endif 67 68 #ifndef XCHAL_LOOP_BUFFER_SIZE 69 #define XCHAL_LOOP_BUFFER_SIZE 0 70 #endif 71 72 #ifndef XCHAL_HAVE_EXTERN_REGS 73 #define XCHAL_HAVE_EXTERN_REGS 0 74 #endif 75 76 #ifndef XCHAL_HAVE_MPU 77 #define XCHAL_HAVE_MPU 0 78 #endif 79 80 #ifndef XCHAL_HAVE_EXCLUSIVE 81 #define XCHAL_HAVE_EXCLUSIVE 0 82 #endif 83 84 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) 85 86 #define XTENSA_OPTIONS ( \ 87 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \ 88 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \ 89 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \ 90 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \ 91 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \ 92 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \ 93 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \ 94 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \ 95 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \ 96 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \ 97 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \ 98 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \ 99 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \ 100 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \ 101 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ 102 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ 103 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ 104 XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \ 105 XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \ 106 XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \ 107 /* Interrupts and exceptions */ \ 108 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ 109 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \ 110 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \ 111 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \ 112 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \ 113 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \ 114 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \ 115 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \ 116 /* Local memory, TODO */ \ 117 XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \ 118 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \ 119 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \ 120 XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \ 121 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ 122 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ 123 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ 124 XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \ 125 XTENSA_OPTION_MEMORY_ECC_PARITY) | \ 126 /* Memory protection and translation */ \ 127 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ 128 XTENSA_OPTION_REGION_PROTECTION) | \ 129 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \ 130 XTENSA_OPTION_REGION_TRANSLATION) | \ 131 XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \ 132 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \ 133 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \ 134 /* Other, TODO */ \ 135 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ 136 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\ 137 XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \ 138 XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \ 139 XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \ 140 XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS)) 141 142 #ifndef XCHAL_WINDOW_OF4_VECOFS 143 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 144 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 145 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 146 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 147 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 148 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 149 #endif 150 151 #if XCHAL_HAVE_WINDOWED 152 #define WINDOW_VECTORS \ 153 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \ 154 XCHAL_WINDOW_VECTORS_VADDR, \ 155 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \ 156 XCHAL_WINDOW_VECTORS_VADDR, \ 157 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \ 158 XCHAL_WINDOW_VECTORS_VADDR, \ 159 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \ 160 XCHAL_WINDOW_VECTORS_VADDR, \ 161 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \ 162 XCHAL_WINDOW_VECTORS_VADDR, \ 163 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \ 164 XCHAL_WINDOW_VECTORS_VADDR, 165 #else 166 #define WINDOW_VECTORS 167 #endif 168 169 #define EXCEPTION_VECTORS { \ 170 [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \ 171 [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \ 172 WINDOW_VECTORS \ 173 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \ 174 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \ 175 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \ 176 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \ 177 } 178 179 #define INTERRUPT_VECTORS { \ 180 0, \ 181 0, \ 182 XCHAL_INTLEVEL2_VECTOR_VADDR, \ 183 XCHAL_INTLEVEL3_VECTOR_VADDR, \ 184 XCHAL_INTLEVEL4_VECTOR_VADDR, \ 185 XCHAL_INTLEVEL5_VECTOR_VADDR, \ 186 XCHAL_INTLEVEL6_VECTOR_VADDR, \ 187 XCHAL_INTLEVEL7_VECTOR_VADDR, \ 188 } 189 190 #define LEVEL_MASKS { \ 191 [1] = XCHAL_INTLEVEL1_MASK, \ 192 [2] = XCHAL_INTLEVEL2_MASK, \ 193 [3] = XCHAL_INTLEVEL3_MASK, \ 194 [4] = XCHAL_INTLEVEL4_MASK, \ 195 [5] = XCHAL_INTLEVEL5_MASK, \ 196 [6] = XCHAL_INTLEVEL6_MASK, \ 197 [7] = XCHAL_INTLEVEL7_MASK, \ 198 } 199 200 #define INTTYPE_MASKS { \ 201 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \ 202 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \ 203 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \ 204 } 205 206 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL 207 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE 208 #define XTHAL_INTTYPE_NMI INTTYPE_NMI 209 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE 210 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER 211 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG 212 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR 213 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR 214 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING 215 #define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE 216 #define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR 217 #define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR 218 219 #ifndef XCHAL_NMILEVEL 220 #define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS + 1) 221 #endif 222 223 #define INTERRUPT(i) { \ 224 .level = XCHAL_INT ## i ## _LEVEL, \ 225 .inttype = XCHAL_INT ## i ## _TYPE, \ 226 } 227 228 #define INTERRUPTS { \ 229 [0] = INTERRUPT(0), \ 230 [1] = INTERRUPT(1), \ 231 [2] = INTERRUPT(2), \ 232 [3] = INTERRUPT(3), \ 233 [4] = INTERRUPT(4), \ 234 [5] = INTERRUPT(5), \ 235 [6] = INTERRUPT(6), \ 236 [7] = INTERRUPT(7), \ 237 [8] = INTERRUPT(8), \ 238 [9] = INTERRUPT(9), \ 239 [10] = INTERRUPT(10), \ 240 [11] = INTERRUPT(11), \ 241 [12] = INTERRUPT(12), \ 242 [13] = INTERRUPT(13), \ 243 [14] = INTERRUPT(14), \ 244 [15] = INTERRUPT(15), \ 245 [16] = INTERRUPT(16), \ 246 [17] = INTERRUPT(17), \ 247 [18] = INTERRUPT(18), \ 248 [19] = INTERRUPT(19), \ 249 [20] = INTERRUPT(20), \ 250 [21] = INTERRUPT(21), \ 251 [22] = INTERRUPT(22), \ 252 [23] = INTERRUPT(23), \ 253 [24] = INTERRUPT(24), \ 254 [25] = INTERRUPT(25), \ 255 [26] = INTERRUPT(26), \ 256 [27] = INTERRUPT(27), \ 257 [28] = INTERRUPT(28), \ 258 [29] = INTERRUPT(29), \ 259 [30] = INTERRUPT(30), \ 260 [31] = INTERRUPT(31), \ 261 } 262 263 #define TIMERINTS { \ 264 [0] = XCHAL_TIMER0_INTERRUPT, \ 265 [1] = XCHAL_TIMER1_INTERRUPT, \ 266 [2] = XCHAL_TIMER2_INTERRUPT, \ 267 } 268 269 #define EXTINTS { \ 270 [0] = XCHAL_EXTINT0_NUM, \ 271 [1] = XCHAL_EXTINT1_NUM, \ 272 [2] = XCHAL_EXTINT2_NUM, \ 273 [3] = XCHAL_EXTINT3_NUM, \ 274 [4] = XCHAL_EXTINT4_NUM, \ 275 [5] = XCHAL_EXTINT5_NUM, \ 276 [6] = XCHAL_EXTINT6_NUM, \ 277 [7] = XCHAL_EXTINT7_NUM, \ 278 [8] = XCHAL_EXTINT8_NUM, \ 279 [9] = XCHAL_EXTINT9_NUM, \ 280 [10] = XCHAL_EXTINT10_NUM, \ 281 [11] = XCHAL_EXTINT11_NUM, \ 282 [12] = XCHAL_EXTINT12_NUM, \ 283 [13] = XCHAL_EXTINT13_NUM, \ 284 [14] = XCHAL_EXTINT14_NUM, \ 285 [15] = XCHAL_EXTINT15_NUM, \ 286 [16] = XCHAL_EXTINT16_NUM, \ 287 [17] = XCHAL_EXTINT17_NUM, \ 288 [18] = XCHAL_EXTINT18_NUM, \ 289 [19] = XCHAL_EXTINT19_NUM, \ 290 [20] = XCHAL_EXTINT20_NUM, \ 291 [21] = XCHAL_EXTINT21_NUM, \ 292 [22] = XCHAL_EXTINT22_NUM, \ 293 [23] = XCHAL_EXTINT23_NUM, \ 294 [24] = XCHAL_EXTINT24_NUM, \ 295 [25] = XCHAL_EXTINT25_NUM, \ 296 [26] = XCHAL_EXTINT26_NUM, \ 297 [27] = XCHAL_EXTINT27_NUM, \ 298 [28] = XCHAL_EXTINT28_NUM, \ 299 [29] = XCHAL_EXTINT29_NUM, \ 300 [30] = XCHAL_EXTINT30_NUM, \ 301 [31] = XCHAL_EXTINT31_NUM, \ 302 } 303 304 #define EXCEPTIONS_SECTION \ 305 .excm_level = XCHAL_EXCM_LEVEL, \ 306 .vecbase = XCHAL_VECBASE_RESET_VADDR, \ 307 .exception_vector = EXCEPTION_VECTORS 308 309 #define INTERRUPTS_SECTION \ 310 .ninterrupt = XCHAL_NUM_INTERRUPTS, \ 311 .nlevel = XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI, \ 312 .nmi_level = XCHAL_NMILEVEL, \ 313 .interrupt_vector = INTERRUPT_VECTORS, \ 314 .level_mask = LEVEL_MASKS, \ 315 .inttype_mask = INTTYPE_MASKS, \ 316 .interrupt = INTERRUPTS, \ 317 .nccompare = XCHAL_NUM_TIMERS, \ 318 .timerint = TIMERINTS, \ 319 .nextint = XCHAL_NUM_EXTINTERRUPTS, \ 320 .extint = EXTINTS 321 322 #if XCHAL_HAVE_PTP_MMU 323 324 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \ 325 .nways = ways, \ 326 .way_size = { \ 327 (refill_way_size), (refill_way_size), \ 328 (refill_way_size), (refill_way_size), \ 329 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \ 330 }, \ 331 .varway56 = (way56), \ 332 .nrefillentries = (refill_way_size) * 4, \ 333 } 334 335 #define ITLB(varway56) \ 336 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56) 337 338 #define DTLB(varway56) \ 339 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56) 340 341 #define TLB_SECTION \ 342 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \ 343 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY) 344 345 #ifndef XCHAL_SYSROM0_PADDR 346 #define XCHAL_SYSROM0_PADDR 0xfe000000 347 #define XCHAL_SYSROM0_SIZE 0x02000000 348 #endif 349 350 #ifndef XCHAL_SYSRAM0_PADDR 351 #define XCHAL_SYSRAM0_PADDR 0x00000000 352 #define XCHAL_SYSRAM0_SIZE 0x08000000 353 #endif 354 355 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR 356 357 #define TLB_TEMPLATE { \ 358 .nways = 1, \ 359 .way_size = { \ 360 8, \ 361 } \ 362 } 363 364 #define TLB_SECTION \ 365 .itlb = TLB_TEMPLATE, \ 366 .dtlb = TLB_TEMPLATE 367 368 #ifndef XCHAL_SYSROM0_PADDR 369 #define XCHAL_SYSROM0_PADDR 0x50000000 370 #define XCHAL_SYSROM0_SIZE 0x04000000 371 #endif 372 373 #ifndef XCHAL_SYSRAM0_PADDR 374 #define XCHAL_SYSRAM0_PADDR 0x60000000 375 #define XCHAL_SYSRAM0_SIZE 0x04000000 376 #endif 377 378 #elif XCHAL_HAVE_MPU 379 380 #ifndef XTENSA_MPU_BG_MAP 381 #ifdef XCHAL_MPU_BACKGROUND_MAP 382 #define XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) \ 383 { .vaddr = (vaddr_start), .attr = ((rights) << 8) | ((memtype) << 12), }, 384 385 #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ 386 XCHAL_MPU_BACKGROUND_MAP(0) \ 387 } 388 389 #define XTENSA_MPU_BG_MAP_ENTRIES XCHAL_MPU_BACKGROUND_ENTRIES 390 #else 391 #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ 392 { .vaddr = 0, .attr = 0x00006700, }, \ 393 } 394 395 #define XTENSA_MPU_BG_MAP_ENTRIES 1 396 #endif 397 #endif 398 399 #define TLB_SECTION \ 400 .mpu_align = XCHAL_MPU_ALIGN, \ 401 .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \ 402 .n_mpu_bg_segments = XTENSA_MPU_BG_MAP_ENTRIES, \ 403 .mpu_bg = XTENSA_MPU_BG_MAP 404 405 #ifndef XCHAL_SYSROM0_PADDR 406 #define XCHAL_SYSROM0_PADDR 0x50000000 407 #define XCHAL_SYSROM0_SIZE 0x04000000 408 #endif 409 410 #ifndef XCHAL_SYSRAM0_PADDR 411 #define XCHAL_SYSRAM0_PADDR 0x60000000 412 #define XCHAL_SYSRAM0_SIZE 0x04000000 413 #endif 414 415 #else 416 417 #ifndef XCHAL_SYSROM0_PADDR 418 #define XCHAL_SYSROM0_PADDR 0x50000000 419 #define XCHAL_SYSROM0_SIZE 0x04000000 420 #endif 421 422 #ifndef XCHAL_SYSRAM0_PADDR 423 #define XCHAL_SYSRAM0_PADDR 0x60000000 424 #define XCHAL_SYSRAM0_SIZE 0x04000000 425 #endif 426 427 #endif 428 429 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0) 430 #define REGISTER_CORE(core) \ 431 static void __attribute__((constructor)) register_core(void) \ 432 { \ 433 static XtensaConfigList node = { \ 434 .config = &core, \ 435 }; \ 436 xtensa_register_core(&node); \ 437 } 438 #else 439 #define REGISTER_CORE(core) 440 #endif 441 442 #define DEBUG_SECTION \ 443 .debug_level = XCHAL_DEBUGLEVEL, \ 444 .nibreak = XCHAL_NUM_IBREAK, \ 445 .ndbreak = XCHAL_NUM_DBREAK 446 447 #define CACHE_SECTION \ 448 .icache_ways = XCHAL_ICACHE_WAYS, \ 449 .dcache_ways = XCHAL_DCACHE_WAYS, \ 450 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ 451 .memctl_mask = \ 452 (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ 453 (XCHAL_DCACHE_SIZE ? \ 454 MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \ 455 MEMCTL_ISNP | MEMCTL_DSNP | \ 456 (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0) 457 458 #define MEM_LOCATION(name, n) \ 459 { \ 460 .addr = XCHAL_ ## name ## n ## _PADDR, \ 461 .size = XCHAL_ ## name ## n ## _SIZE, \ 462 } 463 464 #define MEM_SECTIONS(name) \ 465 MEM_LOCATION(name, 0), \ 466 MEM_LOCATION(name, 1), \ 467 MEM_LOCATION(name, 2), \ 468 MEM_LOCATION(name, 3) 469 470 #define MEM_SECTION(name) \ 471 .num = XCHAL_NUM_ ## name, \ 472 .location = { \ 473 MEM_SECTIONS(name) \ 474 } 475 476 #define SYSMEM_SECTION(name) \ 477 .num = 1, \ 478 .location = { \ 479 { \ 480 .addr = XCHAL_ ## name ## 0_PADDR, \ 481 .size = XCHAL_ ## name ## 0_SIZE, \ 482 } \ 483 } 484 485 #define LOCAL_MEMORIES_SECTION \ 486 .instrom = { \ 487 MEM_SECTION(INSTROM) \ 488 }, \ 489 .instram = { \ 490 MEM_SECTION(INSTRAM) \ 491 }, \ 492 .datarom = { \ 493 MEM_SECTION(DATAROM) \ 494 }, \ 495 .dataram = { \ 496 MEM_SECTION(DATARAM) \ 497 }, \ 498 .sysrom = { \ 499 SYSMEM_SECTION(SYSROM) \ 500 }, \ 501 .sysram = { \ 502 SYSMEM_SECTION(SYSRAM) \ 503 } 504 505 #define CONFIG_SECTION \ 506 .hw_version = XCHAL_HW_VERSION, \ 507 .configid = { \ 508 XCHAL_HW_CONFIGID0, \ 509 XCHAL_HW_CONFIGID1, \ 510 } 511 512 #define DEFAULT_SECTIONS \ 513 .options = XTENSA_OPTIONS, \ 514 .nareg = XCHAL_NUM_AREGS, \ 515 .ndepc = (XCHAL_XEA_VERSION >= 2), \ 516 .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \ 517 .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ 518 EXCEPTIONS_SECTION, \ 519 INTERRUPTS_SECTION, \ 520 TLB_SECTION, \ 521 DEBUG_SECTION, \ 522 CACHE_SECTION, \ 523 LOCAL_MEMORIES_SECTION, \ 524 CONFIG_SECTION 525 526 527 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2 528 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0 529 #endif 530 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3 531 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0 532 #endif 533 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4 534 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0 535 #endif 536 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5 537 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0 538 #endif 539 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6 540 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0 541 #endif 542 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7 543 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0 544 #endif 545 546 547 #if XCHAL_NUM_INTERRUPTS <= 0 548 #define XCHAL_INT0_LEVEL 0 549 #define XCHAL_INT0_TYPE 0 550 #endif 551 #if XCHAL_NUM_INTERRUPTS <= 1 552 #define XCHAL_INT1_LEVEL 0 553 #define XCHAL_INT1_TYPE 0 554 #endif 555 #if XCHAL_NUM_INTERRUPTS <= 2 556 #define XCHAL_INT2_LEVEL 0 557 #define XCHAL_INT2_TYPE 0 558 #endif 559 #if XCHAL_NUM_INTERRUPTS <= 3 560 #define XCHAL_INT3_LEVEL 0 561 #define XCHAL_INT3_TYPE 0 562 #endif 563 #if XCHAL_NUM_INTERRUPTS <= 4 564 #define XCHAL_INT4_LEVEL 0 565 #define XCHAL_INT4_TYPE 0 566 #endif 567 #if XCHAL_NUM_INTERRUPTS <= 5 568 #define XCHAL_INT5_LEVEL 0 569 #define XCHAL_INT5_TYPE 0 570 #endif 571 #if XCHAL_NUM_INTERRUPTS <= 6 572 #define XCHAL_INT6_LEVEL 0 573 #define XCHAL_INT6_TYPE 0 574 #endif 575 #if XCHAL_NUM_INTERRUPTS <= 7 576 #define XCHAL_INT7_LEVEL 0 577 #define XCHAL_INT7_TYPE 0 578 #endif 579 #if XCHAL_NUM_INTERRUPTS <= 8 580 #define XCHAL_INT8_LEVEL 0 581 #define XCHAL_INT8_TYPE 0 582 #endif 583 #if XCHAL_NUM_INTERRUPTS <= 9 584 #define XCHAL_INT9_LEVEL 0 585 #define XCHAL_INT9_TYPE 0 586 #endif 587 #if XCHAL_NUM_INTERRUPTS <= 10 588 #define XCHAL_INT10_LEVEL 0 589 #define XCHAL_INT10_TYPE 0 590 #endif 591 #if XCHAL_NUM_INTERRUPTS <= 11 592 #define XCHAL_INT11_LEVEL 0 593 #define XCHAL_INT11_TYPE 0 594 #endif 595 #if XCHAL_NUM_INTERRUPTS <= 12 596 #define XCHAL_INT12_LEVEL 0 597 #define XCHAL_INT12_TYPE 0 598 #endif 599 #if XCHAL_NUM_INTERRUPTS <= 13 600 #define XCHAL_INT13_LEVEL 0 601 #define XCHAL_INT13_TYPE 0 602 #endif 603 #if XCHAL_NUM_INTERRUPTS <= 14 604 #define XCHAL_INT14_LEVEL 0 605 #define XCHAL_INT14_TYPE 0 606 #endif 607 #if XCHAL_NUM_INTERRUPTS <= 15 608 #define XCHAL_INT15_LEVEL 0 609 #define XCHAL_INT15_TYPE 0 610 #endif 611 #if XCHAL_NUM_INTERRUPTS <= 16 612 #define XCHAL_INT16_LEVEL 0 613 #define XCHAL_INT16_TYPE 0 614 #endif 615 #if XCHAL_NUM_INTERRUPTS <= 17 616 #define XCHAL_INT17_LEVEL 0 617 #define XCHAL_INT17_TYPE 0 618 #endif 619 #if XCHAL_NUM_INTERRUPTS <= 18 620 #define XCHAL_INT18_LEVEL 0 621 #define XCHAL_INT18_TYPE 0 622 #endif 623 #if XCHAL_NUM_INTERRUPTS <= 19 624 #define XCHAL_INT19_LEVEL 0 625 #define XCHAL_INT19_TYPE 0 626 #endif 627 #if XCHAL_NUM_INTERRUPTS <= 20 628 #define XCHAL_INT20_LEVEL 0 629 #define XCHAL_INT20_TYPE 0 630 #endif 631 #if XCHAL_NUM_INTERRUPTS <= 21 632 #define XCHAL_INT21_LEVEL 0 633 #define XCHAL_INT21_TYPE 0 634 #endif 635 #if XCHAL_NUM_INTERRUPTS <= 22 636 #define XCHAL_INT22_LEVEL 0 637 #define XCHAL_INT22_TYPE 0 638 #endif 639 #if XCHAL_NUM_INTERRUPTS <= 23 640 #define XCHAL_INT23_LEVEL 0 641 #define XCHAL_INT23_TYPE 0 642 #endif 643 #if XCHAL_NUM_INTERRUPTS <= 24 644 #define XCHAL_INT24_LEVEL 0 645 #define XCHAL_INT24_TYPE 0 646 #endif 647 #if XCHAL_NUM_INTERRUPTS <= 25 648 #define XCHAL_INT25_LEVEL 0 649 #define XCHAL_INT25_TYPE 0 650 #endif 651 #if XCHAL_NUM_INTERRUPTS <= 26 652 #define XCHAL_INT26_LEVEL 0 653 #define XCHAL_INT26_TYPE 0 654 #endif 655 #if XCHAL_NUM_INTERRUPTS <= 27 656 #define XCHAL_INT27_LEVEL 0 657 #define XCHAL_INT27_TYPE 0 658 #endif 659 #if XCHAL_NUM_INTERRUPTS <= 28 660 #define XCHAL_INT28_LEVEL 0 661 #define XCHAL_INT28_TYPE 0 662 #endif 663 #if XCHAL_NUM_INTERRUPTS <= 29 664 #define XCHAL_INT29_LEVEL 0 665 #define XCHAL_INT29_TYPE 0 666 #endif 667 #if XCHAL_NUM_INTERRUPTS <= 30 668 #define XCHAL_INT30_LEVEL 0 669 #define XCHAL_INT30_TYPE 0 670 #endif 671 #if XCHAL_NUM_INTERRUPTS <= 31 672 #define XCHAL_INT31_LEVEL 0 673 #define XCHAL_INT31_TYPE 0 674 #endif 675 676 677 #if XCHAL_NUM_EXTINTERRUPTS <= 0 678 #define XCHAL_EXTINT0_NUM 0 679 #endif 680 #if XCHAL_NUM_EXTINTERRUPTS <= 1 681 #define XCHAL_EXTINT1_NUM 0 682 #endif 683 #if XCHAL_NUM_EXTINTERRUPTS <= 2 684 #define XCHAL_EXTINT2_NUM 0 685 #endif 686 #if XCHAL_NUM_EXTINTERRUPTS <= 3 687 #define XCHAL_EXTINT3_NUM 0 688 #endif 689 #if XCHAL_NUM_EXTINTERRUPTS <= 4 690 #define XCHAL_EXTINT4_NUM 0 691 #endif 692 #if XCHAL_NUM_EXTINTERRUPTS <= 5 693 #define XCHAL_EXTINT5_NUM 0 694 #endif 695 #if XCHAL_NUM_EXTINTERRUPTS <= 6 696 #define XCHAL_EXTINT6_NUM 0 697 #endif 698 #if XCHAL_NUM_EXTINTERRUPTS <= 7 699 #define XCHAL_EXTINT7_NUM 0 700 #endif 701 #if XCHAL_NUM_EXTINTERRUPTS <= 8 702 #define XCHAL_EXTINT8_NUM 0 703 #endif 704 #if XCHAL_NUM_EXTINTERRUPTS <= 9 705 #define XCHAL_EXTINT9_NUM 0 706 #endif 707 #if XCHAL_NUM_EXTINTERRUPTS <= 10 708 #define XCHAL_EXTINT10_NUM 0 709 #endif 710 #if XCHAL_NUM_EXTINTERRUPTS <= 11 711 #define XCHAL_EXTINT11_NUM 0 712 #endif 713 #if XCHAL_NUM_EXTINTERRUPTS <= 12 714 #define XCHAL_EXTINT12_NUM 0 715 #endif 716 #if XCHAL_NUM_EXTINTERRUPTS <= 13 717 #define XCHAL_EXTINT13_NUM 0 718 #endif 719 #if XCHAL_NUM_EXTINTERRUPTS <= 14 720 #define XCHAL_EXTINT14_NUM 0 721 #endif 722 #if XCHAL_NUM_EXTINTERRUPTS <= 15 723 #define XCHAL_EXTINT15_NUM 0 724 #endif 725 #if XCHAL_NUM_EXTINTERRUPTS <= 16 726 #define XCHAL_EXTINT16_NUM 0 727 #endif 728 #if XCHAL_NUM_EXTINTERRUPTS <= 17 729 #define XCHAL_EXTINT17_NUM 0 730 #endif 731 #if XCHAL_NUM_EXTINTERRUPTS <= 18 732 #define XCHAL_EXTINT18_NUM 0 733 #endif 734 #if XCHAL_NUM_EXTINTERRUPTS <= 19 735 #define XCHAL_EXTINT19_NUM 0 736 #endif 737 #if XCHAL_NUM_EXTINTERRUPTS <= 20 738 #define XCHAL_EXTINT20_NUM 0 739 #endif 740 #if XCHAL_NUM_EXTINTERRUPTS <= 21 741 #define XCHAL_EXTINT21_NUM 0 742 #endif 743 #if XCHAL_NUM_EXTINTERRUPTS <= 22 744 #define XCHAL_EXTINT22_NUM 0 745 #endif 746 #if XCHAL_NUM_EXTINTERRUPTS <= 23 747 #define XCHAL_EXTINT23_NUM 0 748 #endif 749 #if XCHAL_NUM_EXTINTERRUPTS <= 24 750 #define XCHAL_EXTINT24_NUM 0 751 #endif 752 #if XCHAL_NUM_EXTINTERRUPTS <= 25 753 #define XCHAL_EXTINT25_NUM 0 754 #endif 755 #if XCHAL_NUM_EXTINTERRUPTS <= 26 756 #define XCHAL_EXTINT26_NUM 0 757 #endif 758 #if XCHAL_NUM_EXTINTERRUPTS <= 27 759 #define XCHAL_EXTINT27_NUM 0 760 #endif 761 #if XCHAL_NUM_EXTINTERRUPTS <= 28 762 #define XCHAL_EXTINT28_NUM 0 763 #endif 764 #if XCHAL_NUM_EXTINTERRUPTS <= 29 765 #define XCHAL_EXTINT29_NUM 0 766 #endif 767 #if XCHAL_NUM_EXTINTERRUPTS <= 30 768 #define XCHAL_EXTINT30_NUM 0 769 #endif 770 #if XCHAL_NUM_EXTINTERRUPTS <= 31 771 #define XCHAL_EXTINT31_NUM 0 772 #endif 773 774 775 #define XTHAL_TIMER_UNCONFIGURED 0 776 777 #if XCHAL_NUM_INSTROM < 1 778 #define XCHAL_INSTROM0_PADDR 0 779 #define XCHAL_INSTROM0_SIZE 0 780 #endif 781 #if XCHAL_NUM_INSTROM < 2 782 #define XCHAL_INSTROM1_PADDR 0 783 #define XCHAL_INSTROM1_SIZE 0 784 #endif 785 #if XCHAL_NUM_INSTROM < 3 786 #define XCHAL_INSTROM2_PADDR 0 787 #define XCHAL_INSTROM2_SIZE 0 788 #endif 789 #if XCHAL_NUM_INSTROM < 4 790 #define XCHAL_INSTROM3_PADDR 0 791 #define XCHAL_INSTROM3_SIZE 0 792 #endif 793 #if XCHAL_NUM_INSTROM > MAX_NMEMORY 794 #error XCHAL_NUM_INSTROM > MAX_NMEMORY 795 #endif 796 797 #if XCHAL_NUM_INSTRAM < 1 798 #define XCHAL_INSTRAM0_PADDR 0 799 #define XCHAL_INSTRAM0_SIZE 0 800 #endif 801 #if XCHAL_NUM_INSTRAM < 2 802 #define XCHAL_INSTRAM1_PADDR 0 803 #define XCHAL_INSTRAM1_SIZE 0 804 #endif 805 #if XCHAL_NUM_INSTRAM < 3 806 #define XCHAL_INSTRAM2_PADDR 0 807 #define XCHAL_INSTRAM2_SIZE 0 808 #endif 809 #if XCHAL_NUM_INSTRAM < 4 810 #define XCHAL_INSTRAM3_PADDR 0 811 #define XCHAL_INSTRAM3_SIZE 0 812 #endif 813 #if XCHAL_NUM_INSTRAM > MAX_NMEMORY 814 #error XCHAL_NUM_INSTRAM > MAX_NMEMORY 815 #endif 816 817 #if XCHAL_NUM_DATAROM < 1 818 #define XCHAL_DATAROM0_PADDR 0 819 #define XCHAL_DATAROM0_SIZE 0 820 #endif 821 #if XCHAL_NUM_DATAROM < 2 822 #define XCHAL_DATAROM1_PADDR 0 823 #define XCHAL_DATAROM1_SIZE 0 824 #endif 825 #if XCHAL_NUM_DATAROM < 3 826 #define XCHAL_DATAROM2_PADDR 0 827 #define XCHAL_DATAROM2_SIZE 0 828 #endif 829 #if XCHAL_NUM_DATAROM < 4 830 #define XCHAL_DATAROM3_PADDR 0 831 #define XCHAL_DATAROM3_SIZE 0 832 #endif 833 #if XCHAL_NUM_DATAROM > MAX_NMEMORY 834 #error XCHAL_NUM_DATAROM > MAX_NMEMORY 835 #endif 836 837 #if XCHAL_NUM_DATARAM < 1 838 #define XCHAL_DATARAM0_PADDR 0 839 #define XCHAL_DATARAM0_SIZE 0 840 #endif 841 #if XCHAL_NUM_DATARAM < 2 842 #define XCHAL_DATARAM1_PADDR 0 843 #define XCHAL_DATARAM1_SIZE 0 844 #endif 845 #if XCHAL_NUM_DATARAM < 3 846 #define XCHAL_DATARAM2_PADDR 0 847 #define XCHAL_DATARAM2_SIZE 0 848 #endif 849 #if XCHAL_NUM_DATARAM < 4 850 #define XCHAL_DATARAM3_PADDR 0 851 #define XCHAL_DATARAM3_SIZE 0 852 #endif 853 #if XCHAL_NUM_DATARAM > MAX_NMEMORY 854 #error XCHAL_NUM_DATARAM > MAX_NMEMORY 855 #endif 856