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72d680e4 |
| 20-Jun-2022 |
Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> |
target/mips: introduce decodetree structure for Cavium Octeon extension
This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models.
Sign
target/mips: introduce decodetree structure for Cavium Octeon extension
This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Revision tags: v6.2.0, v6.1.0 |
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#
e0cbcf1e |
| 17-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc,pci,virtio: fixes, features Fixes all over the place. PXB support for ARM. boot index for vhost-
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc,pci,virtio: fixes, features Fixes all over the place. PXB support for ARM. boot index for vhost-user-fs. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 17 Jan 2021 11:44:55 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: acpi: Update _DSM method in expected files acpi: Enable pxb unit-test for ARM virt machine Kconfig: Compile PXB for ARM_VIRT acpi/gpex: Exclude pxb's resources from PCI0 acpi/gpex: Inform os to keep firmware resource map acpi: Add addr offset in build_crs acpi: Fix unmatched expected DSDT.pxb file acpi: Allow DSDT acpi table changes vhost-user-fs: add the "bootindex" property pci/shpc: don't push attention button when ejecting powered-off device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
825a215c |
| 15-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging audio: improvements for sdl, pulse, fsound. audio: cleanups & codestyle fixes. # gpg:
Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging audio: improvements for sdl, pulse, fsound. audio: cleanups & codestyle fixes. # gpg: Signature made Fri 15 Jan 2021 13:20:56 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/audio-20210115-pull-request: (30 commits) audio: space prohibited between function name and parenthesis'(' audio: Suspect code indent for conditional statements audio: Don't use '%#' in format strings audio: Fix lines over 90 characters audio: foo* bar" should be "foo *bar". audio: Add spaces around operator/delete redundant spaces audio: Add braces for statements/fix braces' position dsoundaudio: fix log message dsoundaudio: enable f32 audio sample format dsoundaudio: rename dsound_open() dsoundaudio: replace GetForegroundWindow() paaudio: send recorded data in smaller chunks paaudio: limit minreq to 75% of audio timer_rate paaudio: comment bugs in functions qpa_init_* paaudio: remove unneeded code paaudio: wait until the playback stream is ready paaudio: wait for PA_STREAM_READY in qpa_write() paaudio: avoid to clip samples multiple times audio: remove remaining unused plive code sdlaudio: enable (in|out).mixing-engine=off ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
7cb6b973 |
| 15-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210115-pull-request' into staging ui/gtk: refresh rate fixes. ui/vnc: add support for desktop resize and power contol. ui/vnc:
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210115-pull-request' into staging ui/gtk: refresh rate fixes. ui/vnc: add support for desktop resize and power contol. ui/vnc: misc bugfixes. # gpg: Signature made Fri 15 Jan 2021 10:24:10 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20210115-pull-request: vnc: add support for extended desktop resize vnc: move initialization to framebuffer_update_request vnc: move check into vnc_cursor_define vnc: Fix a memleak in vnc_display_connect() ui: add support for remote power control to VNC server vnc: fix unfinalized tlscreds for VncDisplay ui/gtk: update monitor interval on egl displays ui/gtk: expose gd_monitor_update_interval ui/gtk: limit virtual console max update interval ui/gtk: rename variable window to widget ui/gtk: don't try to redefine SI prefixes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
a968a380 |
| 15-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-next-2021-01-15' into staging Fix for CVE-2021-20181 # gpg: Signature made Fri 15 Jan 2021 08:52:19 GMT # gpg:
Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-next-2021-01-15' into staging Fix for CVE-2021-20181 # gpg: Signature made Fri 15 Jan 2021 08:52:19 GMT # gpg: using RSA key B4828BAF943140CEF2A3491071D4D5E5822F73D6 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full] # gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" [full] # gpg: aka "[jpeg image of size 3330]" [full] # Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6 * remotes/gkurz-gitlab/tags/9p-next-2021-01-15: 9pfs: Fully restart unreclaim loop (CVE-2021-20181) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
eaca8576 |
| 10-Jan-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Remove vendor specific CPU definitions Vendor specific CPU definitions are not very useful. Use the ISA definitions instead, which are more helpful when looking at the v
target/mips: Remove vendor specific CPU definitions Vendor specific CPU definitions are not very useful. Use the ISA definitions instead, which are more helpful when looking at the various CPU definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
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#
fc63010e |
| 10-Jan-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Remove CPU_NANOMIPS32 definition nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already defined as ISA_NANOMIPS32. Remove this incorrect definition and update the s
target/mips: Remove CPU_NANOMIPS32 definition nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already defined as ISA_NANOMIPS32. Remove this incorrect definition and update the single CPU implementing it, the I7200. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>
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6648042a |
| 10-Jan-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Remove CPU_R5900 definition Commit 823f2897bdd ("target/mips: Disable R5900 support") removed the single CPU using the CPU_R5900 definition. As it is unused, remove it.
target/mips: Remove CPU_R5900 definition Commit 823f2897bdd ("target/mips: Disable R5900 support") removed the single CPU using the CPU_R5900 definition. As it is unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-2-f4bug@amsat.org>
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7e2a619a |
| 29-Nov-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Remove now unused ASE_MSA definition We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Reviewed-by: Jiax
target/mips: Remove now unused ASE_MSA definition We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-6-f4bug@amsat.org>
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#
2e211e0a |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with t
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
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#
5f89ce4f |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with t
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
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#
bae4b15a |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with t
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-14-f4bug@amsat.org>
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#
7a47bae5 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signe
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
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#
bbd5e4a2 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signe
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-12-f4bug@amsat.org>
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13514fc9 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
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#
d913c399 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-10-f4bug@amsat.org>
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4d1524d2 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-9-f4bug@amsat.org>
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#
f395cef7 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
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08e2262f |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit.
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-7-f4bug@amsat.org>
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b0586b38 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and t
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
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8b0ea9b6 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
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bf552377 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Reorder CPU_MIPS5 definition Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.
target/mips/mips-defs: Reorder CPU_MIPS5 definition Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-3-f4bug@amsat.org>
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737cca57 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation"). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-2-f4bug@amsat.org>
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5acc270a |
| 25-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging target/xtensa fixes for 5.1: - fix access to special registers missing in the core configuration;
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging target/xtensa fixes for 5.1: - fix access to special registers missing in the core configuration; - fix simcall opcode behavior for new hardware; - drop gen_io_end call from xtensa translator. # gpg: Signature made Thu 25 Jun 2020 09:08:58 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20200625-xtensa: target/xtensa: drop gen_io_end call target/xtensa: fix simcall for newer hardware target/xtensa: fetch HW version from configuration overlay target/xtensa: work around missing SR definitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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cb8278cd |
| 16-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200616' into staging * hw: arm: Set vendor property for IMX SDHCI emulations * sd: sdhci: Implement basic vendor s
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200616' into staging * hw: arm: Set vendor property for IMX SDHCI emulations * sd: sdhci: Implement basic vendor specific register support * hw/net/imx_fec: Convert debug fprintf() to trace events * target/arm/cpu: adjust virtual time for all KVM arm cpus * Implement configurable descriptor size in ftgmac100 * hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers * target/arm: More Neon decodetree conversion work # gpg: Signature made Tue 16 Jun 2020 10:56:10 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200616: (23 commits) hw: arm: Set vendor property for IMX SDHCI emulations sd: sdhci: Implement basic vendor specific register support hw/net/imx_fec: Convert debug fprintf() to trace events target/arm/cpu: adjust virtual time for all KVM arm cpus Implement configurable descriptor size in ftgmac100 hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers target/arm: Convert Neon VDUP (scalar) to decodetree target/arm: Convert Neon VTBL, VTBX to decodetree target/arm: Convert Neon VEXT to decodetree target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree target/arm: Add missing TCG temp free in do_2shift_env_64() target/arm: Add 'static' and 'const' annotations to VSHLL function arrays target/arm: Convert Neon 3-reg-diff polynomial VMULL target/arm: Convert Neon 3-reg-diff saturating doubling multiplies target/arm: Convert Neon 3-reg-diff long multiplies target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/fsl-imx25.c # hw/arm/fsl-imx6.c # hw/arm/fsl-imx6ul.c # hw/arm/fsl-imx7.c
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