1 #ifndef QEMU_MIPS_DEFS_H 2 #define QEMU_MIPS_DEFS_H 3 4 /* Real pages are variable size... */ 5 #define MIPS_TLB_MAX 128 6 7 /* 8 * bit definitions for insn_flags (ISAs/ASEs flags) 9 * ------------------------------------------------ 10 */ 11 /* 12 * bits 0-23: MIPS base instruction sets 13 */ 14 #define ISA_MIPS1 0x0000000000000001ULL 15 #define ISA_MIPS2 0x0000000000000002ULL 16 #define ISA_MIPS3 0x0000000000000004ULL 17 #define ISA_MIPS4 0x0000000000000008ULL 18 #define ISA_MIPS5 0x0000000000000010ULL 19 #define ISA_MIPS32 0x0000000000000020ULL 20 #define ISA_MIPS32R2 0x0000000000000040ULL 21 #define ISA_MIPS64 0x0000000000000080ULL 22 #define ISA_MIPS64R2 0x0000000000000100ULL 23 #define ISA_MIPS32R3 0x0000000000000200ULL 24 #define ISA_MIPS64R3 0x0000000000000400ULL 25 #define ISA_MIPS32R5 0x0000000000000800ULL 26 #define ISA_MIPS64R5 0x0000000000001000ULL 27 #define ISA_MIPS32R6 0x0000000000002000ULL 28 #define ISA_MIPS64R6 0x0000000000004000ULL 29 #define ISA_NANOMIPS32 0x0000000000008000ULL 30 /* 31 * bits 24-39: MIPS ASEs 32 */ 33 #define ASE_MIPS16 0x0000000001000000ULL 34 #define ASE_MIPS3D 0x0000000002000000ULL 35 #define ASE_MDMX 0x0000000004000000ULL 36 #define ASE_DSP 0x0000000008000000ULL 37 #define ASE_DSP_R2 0x0000000010000000ULL 38 #define ASE_DSP_R3 0x0000000020000000ULL 39 #define ASE_MT 0x0000000040000000ULL 40 #define ASE_SMARTMIPS 0x0000000080000000ULL 41 #define ASE_MICROMIPS 0x0000000100000000ULL 42 #define ASE_MSA 0x0000000200000000ULL 43 /* 44 * bits 40-51: vendor-specific base instruction sets 45 */ 46 #define INSN_VR54XX 0x0000010000000000ULL 47 #define INSN_R5900 0x0000020000000000ULL 48 #define INSN_LOONGSON2E 0x0000040000000000ULL 49 #define INSN_LOONGSON2F 0x0000080000000000ULL 50 #define INSN_LOONGSON3A 0x0000100000000000ULL 51 /* 52 * bits 52-63: vendor-specific ASEs 53 */ 54 /* MultiMedia Instructions defined by R5900 */ 55 #define ASE_MMI 0x0010000000000000ULL 56 /* MIPS eXtension/enhanced Unit defined by Ingenic */ 57 #define ASE_MXU 0x0020000000000000ULL 58 /* Loongson MultiMedia Instructions */ 59 #define ASE_LMMI 0x0040000000000000ULL 60 /* Loongson EXTensions */ 61 #define ASE_LEXT 0x0080000000000000ULL 62 63 /* MIPS CPU defines. */ 64 #define CPU_MIPS1 (ISA_MIPS1) 65 #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) 66 #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) 67 #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) 68 #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) 69 #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) 70 #define CPU_R5900 (CPU_MIPS3 | INSN_R5900) 71 #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) 72 #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) 73 74 /* MIPS Technologies "Release 1" */ 75 #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) 76 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) 77 78 /* MIPS Technologies "Release 2" */ 79 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) 80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) 81 82 /* MIPS Technologies "Release 3" */ 83 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) 84 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) 85 86 /* MIPS Technologies "Release 5" */ 87 #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) 88 #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) 89 90 /* MIPS Technologies "Release 6" */ 91 #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) 92 #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) 93 94 /* Wave Computing: "nanoMIPS" */ 95 #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) 96 97 #define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT) 98 99 /* 100 * Strictly follow the architecture standard: 101 * - Disallow "special" instruction handling for PMON/SPIM. 102 * Note that we still maintain Count/Compare to match the host clock. 103 * 104 * #define MIPS_STRICT_STANDARD 1 105 */ 106 107 #endif /* QEMU_MIPS_DEFS_H */ 108