85eed507 | 13-Sep-2024 |
Michael Kowal <kowal@linux.ibm.com> |
pnv/xive2: TIMA CI ops using alternative offsets or byte lengths
Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_op
pnv/xive2: TIMA CI ops using alternative offsets or byte lengths
Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_opertions[] table entries are missing when they exist for other offsets/sizes and have been added: - lwz@0x810 Pull/Invalidate O/S Context to register added lwz@0x818 exists ld @0x818 exists - lwz@0x820 Pull Pool Context to register added lwz@0x828 exists ld @0x828 exists - lwz@0x830 Pull Thread Context to register added lbz@0x838 exists
Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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81939a92 | 13-Sep-2024 |
Glenn Miles <milesg@linux.vnet.ibm.com> |
ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC38 of the TIMA address space. When this offset is written to, the hardware dis
ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC38 of the TIMA address space. When this offset is written to, the hardware disables the thread context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the THREAD CAM entry.
Note that this operation is almost identical to what we are already doing for the "Pull OS Context to Odd Thread Reporting Line" operation except that it also invalidates the Pool and Thread Contexts.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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00a7a7a5 | 13-Sep-2024 |
Michael Kowal <kowal@linux.ibm.com> |
ppc/xive2: Change context/ring specific functions to be generic
Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate
ppc/xive2: Change context/ring specific functions to be generic
Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate on any ring/context. This will simplify the next patch sets that are adding additional ring/context operations.
Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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f82fec6c | 13-Sep-2024 |
Glenn Miles <milesg@linux.vnet.ibm.com> |
ppc/xive2: Support "Pull Thread Context to Register" operation
Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the har
ppc/xive2: Support "Pull Thread Context to Register" operation
Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the hardware to atomically: 1. Read the number of bytes requested (lbz or lhz are supported). 2. Reset the valid bit of the thread context. 3. Return the number of bytes requested in step 1 to a register.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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cfe9a7f2 | 13-Sep-2024 |
Glenn Miles <milesg@linux.vnet.ibm.com> |
ppc/xive2: Allow 1-byte write of Target field in TIMA
When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for wri
ppc/xive2: Allow 1-byte write of Target field in TIMA
When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for writes to the "TARGET" field which was added for XIVE GEN2. To fix this, we add special op support for 1-byte writes to this field.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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76798e12 | 13-Sep-2024 |
Frederic Barrat <fbarrat@linux.ibm.com> |
ppc/xive2: Dump the VP-group and crowd tables with 'info pic'
The 'info pic' HMP command dumps the state of the interrupt controller. Add the dump of the NVG and NVC tables to its output to ease deb
ppc/xive2: Dump the VP-group and crowd tables with 'info pic'
The 'info pic' HMP command dumps the state of the interrupt controller. Add the dump of the NVG and NVC tables to its output to ease debug.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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cfeafb0d | 13-Sep-2024 |
Frederic Barrat <fbarrat@linux.ibm.com> |
ppc/xive2: Dump more NVP state with 'info pic'
The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP belongs to a VP group.
Also, print the Reporting Cache Line address, if defined.
ppc/xive2: Dump more NVP state with 'info pic'
The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP belongs to a VP group.
Also, print the Reporting Cache Line address, if defined.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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cebfeb9e | 13-Sep-2024 |
Frederic Barrat <fbarrat@linux.ibm.com> |
ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware di
ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CAM entry.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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b9deafe7 | 13-Sep-2024 |
Frederic Barrat <fbarrat@linux.ibm.com> |
pnv/xive2: Define OGEN field in the TIMA
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This patch defines it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Mic
pnv/xive2: Define OGEN field in the TIMA
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This patch defines it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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a5330463 | 13-Sep-2024 |
Michael Kowal <kowal@linux.vnet.ibm.com> |
pnv/xive: TIMA patch sets pre-req alignment and formatting changes
Making some pre-requisite alignment changes ahead of the following patch sets. Making these changes now will ease the review of th
pnv/xive: TIMA patch sets pre-req alignment and formatting changes
Making some pre-requisite alignment changes ahead of the following patch sets. Making these changes now will ease the review of the patch sets.
Checkpatch wants the closing comment '*/' on a separate line, unless it is on the same line as the starting comment '/*'.
There are also changes to prevent lines from spanning 80 columns.
Changed block of defines from: #define A 1 /* original define comment is not * preferred, but not flagged... */ #define B 2 /* Newly added define comment * is flagged with a warning */ To: #define A 1 /* original define comment is */ /* now fine, no warning... */ #define B 2 /* Newly added define comment */ /* is fine... */
Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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07f27705 | 03-Nov-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc/xive: Fix ESB length overflow on 32-bit hosts
The length of this region can be > 32-bits, which overflows size_t on 32-bit hosts. Change to uint64_t.
Signed-off-by: Nicholas Piggin <npiggin@gma
ppc/xive: Fix ESB length overflow on 32-bit hosts
The length of this region can be > 32-bits, which overflows size_t on 32-bit hosts. Change to uint64_t.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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6fb6f309 | 28-Oct-2024 |
Amit Machhiwal <amachhiw@linux.ibm.com> |
spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0
The Power11 architected and raw mode support in Linux was merged via [1] and the corresponding support in QEMU is waiti
spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0
The Power11 architected and raw mode support in Linux was merged via [1] and the corresponding support in QEMU is waiting to be added by [2] which in V6 currently.
Add the Power11 capabilities and the required handling in TCG L0 implementation of the "Nested PAPR API".
Note: This patch is based on [2].
[1] https://lore.kernel.org/all/20240221044623.1598642-1-mpe@ellerman.id.au/ [2] https://lore.kernel.org/all/20240731055022.696051-1-adityag@linux.ibm.com/
Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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1d7e6318 | 18-Oct-2024 |
Amit Machhiwal <amachhiw@linux.ibm.com> |
spapr: nested: Add support for DPDES SPR in GSB for TCG L0
The DPDES support for doorbell emulation and handling for KVM on PAPR guests was added in Linux via [1]. Subsequently, a new GSB (Guest Sta
spapr: nested: Add support for DPDES SPR in GSB for TCG L0
The DPDES support for doorbell emulation and handling for KVM on PAPR guests was added in Linux via [1]. Subsequently, a new GSB (Guest State Buffer) element for DPDES was added in Linux; the same has been missing in TCG L0 implementation. Add support for DPDES register's APIv2 GSB element and required handling in `spapr_nested.c`.
Currently, booting a KVM guest inside a QEMU TCG guest fails with the following crash. The crash occurs while handling the GUEST_RUN_VCPU hcall made in TCG L0. In the hcall handling path, map_and_getset_state() calls getset_state(), which, in turn, calls guest_state_request_check() to validate the GSR (Guest State Request) elements. During this process, guest_state_request_check() iterates over the GSR elements and receives a NULL return code from guest_state_element_type_find() for the type variable corresponding to the DPDES register's elemetn ID (which was unknown to TCG L0). Subsequently, getset_state() returns H_P3, ultimately leading to the hcall failure and causing the KVM guest to crash.
KVM: unknown exit, hardware reason ffffffffffffffea [ ... KVM register dump ... ]
Fix this by adding the required support in TCG L0 implementation of APIv2.
[1] https://lore.kernel.org/all/20240605113913.83715-1-gautam@linux.ibm.com/
Fixes: 4a575f9a0567 ("spapr: nested: Initialize the GSB elements lookup table.") Suggested-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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c1a13064 | 14-Oct-2024 |
Harsh Prateek Bora <harshpb@linux.ibm.com> |
ppc/spapr: remove deprecated machine pseries-2.12
Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12 specific code with thi
ppc/spapr: remove deprecated machine pseries-2.12
Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12 specific code with this patch.
While at it, also remove pre-3.0-migration hacks introduced for backward compatibility which are now turned useless.
Suggested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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615ab788 | 14-Oct-2024 |
Harsh Prateek Bora <harshpb@linux.ibm.com> |
ppc/spapr: remove deprecated machine pseries-2.5
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.5 specific
ppc/spapr: remove deprecated machine pseries-2.5
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.5 specific code with this patch for now.
Also drop sPAPRMachineClass::use_ohci_by_default which is now useless.
Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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5fc9c717 | 24-Jul-2024 |
Frederic Barrat <fbarrat@linux.ibm.com> |
pnv/xive2: Dump more END state with 'info pic'
Additional END state 'info pic' information as added. The 'ignore', 'crowd' and 'precluded escalation control' bits of an Event Notification Descripto
pnv/xive2: Dump more END state with 'info pic'
Additional END state 'info pic' information as added. The 'ignore', 'crowd' and 'precluded escalation control' bits of an Event Notification Descriptor are all used when delivering an interrupt targeting a VP-group or crowd.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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bb44dc48 | 26-Jun-2024 |
Chalapathi V <chalapathi.v@linux.ibm.com> |
hw/ppc: SPI controller wiring to P10 chip
In this commit, create SPI controller on p10 chip and connect cs irq.
The QOM tree of pnv-spi and seeprom are. /machine (powernv10-machine) /chip[0] (pow
hw/ppc: SPI controller wiring to P10 chip
In this commit, create SPI controller on p10 chip and connect cs irq.
The QOM tree of pnv-spi and seeprom are. /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[2] (pnv-spi) /pnv-spi-bus.2 (SSI) /xscom-spi[0] (memory-region)
/machine (powernv10-machine) /peripheral-anon (container) /device[0] (25csm04) /WP#[0] (irq) /ssi-gpio-cs[0] (irq)
(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus" "/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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29318db1 | 26-Jun-2024 |
Chalapathi V <chalapathi.v@linux.ibm.com> |
hw/ssi: Add SPI model
SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function con
hw/ssi: Add SPI model
SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full control by firmware. In this commit SPI configuration component is modelled which contains all SPI configuration and status registers as well as the hold registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> [np: Fix FDT macro compile for qtest] Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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