1 /* 2 * QEMU PowerPC SPI model 3 * 4 * Copyright (c) 2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef PNV_SPI_CONTROLLER_REGS_H 10 #define PNV_SPI_CONTROLLER_REGS_H 11 12 /* 13 * Macros from target/ppc/cpu.h 14 * These macros are copied from ppc target specific file target/ppc/cpu.h 15 * as target/ppc/cpu.h cannot be included here. 16 */ 17 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) 18 #define PPC_BIT8(bit) (0x80 >> (bit)) 19 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) 20 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs)) 21 #define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1) 22 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) 23 #define SETFIELD(m, v, val) \ 24 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m))) 25 26 /* Error Register */ 27 #define ERROR_REG 0x00 28 29 /* counter_config_reg */ 30 #define SPI_CTR_CFG_REG 0x01 31 32 /* config_reg */ 33 #define CONFIG_REG1 0x02 34 35 /* clock_config_reset_control_ecc_enable_reg */ 36 #define SPI_CLK_CFG_REG 0x03 37 #define SPI_CLK_CFG_HARD_RST 0x0084000000000000; 38 #define SPI_CLK_CFG_RST_CTRL PPC_BITMASK(24, 27) 39 40 /* memory_mapping_reg */ 41 #define SPI_MM_REG 0x04 42 43 /* transmit_data_reg */ 44 #define SPI_XMIT_DATA_REG 0x05 45 46 /* receive_data_reg */ 47 #define SPI_RCV_DATA_REG 0x06 48 49 /* sequencer_operation_reg */ 50 #define SPI_SEQ_OP_REG 0x07 51 52 /* status_reg */ 53 #define SPI_STS_REG 0x08 54 #define SPI_STS_RDR_FULL PPC_BIT(0) 55 #define SPI_STS_RDR_OVERRUN PPC_BIT(1) 56 #define SPI_STS_RDR_UNDERRUN PPC_BIT(2) 57 #define SPI_STS_TDR_FULL PPC_BIT(4) 58 #define SPI_STS_TDR_OVERRUN PPC_BIT(5) 59 #define SPI_STS_TDR_UNDERRUN PPC_BIT(6) 60 #define SPI_STS_SEQ_FSM PPC_BITMASK(8, 15) 61 #define SPI_STS_SHIFTER_FSM PPC_BITMASK(16, 27) 62 #define SPI_STS_SEQ_INDEX PPC_BITMASK(28, 31) 63 #define SPI_STS_GEN_STATUS PPC_BITMASK(32, 63) 64 #define SPI_STS_RDR PPC_BITMASK(1, 3) 65 #define SPI_STS_TDR PPC_BITMASK(5, 7) 66 67 #endif 68