3eb43aeb | 07-Jun-2024 |
Joel Holdsworth <jholdsworth@nvidia.com> |
hw/openrisc: Fixed undercounting of TTCR in continuous mode
In the existing design, TTCR is prone to undercounting when running in continuous mode. This manifests as a timer interrupt appearing to t
hw/openrisc: Fixed undercounting of TTCR in continuous mode
In the existing design, TTCR is prone to undercounting when running in continuous mode. This manifests as a timer interrupt appearing to trigger a few cycles prior to the deadline set in SPR_TTMR_TP.
When the timer triggers, the virtual time delta in nanoseconds between the time when the timer was set, and when it triggers is calculated. This nanoseconds value is then divided by TIMER_PERIOD (50) to compute an increment of cycles to apply to TTCR.
However, this calculation rounds down the number of cycles causing the undercounting.
A simplistic solution would be to instead round up the number of cycles, however this will result in the accumulation of timing error over time.
This patch corrects the issue by calculating the time delta in nanoseconds between when the timer was last reset and the timer event. This approach allows the TTCR value to be rounded up, but without accumulating error over time.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com> [stafford: Incremented version in vmstate_or1k_timer, checkpatch fixes] Signed-off-by: Stafford Horne <shorne@gmail.com>
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c6fe3e6b | 22-Jun-2022 |
Jason A. Donenfeld <Jason@zx2c4.com> |
hw/openrisc: virt: pass random seed to fdt
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function.
hw/openrisc: virt: pass random seed to fdt
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This is confirmed to successfully initialize the RNG on Linux 5.19-rc2.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
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557e3707 | 14-Jun-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc: Initialize timer time at startup
The last_clk time was initialized at zero, this means when we calculate the first delta we will calculate 0 vs current time which could cause unnecessar
hw/openrisc: Initialize timer time at startup
The last_clk time was initialized at zero, this means when we calculate the first delta we will calculate 0 vs current time which could cause unnecessary hops.
This patch moves timer initialization to the cpu reset. There are two resets registered here:
1. Per cpu timer mask (ttmr) reset. 2. Global cpu timer (last_clk and ttcr) reset, attached to the first cpu only.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
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40fef82c | 12-Jun-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc: Add PCI bus support to virt
This is mostly borrowed from xtensa and riscv as examples. The create_pcie_irq_map swizzle function is almost and exact copy but here we use a single cell i
hw/openrisc: Add PCI bus support to virt
This is mostly borrowed from xtensa and riscv as examples. The create_pcie_irq_map swizzle function is almost and exact copy but here we use a single cell interrupt, possibly we can make this generic.
Signed-off-by: Stafford Horne <shorne@gmail.com>
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b5fcfe92 | 20-May-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc: Add the OpenRISC virtual machine
This patch adds the OpenRISC virtual machine 'virt' for OpenRISC. This platform allows for a convenient CI platform for toolchain, software ports and t
hw/openrisc: Add the OpenRISC virtual machine
This patch adds the OpenRISC virtual machine 'virt' for OpenRISC. This platform allows for a convenient CI platform for toolchain, software ports and the OpenRISC linux kernel port.
Much of this has been sourced from the m68k and riscv virt platforms.
The platform provides: - OpenRISC SMP with up to 4 cpus - A virtio bus with up to 8 devices - Standard ns16550a serial - Goldfish RTC - SiFive TEST device for poweroff and reboot - Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne <shorne@gmail.com>
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a92162f4 | 03-May-2022 |
Jason A. Donenfeld <Jason@zx2c4.com> |
hw/openrisc: use right OMPIC size variable
This appears to be a copy and paste error. The UART size was used instead of the much smaller OMPIC size. But actually that smaller OMPIC size is wrong too
hw/openrisc: use right OMPIC size variable
This appears to be a copy and paste error. The UART size was used instead of the much smaller OMPIC size. But actually that smaller OMPIC size is wrong too and doesn't allow the IPI to work in Linux. So set it to the old value.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX] Signed-off-by: Stafford Horne <shorne@gmail.com>
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777784bd | 02-May-2022 |
Jason A. Donenfeld <Jason@zx2c4.com> |
hw/openrisc: support 4 serial ports in or1ksim
The 8250 serial controller supports 4 serial ports, so wire them all up, so that we can have more than one basic I/O channel.
Cc: Stafford Horne <shor
hw/openrisc: support 4 serial ports in or1ksim
The 8250 serial controller supports 4 serial ports, so wire them all up, so that we can have more than one basic I/O channel.
Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [smh:Fixup indentation and lines over 80 chars] Signed-off-by: Stafford Horne <shorne@gmail.com>
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9576abf2 | 09-Feb-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc/openrisc_sim: Add support for initrd loading
The initrd passed via the command line is loaded into memory. It's location and size is then added to the device tree so the kernel knows wh
hw/openrisc/openrisc_sim: Add support for initrd loading
The initrd passed via the command line is loaded into memory. It's location and size is then added to the device tree so the kernel knows where to find it.
Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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5852c1f8 | 09-Feb-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc/openrisc_sim: Add automatic device tree generation
Using the device tree means that qemu can now directly tell the kernel what hardware is configured rather than use having to maintain a
hw/openrisc/openrisc_sim: Add automatic device tree generation
Using the device tree means that qemu can now directly tell the kernel what hardware is configured rather than use having to maintain and update a separate device tree file.
This patch adds automatic device tree generation support for the OpenRISC simulator. A device tree is built up based on the state of the configure openrisc simulator.
This is then dumped to memory and the load address is passed to the kernel in register r3.
Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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f42e09e6 | 18-Feb-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc/openrisc_sim: Increase max_cpus to 4
Now that we no longer have a limit of 2 CPUs due to fixing the IRQ routing issues we can increase the max. Here we increase the limit to 4, we could
hw/openrisc/openrisc_sim: Increase max_cpus to 4
Now that we no longer have a limit of 2 CPUs due to fixing the IRQ routing issues we can increase the max. Here we increase the limit to 4, we could go higher, but currently OMPIC has a limit of 4, so we align with that.
Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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22991cfb | 18-Feb-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART
Currently the OpenRISC SMP configuration only supports 2 cores due to the UART IRQ routing being limited to 2 cores. As was done in c
hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART
Currently the OpenRISC SMP configuration only supports 2 cores due to the UART IRQ routing being limited to 2 cores. As was done in commit 1eeffbeb11 ("hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs") we can use a splitter to wire more than 2 CPUs.
This patch moves serial initialization out to it's own function and uses a splitter to connect multiple CPU irq lines to the UART.
Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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76f36985 | 09-Feb-2022 |
Stafford Horne <shorne@gmail.com> |
hw/openrisc/openrisc_sim: Parameterize initialization
Move magic numbers to variables and enums. These will be reused for upcoming fdt initialization.
Signed-off-by: Stafford Horne <shorne@gmail.co
hw/openrisc/openrisc_sim: Parameterize initialization
Move magic numbers to variables and enums. These will be reused for upcoming fdt initialization.
Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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