arm_gic: QOM cast cleanup

Signed-off-by: Andreas Färber <afaerber@suse.de>

imx_avic: QOM cast cleanup

Introduce type constant, use QOM casts and prepare SysBus initfn for QOM
realize by resolving SysBusDevice vs. DeviceState "dev" name conflict.

Acked-by: Peter Chubb <pet

imx_avic: QOM cast cleanup

Introduce type constant, use QOM casts and prepare SysBus initfn for QOM
realize by resolving SysBusDevice vs. DeviceState "dev" name conflict.

Acked-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Andreas Färber <afaerber@suse.de>

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xics: rename types to be sane and follow coding style

Basically, in HW the layout of the interrupt network is:

- One ICP per processor thread (the "presenter"). This contains the
regis

xics: rename types to be sane and follow coding style

Basically, in HW the layout of the interrupt network is:

- One ICP per processor thread (the "presenter"). This contains the
registers to fetch a pending interrupt (ack), EOI, and control the
processor priority.

- One ICS per logical source of interrupts (ie, one per PCI host
bridge, and a few others here or there). This contains the per-interrupt
source configuration (target processor(s), priority, mask) and the
per-interrupt internal state.

Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit
oddball what pHyp does here, arguably there are two but we can ignore
that distinction). There is no register level access. A pair of firmware
(RTAS) calls is used to configure each virtual interrupt.

So our model here is somewhat the same. We have one ICS in the emulated
XICS which arguably *is* the emulated XICS, there's no point making it a
separate "device", that would just be gross, and each VCPU has an
associated ICP.

Yet we call the "XICS" struct icp_state and then the ICPs
'struct icp_server_state'. It's particularly confusing when all of the
functions have xics_prefixes yet take *icp arguments.

Rename:

struct icp_state -> XICSState
struct icp_server_state -> ICPState
struct ics_state -> ICSState
struct ics_irq_state -> ICSIRQState

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-id: 1374175984-8930-12-git-send-email-aliguori@us.ibm.com
[aik: added ics_resend() on post_load]
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>

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ioapic: Use QOM realize for ioapic

Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
[AF: Tweaked error message]
Signed-off-by: Andreas Färber <afaerber@suse.de>

pseries: move interrupt controllers to hw/intc/

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>

intc/openpic: Build openpic only once

Since current_cpu is CPUState it no longer depends on CPUPPCState.

Move ppce500_set_mpic_proxy() to a new hw/ppc/ppc_e500.h because
hw/ppc/ppc.h is too heavily

intc/openpic: Build openpic only once

Since current_cpu is CPUState it no longer depends on CPUPPCState.

Move ppce500_set_mpic_proxy() to a new hw/ppc/ppc_e500.h because
hw/ppc/ppc.h is too heavily using CPUPPCState and PowerPCCPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>

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intc/arm_gic: Build arm_gic only once

Since current_cpu is CPUState it no longer needs CPUArchState.

Signed-off-by: Andreas Färber <afaerber@suse.de>

cpu: Make first_cpu and next_cpu CPUState

Move next_cpu from CPU_COMMON to CPUState.
Move first_cpu variable to qom/cpu.h.

gdbstub needs to use CPUState::env_ptr for now.
cpu_copy() no longer needs

cpu: Make first_cpu and next_cpu CPUState

Move next_cpu from CPU_COMMON to CPUState.
Move first_cpu variable to qom/cpu.h.

gdbstub needs to use CPUState::env_ptr for now.
cpu_copy() no longer needs to save and restore cpu_next.

Acked-by: Paolo Bonzini <pbonzini@redhat.com>
[AF: Rebased, simplified cpu_copy()]
Signed-off-by: Andreas Färber <afaerber@suse.de>

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cpu: Replace cpu_single_env with CPUState current_cpu

Move it to qom/cpu.h.

Signed-off-by: Andreas Färber <afaerber@suse.de>

hw/i*: pass owner to memory_region_init* functions

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

memory: add owner argument to initialization functions

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

intc/openpic_kvm: Fix QOM and build issues

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>

intc/openpic: Convert to QOM realize

Split qdev initfn into instance_init and realize functions.
Change one occurrence of "klass" while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Revie

intc/openpic: Convert to QOM realize

Split qdev initfn into instance_init and realize functions.
Change one occurrence of "klass" while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

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intc/openpic: QOM'ify

Introduce type constant and cast macro.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alexander

intc/openpic: QOM'ify

Introduce type constant and cast macro.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

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kvm/openpic: in-kernel mpic support

Enables support for the in-kernel MPIC that thas been merged into the
KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex
Graf (along with some o

kvm/openpic: in-kernel mpic support

Enables support for the in-kernel MPIC that thas been merged into the
KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex
Graf (along with some other improvements).

Note from Alex regarding kvm_irqchip_create():

On x86, one would call kvm_irqchip_create() to initialize an
in-kernel interrupt controller. That function then goes ahead and
initializes global capability variables as well as the default irq
routing table.

On ppc, we can't call kvm_irqchip_create() because we can have
different types of interrupt controllers. So we want to do all the
things that function would do for us in the in-kernel device init
handler.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build,
fix ppcemb]
Signed-off-by: Alexander Graf <agraf@suse.de>

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openpic: factor out some common defines into openpic.h

...for use by the KVM in-kernel irqchip stub.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

intc/xilinx_intc: Dont lower IRQ when HIE cleared

This is a little strange. It is lowering the parent IRQ pin on input
when HIE is cleared. There is no such behaviour in the real hardware.

ISR chan

intc/xilinx_intc: Dont lower IRQ when HIE cleared

This is a little strange. It is lowering the parent IRQ pin on input
when HIE is cleared. There is no such behaviour in the real hardware.

ISR changes based on interrupt pin state are already guarded on HIE
being set. So we can just delete this if in its entirety.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

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intc/xilinx_intc: Inhibit write to ISR when HIE

When the Hardware Interrupt Enable (HIE) bit is set, software cannot
change ISR. Add write guard accordingly.

Signed-off-by: Peter Crosthwaite <peter

intc/xilinx_intc: Inhibit write to ISR when HIE

When the Hardware Interrupt Enable (HIE) bit is set, software cannot
change ISR. Add write guard accordingly.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

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intc/xilinx_intc: Handle level interrupt retriggering

Acking a level sensitive interrupt should have no effect if the
interrupt pin is still asserted. The current implementation requires
and edge co

intc/xilinx_intc: Handle level interrupt retriggering

Acking a level sensitive interrupt should have no effect if the
interrupt pin is still asserted. The current implementation requires
and edge condition to occur for setting a level sensitive IRQ, which
means an ACK can clear a level sensitive interrupt, until the original
source strobes the interrupt again.

Fix by keeping track of the interrupt pin state and setting ISR based
on this every time update_irq() is called.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

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intc/xilinx_intc: Don't clear level sens. IRQs without ACK

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (vi

intc/xilinx_intc: Don't clear level sens. IRQs without ACK

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

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Merge branch 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu

* 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu:
qdev: Drop FROM_QBUS() macro
isa: QOM'ify ISADevice
isa: QOM'ify I

Merge branch 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu

* 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu:
qdev: Drop FROM_QBUS() macro
isa: QOM'ify ISADevice
isa: QOM'ify ISABus
i8259: Convert PICCommonState to use QOM realizefn
kvm/i8259: QOM'ify some more
i8259: QOM'ify some more
i8254: Convert PITCommonState to QOM realizefn
kvm/i8254: QOM'ify some more
i8254: QOM'ify some more
isa: Use realizefn for ISADevice
cs4231a: QOM'ify some more
gus: QOM'ify some more

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intc/xilinx_intc: Use qemu_set_irq

Use qemu_set_irq rather than if-elsing qemu_irq_(lower|raise). No
functional change, just reduces verbosity.

Cc: qemu-trivial@nongnu.org

Signed-off-by: Peter Cro

intc/xilinx_intc: Use qemu_set_irq

Use qemu_set_irq rather than if-elsing qemu_irq_(lower|raise). No
functional change, just reduces verbosity.

Cc: qemu-trivial@nongnu.org

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

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isa: QOM'ify ISADevice

Rename its parent field and use DEVICE() where necessary.

Signed-off-by: Andreas Färber <afaerber@suse.de>

i8259: Convert PICCommonState to use QOM realizefn

Instead of having the parent provide PICCommonClass::init,
let the children override DeviceClass::realize themselves.
This pushes the responsibilit

i8259: Convert PICCommonState to use QOM realizefn

Instead of having the parent provide PICCommonClass::init,
let the children override DeviceClass::realize themselves.
This pushes the responsibility of saving and calling the parent's
realizefn to the children.

Signed-off-by: Andreas Färber <afaerber@suse.de>

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i8259: QOM'ify some more

Introduce type constant.

Prepares for PIC realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>