1 /* 2 * OpenPIC emulation 3 * 4 * Copyright (c) 2004 Jocelyn Mayer 5 * 2011 Alexander Graf 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * 27 * Based on OpenPic implementations: 28 * - Intel GW80314 I/O companion chip developer's manual 29 * - Motorola MPC8245 & MPC8540 user manuals. 30 * - Motorola MCP750 (aka Raven) programmer manual. 31 * - Motorola Harrier programmer manuel 32 * 33 * Serial interrupts, as implemented in Raven chipset are not supported yet. 34 * 35 */ 36 #include "hw/hw.h" 37 #include "hw/ppc/mac.h" 38 #include "hw/pci/pci.h" 39 #include "hw/ppc/openpic.h" 40 #include "hw/sysbus.h" 41 #include "hw/pci/msi.h" 42 #include "qemu/bitops.h" 43 #include "hw/ppc/ppc.h" 44 45 //#define DEBUG_OPENPIC 46 47 #ifdef DEBUG_OPENPIC 48 static const int debug_openpic = 1; 49 #else 50 static const int debug_openpic = 0; 51 #endif 52 53 #define DPRINTF(fmt, ...) do { \ 54 if (debug_openpic) { \ 55 printf(fmt , ## __VA_ARGS__); \ 56 } \ 57 } while (0) 58 59 #define MAX_CPU 32 60 #define MAX_MSI 8 61 #define VID 0x03 /* MPIC version ID */ 62 63 /* OpenPIC capability flags */ 64 #define OPENPIC_FLAG_IDR_CRIT (1 << 0) 65 #define OPENPIC_FLAG_ILR (2 << 0) 66 67 /* OpenPIC address map */ 68 #define OPENPIC_GLB_REG_START 0x0 69 #define OPENPIC_GLB_REG_SIZE 0x10F0 70 #define OPENPIC_TMR_REG_START 0x10F0 71 #define OPENPIC_TMR_REG_SIZE 0x220 72 #define OPENPIC_MSI_REG_START 0x1600 73 #define OPENPIC_MSI_REG_SIZE 0x200 74 #define OPENPIC_SUMMARY_REG_START 0x3800 75 #define OPENPIC_SUMMARY_REG_SIZE 0x800 76 #define OPENPIC_SRC_REG_START 0x10000 77 #define OPENPIC_SRC_REG_SIZE (OPENPIC_MAX_SRC * 0x20) 78 #define OPENPIC_CPU_REG_START 0x20000 79 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) 80 81 /* Raven */ 82 #define RAVEN_MAX_CPU 2 83 #define RAVEN_MAX_EXT 48 84 #define RAVEN_MAX_IRQ 64 85 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR 86 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI 87 88 /* Interrupt definitions */ 89 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ 90 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ 91 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ 92 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ 93 /* First doorbell IRQ */ 94 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) 95 96 typedef struct FslMpicInfo { 97 int max_ext; 98 } FslMpicInfo; 99 100 static FslMpicInfo fsl_mpic_20 = { 101 .max_ext = 12, 102 }; 103 104 static FslMpicInfo fsl_mpic_42 = { 105 .max_ext = 12, 106 }; 107 108 #define FRR_NIRQ_SHIFT 16 109 #define FRR_NCPU_SHIFT 8 110 #define FRR_VID_SHIFT 0 111 112 #define VID_REVISION_1_2 2 113 #define VID_REVISION_1_3 3 114 115 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ 116 117 #define GCR_RESET 0x80000000 118 #define GCR_MODE_PASS 0x00000000 119 #define GCR_MODE_MIXED 0x20000000 120 #define GCR_MODE_PROXY 0x60000000 121 122 #define TBCR_CI 0x80000000 /* count inhibit */ 123 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ 124 125 #define IDR_EP_SHIFT 31 126 #define IDR_EP_MASK (1 << IDR_EP_SHIFT) 127 #define IDR_CI0_SHIFT 30 128 #define IDR_CI1_SHIFT 29 129 #define IDR_P1_SHIFT 1 130 #define IDR_P0_SHIFT 0 131 132 #define ILR_INTTGT_MASK 0x000000ff 133 #define ILR_INTTGT_INT 0x00 134 #define ILR_INTTGT_CINT 0x01 /* critical */ 135 #define ILR_INTTGT_MCP 0x02 /* machine check */ 136 137 /* The currently supported INTTGT values happen to be the same as QEMU's 138 * openpic output codes, but don't depend on this. The output codes 139 * could change (unlikely, but...) or support could be added for 140 * more INTTGT values. 141 */ 142 static const int inttgt_output[][2] = { 143 { ILR_INTTGT_INT, OPENPIC_OUTPUT_INT }, 144 { ILR_INTTGT_CINT, OPENPIC_OUTPUT_CINT }, 145 { ILR_INTTGT_MCP, OPENPIC_OUTPUT_MCK }, 146 }; 147 148 static int inttgt_to_output(int inttgt) 149 { 150 int i; 151 152 for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) { 153 if (inttgt_output[i][0] == inttgt) { 154 return inttgt_output[i][1]; 155 } 156 } 157 158 fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt); 159 return OPENPIC_OUTPUT_INT; 160 } 161 162 static int output_to_inttgt(int output) 163 { 164 int i; 165 166 for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) { 167 if (inttgt_output[i][1] == output) { 168 return inttgt_output[i][0]; 169 } 170 } 171 172 abort(); 173 } 174 175 #define MSIIR_OFFSET 0x140 176 #define MSIIR_SRS_SHIFT 29 177 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT) 178 #define MSIIR_IBS_SHIFT 24 179 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT) 180 181 static int get_current_cpu(void) 182 { 183 CPUState *cpu_single_cpu; 184 185 if (!cpu_single_env) { 186 return -1; 187 } 188 189 cpu_single_cpu = ENV_GET_CPU(cpu_single_env); 190 return cpu_single_cpu->cpu_index; 191 } 192 193 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, 194 int idx); 195 static void openpic_cpu_write_internal(void *opaque, hwaddr addr, 196 uint32_t val, int idx); 197 198 typedef enum IRQType { 199 IRQ_TYPE_NORMAL = 0, 200 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ 201 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ 202 } IRQType; 203 204 typedef struct IRQQueue { 205 /* Round up to the nearest 64 IRQs so that the queue length 206 * won't change when moving between 32 and 64 bit hosts. 207 */ 208 unsigned long queue[BITS_TO_LONGS((OPENPIC_MAX_IRQ + 63) & ~63)]; 209 int next; 210 int priority; 211 } IRQQueue; 212 213 typedef struct IRQSource { 214 uint32_t ivpr; /* IRQ vector/priority register */ 215 uint32_t idr; /* IRQ destination register */ 216 uint32_t destmask; /* bitmap of CPU destinations */ 217 int last_cpu; 218 int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ 219 int pending; /* TRUE if IRQ is pending */ 220 IRQType type; 221 bool level:1; /* level-triggered */ 222 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ 223 } IRQSource; 224 225 #define IVPR_MASK_SHIFT 31 226 #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) 227 #define IVPR_ACTIVITY_SHIFT 30 228 #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT) 229 #define IVPR_MODE_SHIFT 29 230 #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT) 231 #define IVPR_POLARITY_SHIFT 23 232 #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT) 233 #define IVPR_SENSE_SHIFT 22 234 #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT) 235 236 #define IVPR_PRIORITY_MASK (0xF << 16) 237 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) 238 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) 239 240 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ 241 #define IDR_EP 0x80000000 /* external pin */ 242 #define IDR_CI 0x40000000 /* critical interrupt */ 243 244 typedef struct IRQDest { 245 int32_t ctpr; /* CPU current task priority */ 246 IRQQueue raised; 247 IRQQueue servicing; 248 qemu_irq *irqs; 249 250 /* Count of IRQ sources asserting on non-INT outputs */ 251 uint32_t outputs_active[OPENPIC_OUTPUT_NB]; 252 } IRQDest; 253 254 #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC) 255 256 typedef struct OpenPICState { 257 /*< private >*/ 258 SysBusDevice parent_obj; 259 /*< public >*/ 260 261 MemoryRegion mem; 262 263 /* Behavior control */ 264 FslMpicInfo *fsl; 265 uint32_t model; 266 uint32_t flags; 267 uint32_t nb_irqs; 268 uint32_t vid; 269 uint32_t vir; /* Vendor identification register */ 270 uint32_t vector_mask; 271 uint32_t tfrr_reset; 272 uint32_t ivpr_reset; 273 uint32_t idr_reset; 274 uint32_t brr1; 275 uint32_t mpic_mode_mask; 276 277 /* Sub-regions */ 278 MemoryRegion sub_io_mem[6]; 279 280 /* Global registers */ 281 uint32_t frr; /* Feature reporting register */ 282 uint32_t gcr; /* Global configuration register */ 283 uint32_t pir; /* Processor initialization register */ 284 uint32_t spve; /* Spurious vector register */ 285 uint32_t tfrr; /* Timer frequency reporting register */ 286 /* Source registers */ 287 IRQSource src[OPENPIC_MAX_IRQ]; 288 /* Local registers per output pin */ 289 IRQDest dst[MAX_CPU]; 290 uint32_t nb_cpus; 291 /* Timer registers */ 292 struct { 293 uint32_t tccr; /* Global timer current count register */ 294 uint32_t tbcr; /* Global timer base count register */ 295 } timers[OPENPIC_MAX_TMR]; 296 /* Shared MSI registers */ 297 struct { 298 uint32_t msir; /* Shared Message Signaled Interrupt Register */ 299 } msi[MAX_MSI]; 300 uint32_t max_irq; 301 uint32_t irq_ipi0; 302 uint32_t irq_tim0; 303 uint32_t irq_msi; 304 } OpenPICState; 305 306 static inline void IRQ_setbit(IRQQueue *q, int n_IRQ) 307 { 308 set_bit(n_IRQ, q->queue); 309 } 310 311 static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ) 312 { 313 clear_bit(n_IRQ, q->queue); 314 } 315 316 static inline int IRQ_testbit(IRQQueue *q, int n_IRQ) 317 { 318 return test_bit(n_IRQ, q->queue); 319 } 320 321 static void IRQ_check(OpenPICState *opp, IRQQueue *q) 322 { 323 int irq = -1; 324 int next = -1; 325 int priority = -1; 326 327 for (;;) { 328 irq = find_next_bit(q->queue, opp->max_irq, irq + 1); 329 if (irq == opp->max_irq) { 330 break; 331 } 332 333 DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n", 334 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); 335 336 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { 337 next = irq; 338 priority = IVPR_PRIORITY(opp->src[irq].ivpr); 339 } 340 } 341 342 q->next = next; 343 q->priority = priority; 344 } 345 346 static int IRQ_get_next(OpenPICState *opp, IRQQueue *q) 347 { 348 /* XXX: optimize */ 349 IRQ_check(opp, q); 350 351 return q->next; 352 } 353 354 static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, 355 bool active, bool was_active) 356 { 357 IRQDest *dst; 358 IRQSource *src; 359 int priority; 360 361 dst = &opp->dst[n_CPU]; 362 src = &opp->src[n_IRQ]; 363 364 DPRINTF("%s: IRQ %d active %d was %d\n", 365 __func__, n_IRQ, active, was_active); 366 367 if (src->output != OPENPIC_OUTPUT_INT) { 368 DPRINTF("%s: output %d irq %d active %d was %d count %d\n", 369 __func__, src->output, n_IRQ, active, was_active, 370 dst->outputs_active[src->output]); 371 372 /* On Freescale MPIC, critical interrupts ignore priority, 373 * IACK, EOI, etc. Before MPIC v4.1 they also ignore 374 * masking. 375 */ 376 if (active) { 377 if (!was_active && dst->outputs_active[src->output]++ == 0) { 378 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n", 379 __func__, src->output, n_CPU, n_IRQ); 380 qemu_irq_raise(dst->irqs[src->output]); 381 } 382 } else { 383 if (was_active && --dst->outputs_active[src->output] == 0) { 384 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n", 385 __func__, src->output, n_CPU, n_IRQ); 386 qemu_irq_lower(dst->irqs[src->output]); 387 } 388 } 389 390 return; 391 } 392 393 priority = IVPR_PRIORITY(src->ivpr); 394 395 /* Even if the interrupt doesn't have enough priority, 396 * it is still raised, in case ctpr is lowered later. 397 */ 398 if (active) { 399 IRQ_setbit(&dst->raised, n_IRQ); 400 } else { 401 IRQ_resetbit(&dst->raised, n_IRQ); 402 } 403 404 IRQ_check(opp, &dst->raised); 405 406 if (active && priority <= dst->ctpr) { 407 DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", 408 __func__, n_IRQ, priority, dst->ctpr, n_CPU); 409 active = 0; 410 } 411 412 if (active) { 413 if (IRQ_get_next(opp, &dst->servicing) >= 0 && 414 priority <= dst->servicing.priority) { 415 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", 416 __func__, n_IRQ, dst->servicing.next, n_CPU); 417 } else { 418 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", 419 __func__, n_CPU, n_IRQ, dst->raised.next); 420 qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); 421 } 422 } else { 423 IRQ_get_next(opp, &dst->servicing); 424 if (dst->raised.priority > dst->ctpr && 425 dst->raised.priority > dst->servicing.priority) { 426 DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n", 427 __func__, n_IRQ, dst->raised.next, dst->raised.priority, 428 dst->ctpr, dst->servicing.priority, n_CPU); 429 /* IRQ line stays asserted */ 430 } else { 431 DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", 432 __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU); 433 qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); 434 } 435 } 436 } 437 438 /* update pic state because registers for n_IRQ have changed value */ 439 static void openpic_update_irq(OpenPICState *opp, int n_IRQ) 440 { 441 IRQSource *src; 442 bool active, was_active; 443 int i; 444 445 src = &opp->src[n_IRQ]; 446 active = src->pending; 447 448 if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { 449 /* Interrupt source is disabled */ 450 DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); 451 active = false; 452 } 453 454 was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); 455 456 /* 457 * We don't have a similar check for already-active because 458 * ctpr may have changed and we need to withdraw the interrupt. 459 */ 460 if (!active && !was_active) { 461 DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ); 462 return; 463 } 464 465 if (active) { 466 src->ivpr |= IVPR_ACTIVITY_MASK; 467 } else { 468 src->ivpr &= ~IVPR_ACTIVITY_MASK; 469 } 470 471 if (src->destmask == 0) { 472 /* No target */ 473 DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); 474 return; 475 } 476 477 if (src->destmask == (1 << src->last_cpu)) { 478 /* Only one CPU is allowed to receive this IRQ */ 479 IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); 480 } else if (!(src->ivpr & IVPR_MODE_MASK)) { 481 /* Directed delivery mode */ 482 for (i = 0; i < opp->nb_cpus; i++) { 483 if (src->destmask & (1 << i)) { 484 IRQ_local_pipe(opp, i, n_IRQ, active, was_active); 485 } 486 } 487 } else { 488 /* Distributed delivery mode */ 489 for (i = src->last_cpu + 1; i != src->last_cpu; i++) { 490 if (i == opp->nb_cpus) { 491 i = 0; 492 } 493 if (src->destmask & (1 << i)) { 494 IRQ_local_pipe(opp, i, n_IRQ, active, was_active); 495 src->last_cpu = i; 496 break; 497 } 498 } 499 } 500 } 501 502 static void openpic_set_irq(void *opaque, int n_IRQ, int level) 503 { 504 OpenPICState *opp = opaque; 505 IRQSource *src; 506 507 if (n_IRQ >= OPENPIC_MAX_IRQ) { 508 fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ); 509 abort(); 510 } 511 512 src = &opp->src[n_IRQ]; 513 DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n", 514 n_IRQ, level, src->ivpr); 515 if (src->level) { 516 /* level-sensitive irq */ 517 src->pending = level; 518 openpic_update_irq(opp, n_IRQ); 519 } else { 520 /* edge-sensitive irq */ 521 if (level) { 522 src->pending = 1; 523 openpic_update_irq(opp, n_IRQ); 524 } 525 526 if (src->output != OPENPIC_OUTPUT_INT) { 527 /* Edge-triggered interrupts shouldn't be used 528 * with non-INT delivery, but just in case, 529 * try to make it do something sane rather than 530 * cause an interrupt storm. This is close to 531 * what you'd probably see happen in real hardware. 532 */ 533 src->pending = 0; 534 openpic_update_irq(opp, n_IRQ); 535 } 536 } 537 } 538 539 static void openpic_reset(DeviceState *d) 540 { 541 OpenPICState *opp = OPENPIC(d); 542 int i; 543 544 opp->gcr = GCR_RESET; 545 /* Initialise controller registers */ 546 opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) | 547 ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) | 548 (opp->vid << FRR_VID_SHIFT); 549 550 opp->pir = 0; 551 opp->spve = -1 & opp->vector_mask; 552 opp->tfrr = opp->tfrr_reset; 553 /* Initialise IRQ sources */ 554 for (i = 0; i < opp->max_irq; i++) { 555 opp->src[i].ivpr = opp->ivpr_reset; 556 opp->src[i].idr = opp->idr_reset; 557 558 switch (opp->src[i].type) { 559 case IRQ_TYPE_NORMAL: 560 opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK); 561 break; 562 563 case IRQ_TYPE_FSLINT: 564 opp->src[i].ivpr |= IVPR_POLARITY_MASK; 565 break; 566 567 case IRQ_TYPE_FSLSPECIAL: 568 break; 569 } 570 } 571 /* Initialise IRQ destinations */ 572 for (i = 0; i < MAX_CPU; i++) { 573 opp->dst[i].ctpr = 15; 574 memset(&opp->dst[i].raised, 0, sizeof(IRQQueue)); 575 opp->dst[i].raised.next = -1; 576 memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue)); 577 opp->dst[i].servicing.next = -1; 578 } 579 /* Initialise timers */ 580 for (i = 0; i < OPENPIC_MAX_TMR; i++) { 581 opp->timers[i].tccr = 0; 582 opp->timers[i].tbcr = TBCR_CI; 583 } 584 /* Go out of RESET state */ 585 opp->gcr = 0; 586 } 587 588 static inline uint32_t read_IRQreg_idr(OpenPICState *opp, int n_IRQ) 589 { 590 return opp->src[n_IRQ].idr; 591 } 592 593 static inline uint32_t read_IRQreg_ilr(OpenPICState *opp, int n_IRQ) 594 { 595 if (opp->flags & OPENPIC_FLAG_ILR) { 596 return output_to_inttgt(opp->src[n_IRQ].output); 597 } 598 599 return 0xffffffff; 600 } 601 602 static inline uint32_t read_IRQreg_ivpr(OpenPICState *opp, int n_IRQ) 603 { 604 return opp->src[n_IRQ].ivpr; 605 } 606 607 static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val) 608 { 609 IRQSource *src = &opp->src[n_IRQ]; 610 uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; 611 uint32_t crit_mask = 0; 612 uint32_t mask = normal_mask; 613 int crit_shift = IDR_EP_SHIFT - opp->nb_cpus; 614 int i; 615 616 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { 617 crit_mask = mask << crit_shift; 618 mask |= crit_mask | IDR_EP; 619 } 620 621 src->idr = val & mask; 622 DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); 623 624 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { 625 if (src->idr & crit_mask) { 626 if (src->idr & normal_mask) { 627 DPRINTF("%s: IRQ configured for multiple output types, using " 628 "critical\n", __func__); 629 } 630 631 src->output = OPENPIC_OUTPUT_CINT; 632 src->nomask = true; 633 src->destmask = 0; 634 635 for (i = 0; i < opp->nb_cpus; i++) { 636 int n_ci = IDR_CI0_SHIFT - i; 637 638 if (src->idr & (1UL << n_ci)) { 639 src->destmask |= 1UL << i; 640 } 641 } 642 } else { 643 src->output = OPENPIC_OUTPUT_INT; 644 src->nomask = false; 645 src->destmask = src->idr & normal_mask; 646 } 647 } else { 648 src->destmask = src->idr; 649 } 650 } 651 652 static inline void write_IRQreg_ilr(OpenPICState *opp, int n_IRQ, uint32_t val) 653 { 654 if (opp->flags & OPENPIC_FLAG_ILR) { 655 IRQSource *src = &opp->src[n_IRQ]; 656 657 src->output = inttgt_to_output(val & ILR_INTTGT_MASK); 658 DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, 659 src->output); 660 661 /* TODO: on MPIC v4.0 only, set nomask for non-INT */ 662 } 663 } 664 665 static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) 666 { 667 uint32_t mask; 668 669 /* NOTE when implementing newer FSL MPIC models: starting with v4.0, 670 * the polarity bit is read-only on internal interrupts. 671 */ 672 mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK | 673 IVPR_POLARITY_MASK | opp->vector_mask; 674 675 /* ACTIVITY bit is read-only */ 676 opp->src[n_IRQ].ivpr = 677 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); 678 679 /* For FSL internal interrupts, The sense bit is reserved and zero, 680 * and the interrupt is always level-triggered. Timers and IPIs 681 * have no sense or polarity bits, and are edge-triggered. 682 */ 683 switch (opp->src[n_IRQ].type) { 684 case IRQ_TYPE_NORMAL: 685 opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); 686 break; 687 688 case IRQ_TYPE_FSLINT: 689 opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; 690 break; 691 692 case IRQ_TYPE_FSLSPECIAL: 693 opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); 694 break; 695 } 696 697 openpic_update_irq(opp, n_IRQ); 698 DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, 699 opp->src[n_IRQ].ivpr); 700 } 701 702 static void openpic_gcr_write(OpenPICState *opp, uint64_t val) 703 { 704 bool mpic_proxy = false; 705 706 if (val & GCR_RESET) { 707 openpic_reset(DEVICE(opp)); 708 return; 709 } 710 711 opp->gcr &= ~opp->mpic_mode_mask; 712 opp->gcr |= val & opp->mpic_mode_mask; 713 714 /* Set external proxy mode */ 715 if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { 716 mpic_proxy = true; 717 } 718 719 ppce500_set_mpic_proxy(mpic_proxy); 720 } 721 722 static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, 723 unsigned len) 724 { 725 OpenPICState *opp = opaque; 726 IRQDest *dst; 727 int idx; 728 729 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", 730 __func__, addr, val); 731 if (addr & 0xF) { 732 return; 733 } 734 switch (addr) { 735 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ 736 break; 737 case 0x40: 738 case 0x50: 739 case 0x60: 740 case 0x70: 741 case 0x80: 742 case 0x90: 743 case 0xA0: 744 case 0xB0: 745 openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); 746 break; 747 case 0x1000: /* FRR */ 748 break; 749 case 0x1020: /* GCR */ 750 openpic_gcr_write(opp, val); 751 break; 752 case 0x1080: /* VIR */ 753 break; 754 case 0x1090: /* PIR */ 755 for (idx = 0; idx < opp->nb_cpus; idx++) { 756 if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { 757 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); 758 dst = &opp->dst[idx]; 759 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); 760 } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { 761 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); 762 dst = &opp->dst[idx]; 763 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); 764 } 765 } 766 opp->pir = val; 767 break; 768 case 0x10A0: /* IPI_IVPR */ 769 case 0x10B0: 770 case 0x10C0: 771 case 0x10D0: 772 { 773 int idx; 774 idx = (addr - 0x10A0) >> 4; 775 write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); 776 } 777 break; 778 case 0x10E0: /* SPVE */ 779 opp->spve = val & opp->vector_mask; 780 break; 781 default: 782 break; 783 } 784 } 785 786 static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) 787 { 788 OpenPICState *opp = opaque; 789 uint32_t retval; 790 791 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); 792 retval = 0xFFFFFFFF; 793 if (addr & 0xF) { 794 return retval; 795 } 796 switch (addr) { 797 case 0x1000: /* FRR */ 798 retval = opp->frr; 799 break; 800 case 0x1020: /* GCR */ 801 retval = opp->gcr; 802 break; 803 case 0x1080: /* VIR */ 804 retval = opp->vir; 805 break; 806 case 0x1090: /* PIR */ 807 retval = 0x00000000; 808 break; 809 case 0x00: /* Block Revision Register1 (BRR1) */ 810 retval = opp->brr1; 811 break; 812 case 0x40: 813 case 0x50: 814 case 0x60: 815 case 0x70: 816 case 0x80: 817 case 0x90: 818 case 0xA0: 819 case 0xB0: 820 retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); 821 break; 822 case 0x10A0: /* IPI_IVPR */ 823 case 0x10B0: 824 case 0x10C0: 825 case 0x10D0: 826 { 827 int idx; 828 idx = (addr - 0x10A0) >> 4; 829 retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx); 830 } 831 break; 832 case 0x10E0: /* SPVE */ 833 retval = opp->spve; 834 break; 835 default: 836 break; 837 } 838 DPRINTF("%s: => 0x%08x\n", __func__, retval); 839 840 return retval; 841 } 842 843 static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, 844 unsigned len) 845 { 846 OpenPICState *opp = opaque; 847 int idx; 848 849 addr += 0x10f0; 850 851 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", 852 __func__, addr, val); 853 if (addr & 0xF) { 854 return; 855 } 856 857 if (addr == 0x10f0) { 858 /* TFRR */ 859 opp->tfrr = val; 860 return; 861 } 862 863 idx = (addr >> 6) & 0x3; 864 addr = addr & 0x30; 865 866 switch (addr & 0x30) { 867 case 0x00: /* TCCR */ 868 break; 869 case 0x10: /* TBCR */ 870 if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && 871 (val & TBCR_CI) == 0 && 872 (opp->timers[idx].tbcr & TBCR_CI) != 0) { 873 opp->timers[idx].tccr &= ~TCCR_TOG; 874 } 875 opp->timers[idx].tbcr = val; 876 break; 877 case 0x20: /* TVPR */ 878 write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val); 879 break; 880 case 0x30: /* TDR */ 881 write_IRQreg_idr(opp, opp->irq_tim0 + idx, val); 882 break; 883 } 884 } 885 886 static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) 887 { 888 OpenPICState *opp = opaque; 889 uint32_t retval = -1; 890 int idx; 891 892 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); 893 if (addr & 0xF) { 894 goto out; 895 } 896 idx = (addr >> 6) & 0x3; 897 if (addr == 0x0) { 898 /* TFRR */ 899 retval = opp->tfrr; 900 goto out; 901 } 902 switch (addr & 0x30) { 903 case 0x00: /* TCCR */ 904 retval = opp->timers[idx].tccr; 905 break; 906 case 0x10: /* TBCR */ 907 retval = opp->timers[idx].tbcr; 908 break; 909 case 0x20: /* TIPV */ 910 retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); 911 break; 912 case 0x30: /* TIDE (TIDR) */ 913 retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx); 914 break; 915 } 916 917 out: 918 DPRINTF("%s: => 0x%08x\n", __func__, retval); 919 920 return retval; 921 } 922 923 static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, 924 unsigned len) 925 { 926 OpenPICState *opp = opaque; 927 int idx; 928 929 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", 930 __func__, addr, val); 931 932 addr = addr & 0xffff; 933 idx = addr >> 5; 934 935 switch (addr & 0x1f) { 936 case 0x00: 937 write_IRQreg_ivpr(opp, idx, val); 938 break; 939 case 0x10: 940 write_IRQreg_idr(opp, idx, val); 941 break; 942 case 0x18: 943 write_IRQreg_ilr(opp, idx, val); 944 break; 945 } 946 } 947 948 static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) 949 { 950 OpenPICState *opp = opaque; 951 uint32_t retval; 952 int idx; 953 954 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); 955 retval = 0xFFFFFFFF; 956 957 addr = addr & 0xffff; 958 idx = addr >> 5; 959 960 switch (addr & 0x1f) { 961 case 0x00: 962 retval = read_IRQreg_ivpr(opp, idx); 963 break; 964 case 0x10: 965 retval = read_IRQreg_idr(opp, idx); 966 break; 967 case 0x18: 968 retval = read_IRQreg_ilr(opp, idx); 969 break; 970 } 971 972 DPRINTF("%s: => 0x%08x\n", __func__, retval); 973 return retval; 974 } 975 976 static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, 977 unsigned size) 978 { 979 OpenPICState *opp = opaque; 980 int idx = opp->irq_msi; 981 int srs, ibs; 982 983 DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", 984 __func__, addr, val); 985 if (addr & 0xF) { 986 return; 987 } 988 989 switch (addr) { 990 case MSIIR_OFFSET: 991 srs = val >> MSIIR_SRS_SHIFT; 992 idx += srs; 993 ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT; 994 opp->msi[srs].msir |= 1 << ibs; 995 openpic_set_irq(opp, idx, 1); 996 break; 997 default: 998 /* most registers are read-only, thus ignored */ 999 break; 1000 } 1001 } 1002 1003 static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) 1004 { 1005 OpenPICState *opp = opaque; 1006 uint64_t r = 0; 1007 int i, srs; 1008 1009 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); 1010 if (addr & 0xF) { 1011 return -1; 1012 } 1013 1014 srs = addr >> 4; 1015 1016 switch (addr) { 1017 case 0x00: 1018 case 0x10: 1019 case 0x20: 1020 case 0x30: 1021 case 0x40: 1022 case 0x50: 1023 case 0x60: 1024 case 0x70: /* MSIRs */ 1025 r = opp->msi[srs].msir; 1026 /* Clear on read */ 1027 opp->msi[srs].msir = 0; 1028 openpic_set_irq(opp, opp->irq_msi + srs, 0); 1029 break; 1030 case 0x120: /* MSISR */ 1031 for (i = 0; i < MAX_MSI; i++) { 1032 r |= (opp->msi[i].msir ? 1 : 0) << i; 1033 } 1034 break; 1035 } 1036 1037 return r; 1038 } 1039 1040 static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size) 1041 { 1042 uint64_t r = 0; 1043 1044 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); 1045 1046 /* TODO: EISR/EIMR */ 1047 1048 return r; 1049 } 1050 1051 static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val, 1052 unsigned size) 1053 { 1054 DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", 1055 __func__, addr, val); 1056 1057 /* TODO: EISR/EIMR */ 1058 } 1059 1060 static void openpic_cpu_write_internal(void *opaque, hwaddr addr, 1061 uint32_t val, int idx) 1062 { 1063 OpenPICState *opp = opaque; 1064 IRQSource *src; 1065 IRQDest *dst; 1066 int s_IRQ, n_IRQ; 1067 1068 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx, 1069 addr, val); 1070 1071 if (idx < 0) { 1072 return; 1073 } 1074 1075 if (addr & 0xF) { 1076 return; 1077 } 1078 dst = &opp->dst[idx]; 1079 addr &= 0xFF0; 1080 switch (addr) { 1081 case 0x40: /* IPIDR */ 1082 case 0x50: 1083 case 0x60: 1084 case 0x70: 1085 idx = (addr - 0x40) >> 4; 1086 /* we use IDE as mask which CPUs to deliver the IPI to still. */ 1087 opp->src[opp->irq_ipi0 + idx].destmask |= val; 1088 openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); 1089 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); 1090 break; 1091 case 0x80: /* CTPR */ 1092 dst->ctpr = val & 0x0000000F; 1093 1094 DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", 1095 __func__, idx, dst->ctpr, dst->raised.priority, 1096 dst->servicing.priority); 1097 1098 if (dst->raised.priority <= dst->ctpr) { 1099 DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", 1100 __func__, idx); 1101 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); 1102 } else if (dst->raised.priority > dst->servicing.priority) { 1103 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n", 1104 __func__, idx, dst->raised.next); 1105 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); 1106 } 1107 1108 break; 1109 case 0x90: /* WHOAMI */ 1110 /* Read-only register */ 1111 break; 1112 case 0xA0: /* IACK */ 1113 /* Read-only register */ 1114 break; 1115 case 0xB0: /* EOI */ 1116 DPRINTF("EOI\n"); 1117 s_IRQ = IRQ_get_next(opp, &dst->servicing); 1118 1119 if (s_IRQ < 0) { 1120 DPRINTF("%s: EOI with no interrupt in service\n", __func__); 1121 break; 1122 } 1123 1124 IRQ_resetbit(&dst->servicing, s_IRQ); 1125 /* Set up next servicing IRQ */ 1126 s_IRQ = IRQ_get_next(opp, &dst->servicing); 1127 /* Check queued interrupts. */ 1128 n_IRQ = IRQ_get_next(opp, &dst->raised); 1129 src = &opp->src[n_IRQ]; 1130 if (n_IRQ != -1 && 1131 (s_IRQ == -1 || 1132 IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { 1133 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", 1134 idx, n_IRQ); 1135 qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]); 1136 } 1137 break; 1138 default: 1139 break; 1140 } 1141 } 1142 1143 static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, 1144 unsigned len) 1145 { 1146 openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); 1147 } 1148 1149 1150 static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu) 1151 { 1152 IRQSource *src; 1153 int retval, irq; 1154 1155 DPRINTF("Lower OpenPIC INT output\n"); 1156 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); 1157 1158 irq = IRQ_get_next(opp, &dst->raised); 1159 DPRINTF("IACK: irq=%d\n", irq); 1160 1161 if (irq == -1) { 1162 /* No more interrupt pending */ 1163 return opp->spve; 1164 } 1165 1166 src = &opp->src[irq]; 1167 if (!(src->ivpr & IVPR_ACTIVITY_MASK) || 1168 !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { 1169 fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", 1170 __func__, irq, dst->ctpr, src->ivpr); 1171 openpic_update_irq(opp, irq); 1172 retval = opp->spve; 1173 } else { 1174 /* IRQ enter servicing state */ 1175 IRQ_setbit(&dst->servicing, irq); 1176 retval = IVPR_VECTOR(opp, src->ivpr); 1177 } 1178 1179 if (!src->level) { 1180 /* edge-sensitive IRQ */ 1181 src->ivpr &= ~IVPR_ACTIVITY_MASK; 1182 src->pending = 0; 1183 IRQ_resetbit(&dst->raised, irq); 1184 } 1185 1186 if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + OPENPIC_MAX_IPI))) { 1187 src->destmask &= ~(1 << cpu); 1188 if (src->destmask && !src->level) { 1189 /* trigger on CPUs that didn't know about it yet */ 1190 openpic_set_irq(opp, irq, 1); 1191 openpic_set_irq(opp, irq, 0); 1192 /* if all CPUs knew about it, set active bit again */ 1193 src->ivpr |= IVPR_ACTIVITY_MASK; 1194 } 1195 } 1196 1197 return retval; 1198 } 1199 1200 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, 1201 int idx) 1202 { 1203 OpenPICState *opp = opaque; 1204 IRQDest *dst; 1205 uint32_t retval; 1206 1207 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); 1208 retval = 0xFFFFFFFF; 1209 1210 if (idx < 0) { 1211 return retval; 1212 } 1213 1214 if (addr & 0xF) { 1215 return retval; 1216 } 1217 dst = &opp->dst[idx]; 1218 addr &= 0xFF0; 1219 switch (addr) { 1220 case 0x80: /* CTPR */ 1221 retval = dst->ctpr; 1222 break; 1223 case 0x90: /* WHOAMI */ 1224 retval = idx; 1225 break; 1226 case 0xA0: /* IACK */ 1227 retval = openpic_iack(opp, dst, idx); 1228 break; 1229 case 0xB0: /* EOI */ 1230 retval = 0; 1231 break; 1232 default: 1233 break; 1234 } 1235 DPRINTF("%s: => 0x%08x\n", __func__, retval); 1236 1237 return retval; 1238 } 1239 1240 static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) 1241 { 1242 return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); 1243 } 1244 1245 static const MemoryRegionOps openpic_glb_ops_le = { 1246 .write = openpic_gbl_write, 1247 .read = openpic_gbl_read, 1248 .endianness = DEVICE_LITTLE_ENDIAN, 1249 .impl = { 1250 .min_access_size = 4, 1251 .max_access_size = 4, 1252 }, 1253 }; 1254 1255 static const MemoryRegionOps openpic_glb_ops_be = { 1256 .write = openpic_gbl_write, 1257 .read = openpic_gbl_read, 1258 .endianness = DEVICE_BIG_ENDIAN, 1259 .impl = { 1260 .min_access_size = 4, 1261 .max_access_size = 4, 1262 }, 1263 }; 1264 1265 static const MemoryRegionOps openpic_tmr_ops_le = { 1266 .write = openpic_tmr_write, 1267 .read = openpic_tmr_read, 1268 .endianness = DEVICE_LITTLE_ENDIAN, 1269 .impl = { 1270 .min_access_size = 4, 1271 .max_access_size = 4, 1272 }, 1273 }; 1274 1275 static const MemoryRegionOps openpic_tmr_ops_be = { 1276 .write = openpic_tmr_write, 1277 .read = openpic_tmr_read, 1278 .endianness = DEVICE_BIG_ENDIAN, 1279 .impl = { 1280 .min_access_size = 4, 1281 .max_access_size = 4, 1282 }, 1283 }; 1284 1285 static const MemoryRegionOps openpic_cpu_ops_le = { 1286 .write = openpic_cpu_write, 1287 .read = openpic_cpu_read, 1288 .endianness = DEVICE_LITTLE_ENDIAN, 1289 .impl = { 1290 .min_access_size = 4, 1291 .max_access_size = 4, 1292 }, 1293 }; 1294 1295 static const MemoryRegionOps openpic_cpu_ops_be = { 1296 .write = openpic_cpu_write, 1297 .read = openpic_cpu_read, 1298 .endianness = DEVICE_BIG_ENDIAN, 1299 .impl = { 1300 .min_access_size = 4, 1301 .max_access_size = 4, 1302 }, 1303 }; 1304 1305 static const MemoryRegionOps openpic_src_ops_le = { 1306 .write = openpic_src_write, 1307 .read = openpic_src_read, 1308 .endianness = DEVICE_LITTLE_ENDIAN, 1309 .impl = { 1310 .min_access_size = 4, 1311 .max_access_size = 4, 1312 }, 1313 }; 1314 1315 static const MemoryRegionOps openpic_src_ops_be = { 1316 .write = openpic_src_write, 1317 .read = openpic_src_read, 1318 .endianness = DEVICE_BIG_ENDIAN, 1319 .impl = { 1320 .min_access_size = 4, 1321 .max_access_size = 4, 1322 }, 1323 }; 1324 1325 static const MemoryRegionOps openpic_msi_ops_be = { 1326 .read = openpic_msi_read, 1327 .write = openpic_msi_write, 1328 .endianness = DEVICE_BIG_ENDIAN, 1329 .impl = { 1330 .min_access_size = 4, 1331 .max_access_size = 4, 1332 }, 1333 }; 1334 1335 static const MemoryRegionOps openpic_summary_ops_be = { 1336 .read = openpic_summary_read, 1337 .write = openpic_summary_write, 1338 .endianness = DEVICE_BIG_ENDIAN, 1339 .impl = { 1340 .min_access_size = 4, 1341 .max_access_size = 4, 1342 }, 1343 }; 1344 1345 static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q) 1346 { 1347 unsigned int i; 1348 1349 for (i = 0; i < ARRAY_SIZE(q->queue); i++) { 1350 /* Always put the lower half of a 64-bit long first, in case we 1351 * restore on a 32-bit host. The least significant bits correspond 1352 * to lower IRQ numbers in the bitmap. 1353 */ 1354 qemu_put_be32(f, (uint32_t)q->queue[i]); 1355 #if LONG_MAX > 0x7FFFFFFF 1356 qemu_put_be32(f, (uint32_t)(q->queue[i] >> 32)); 1357 #endif 1358 } 1359 1360 qemu_put_sbe32s(f, &q->next); 1361 qemu_put_sbe32s(f, &q->priority); 1362 } 1363 1364 static void openpic_save(QEMUFile* f, void *opaque) 1365 { 1366 OpenPICState *opp = (OpenPICState *)opaque; 1367 unsigned int i; 1368 1369 qemu_put_be32s(f, &opp->gcr); 1370 qemu_put_be32s(f, &opp->vir); 1371 qemu_put_be32s(f, &opp->pir); 1372 qemu_put_be32s(f, &opp->spve); 1373 qemu_put_be32s(f, &opp->tfrr); 1374 1375 qemu_put_be32s(f, &opp->nb_cpus); 1376 1377 for (i = 0; i < opp->nb_cpus; i++) { 1378 qemu_put_sbe32s(f, &opp->dst[i].ctpr); 1379 openpic_save_IRQ_queue(f, &opp->dst[i].raised); 1380 openpic_save_IRQ_queue(f, &opp->dst[i].servicing); 1381 qemu_put_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, 1382 sizeof(opp->dst[i].outputs_active)); 1383 } 1384 1385 for (i = 0; i < OPENPIC_MAX_TMR; i++) { 1386 qemu_put_be32s(f, &opp->timers[i].tccr); 1387 qemu_put_be32s(f, &opp->timers[i].tbcr); 1388 } 1389 1390 for (i = 0; i < opp->max_irq; i++) { 1391 qemu_put_be32s(f, &opp->src[i].ivpr); 1392 qemu_put_be32s(f, &opp->src[i].idr); 1393 qemu_get_be32s(f, &opp->src[i].destmask); 1394 qemu_put_sbe32s(f, &opp->src[i].last_cpu); 1395 qemu_put_sbe32s(f, &opp->src[i].pending); 1396 } 1397 } 1398 1399 static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q) 1400 { 1401 unsigned int i; 1402 1403 for (i = 0; i < ARRAY_SIZE(q->queue); i++) { 1404 unsigned long val; 1405 1406 val = qemu_get_be32(f); 1407 #if LONG_MAX > 0x7FFFFFFF 1408 val <<= 32; 1409 val |= qemu_get_be32(f); 1410 #endif 1411 1412 q->queue[i] = val; 1413 } 1414 1415 qemu_get_sbe32s(f, &q->next); 1416 qemu_get_sbe32s(f, &q->priority); 1417 } 1418 1419 static int openpic_load(QEMUFile* f, void *opaque, int version_id) 1420 { 1421 OpenPICState *opp = (OpenPICState *)opaque; 1422 unsigned int i; 1423 1424 if (version_id != 1) { 1425 return -EINVAL; 1426 } 1427 1428 qemu_get_be32s(f, &opp->gcr); 1429 qemu_get_be32s(f, &opp->vir); 1430 qemu_get_be32s(f, &opp->pir); 1431 qemu_get_be32s(f, &opp->spve); 1432 qemu_get_be32s(f, &opp->tfrr); 1433 1434 qemu_get_be32s(f, &opp->nb_cpus); 1435 1436 for (i = 0; i < opp->nb_cpus; i++) { 1437 qemu_get_sbe32s(f, &opp->dst[i].ctpr); 1438 openpic_load_IRQ_queue(f, &opp->dst[i].raised); 1439 openpic_load_IRQ_queue(f, &opp->dst[i].servicing); 1440 qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, 1441 sizeof(opp->dst[i].outputs_active)); 1442 } 1443 1444 for (i = 0; i < OPENPIC_MAX_TMR; i++) { 1445 qemu_get_be32s(f, &opp->timers[i].tccr); 1446 qemu_get_be32s(f, &opp->timers[i].tbcr); 1447 } 1448 1449 for (i = 0; i < opp->max_irq; i++) { 1450 uint32_t val; 1451 1452 val = qemu_get_be32(f); 1453 write_IRQreg_idr(opp, i, val); 1454 val = qemu_get_be32(f); 1455 write_IRQreg_ivpr(opp, i, val); 1456 1457 qemu_get_be32s(f, &opp->src[i].ivpr); 1458 qemu_get_be32s(f, &opp->src[i].idr); 1459 qemu_get_be32s(f, &opp->src[i].destmask); 1460 qemu_get_sbe32s(f, &opp->src[i].last_cpu); 1461 qemu_get_sbe32s(f, &opp->src[i].pending); 1462 } 1463 1464 return 0; 1465 } 1466 1467 typedef struct MemReg { 1468 const char *name; 1469 MemoryRegionOps const *ops; 1470 hwaddr start_addr; 1471 ram_addr_t size; 1472 } MemReg; 1473 1474 static void fsl_common_init(OpenPICState *opp) 1475 { 1476 int i; 1477 int virq = OPENPIC_MAX_SRC; 1478 1479 opp->vid = VID_REVISION_1_2; 1480 opp->vir = VIR_GENERIC; 1481 opp->vector_mask = 0xFFFF; 1482 opp->tfrr_reset = 0; 1483 opp->ivpr_reset = IVPR_MASK_MASK; 1484 opp->idr_reset = 1 << 0; 1485 opp->max_irq = OPENPIC_MAX_IRQ; 1486 1487 opp->irq_ipi0 = virq; 1488 virq += OPENPIC_MAX_IPI; 1489 opp->irq_tim0 = virq; 1490 virq += OPENPIC_MAX_TMR; 1491 1492 assert(virq <= OPENPIC_MAX_IRQ); 1493 1494 opp->irq_msi = 224; 1495 1496 msi_supported = true; 1497 for (i = 0; i < opp->fsl->max_ext; i++) { 1498 opp->src[i].level = false; 1499 } 1500 1501 /* Internal interrupts, including message and MSI */ 1502 for (i = 16; i < OPENPIC_MAX_SRC; i++) { 1503 opp->src[i].type = IRQ_TYPE_FSLINT; 1504 opp->src[i].level = true; 1505 } 1506 1507 /* timers and IPIs */ 1508 for (i = OPENPIC_MAX_SRC; i < virq; i++) { 1509 opp->src[i].type = IRQ_TYPE_FSLSPECIAL; 1510 opp->src[i].level = false; 1511 } 1512 } 1513 1514 static void map_list(OpenPICState *opp, const MemReg *list, int *count) 1515 { 1516 while (list->name) { 1517 assert(*count < ARRAY_SIZE(opp->sub_io_mem)); 1518 1519 memory_region_init_io(&opp->sub_io_mem[*count], OBJECT(opp), list->ops, 1520 opp, list->name, list->size); 1521 1522 memory_region_add_subregion(&opp->mem, list->start_addr, 1523 &opp->sub_io_mem[*count]); 1524 1525 (*count)++; 1526 list++; 1527 } 1528 } 1529 1530 static void openpic_init(Object *obj) 1531 { 1532 OpenPICState *opp = OPENPIC(obj); 1533 1534 memory_region_init(&opp->mem, obj, "openpic", 0x40000); 1535 } 1536 1537 static void openpic_realize(DeviceState *dev, Error **errp) 1538 { 1539 SysBusDevice *d = SYS_BUS_DEVICE(dev); 1540 OpenPICState *opp = OPENPIC(dev); 1541 int i, j; 1542 int list_count = 0; 1543 static const MemReg list_le[] = { 1544 {"glb", &openpic_glb_ops_le, 1545 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, 1546 {"tmr", &openpic_tmr_ops_le, 1547 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, 1548 {"src", &openpic_src_ops_le, 1549 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, 1550 {"cpu", &openpic_cpu_ops_le, 1551 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, 1552 {NULL} 1553 }; 1554 static const MemReg list_be[] = { 1555 {"glb", &openpic_glb_ops_be, 1556 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, 1557 {"tmr", &openpic_tmr_ops_be, 1558 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, 1559 {"src", &openpic_src_ops_be, 1560 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, 1561 {"cpu", &openpic_cpu_ops_be, 1562 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, 1563 {NULL} 1564 }; 1565 static const MemReg list_fsl[] = { 1566 {"msi", &openpic_msi_ops_be, 1567 OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, 1568 {"summary", &openpic_summary_ops_be, 1569 OPENPIC_SUMMARY_REG_START, OPENPIC_SUMMARY_REG_SIZE}, 1570 {NULL} 1571 }; 1572 1573 switch (opp->model) { 1574 case OPENPIC_MODEL_FSL_MPIC_20: 1575 default: 1576 opp->fsl = &fsl_mpic_20; 1577 opp->brr1 = 0x00400200; 1578 opp->flags |= OPENPIC_FLAG_IDR_CRIT; 1579 opp->nb_irqs = 80; 1580 opp->mpic_mode_mask = GCR_MODE_MIXED; 1581 1582 fsl_common_init(opp); 1583 map_list(opp, list_be, &list_count); 1584 map_list(opp, list_fsl, &list_count); 1585 1586 break; 1587 1588 case OPENPIC_MODEL_FSL_MPIC_42: 1589 opp->fsl = &fsl_mpic_42; 1590 opp->brr1 = 0x00400402; 1591 opp->flags |= OPENPIC_FLAG_ILR; 1592 opp->nb_irqs = 196; 1593 opp->mpic_mode_mask = GCR_MODE_PROXY; 1594 1595 fsl_common_init(opp); 1596 map_list(opp, list_be, &list_count); 1597 map_list(opp, list_fsl, &list_count); 1598 1599 break; 1600 1601 case OPENPIC_MODEL_RAVEN: 1602 opp->nb_irqs = RAVEN_MAX_EXT; 1603 opp->vid = VID_REVISION_1_3; 1604 opp->vir = VIR_GENERIC; 1605 opp->vector_mask = 0xFF; 1606 opp->tfrr_reset = 4160000; 1607 opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK; 1608 opp->idr_reset = 0; 1609 opp->max_irq = RAVEN_MAX_IRQ; 1610 opp->irq_ipi0 = RAVEN_IPI_IRQ; 1611 opp->irq_tim0 = RAVEN_TMR_IRQ; 1612 opp->brr1 = -1; 1613 opp->mpic_mode_mask = GCR_MODE_MIXED; 1614 1615 if (opp->nb_cpus != 1) { 1616 error_setg(errp, "Only UP supported today"); 1617 return; 1618 } 1619 1620 map_list(opp, list_le, &list_count); 1621 break; 1622 } 1623 1624 for (i = 0; i < opp->nb_cpus; i++) { 1625 opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB); 1626 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 1627 sysbus_init_irq(d, &opp->dst[i].irqs[j]); 1628 } 1629 } 1630 1631 register_savevm(dev, "openpic", 0, 2, 1632 openpic_save, openpic_load, opp); 1633 1634 sysbus_init_mmio(d, &opp->mem); 1635 qdev_init_gpio_in(dev, openpic_set_irq, opp->max_irq); 1636 } 1637 1638 static Property openpic_properties[] = { 1639 DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20), 1640 DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1), 1641 DEFINE_PROP_END_OF_LIST(), 1642 }; 1643 1644 static void openpic_class_init(ObjectClass *oc, void *data) 1645 { 1646 DeviceClass *dc = DEVICE_CLASS(oc); 1647 1648 dc->realize = openpic_realize; 1649 dc->props = openpic_properties; 1650 dc->reset = openpic_reset; 1651 } 1652 1653 static const TypeInfo openpic_info = { 1654 .name = TYPE_OPENPIC, 1655 .parent = TYPE_SYS_BUS_DEVICE, 1656 .instance_size = sizeof(OpenPICState), 1657 .instance_init = openpic_init, 1658 .class_init = openpic_class_init, 1659 }; 1660 1661 static void openpic_register_types(void) 1662 { 1663 type_register_static(&openpic_info); 1664 } 1665 1666 type_init(openpic_register_types) 1667