| be4f9829 | 25-Oct-2024 |
Cédric Le Goater <clg@redhat.com> |
aspeed: Create sd devices only when defaults are enabled
When the -nodefaults option is set, sd devices should be created
with :
-blockdev node-name=fmc0,driver=file,filename=./flash.img \
-dev
aspeed: Create sd devices only when defaults are enabled
When the -nodefaults option is set, sd devices should be created
with :
-blockdev node-name=fmc0,driver=file,filename=./flash.img \
-device mx66u51235f,cs=0x0,bus=ssi.0,drive=fmc0 \
To be noted that in this case, the ROM will not be installed and the
initial boot sequence (U-Boot loading) will fetch instructions using
SPI transactions which is significantly slower. That's exactly how HW
operates though.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
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| ec40012a | 25-Oct-2024 |
Cédric Le Goater <clg@redhat.com> |
aspeed: Avoid referencing "sd-bus"
Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| ce158aa5 | 30-Mar-2023 |
Joe Komlodi <komlodi@google.com> |
qtest: remote_i3c: Add remote I3C qtest
This adds a remote I3C qtest using the Aspeed I3C controller and an
AST2600 board.
The qtest uses a basic Aspeed I3C driver to test:
- data transmission from
qtest: remote_i3c: Add remote I3C qtest
This adds a remote I3C qtest using the Aspeed I3C controller and an
AST2600 board.
The qtest uses a basic Aspeed I3C driver to test:
- data transmission from controller to target
- data reception from target to controller
- target sending an IBI (with data bytes) to controller
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
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| 084e81f3 | 30-Mar-2023 |
Joe Komlodi <komlodi@google.com> |
hw/misc/aspeed_i3c: Move to i3c directory
Moves the Aspeed I3C model and traces into hw/i3c and create I3C build
files.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture
hw/misc/aspeed_i3c: Move to i3c directory
Moves the Aspeed I3C model and traces into hw/i3c and create I3C build
files.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
[ clg: - replaced softmmu_ss with system_ss in meson.build files
- local variable renames in aspeed_i3c_realize() ]
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| 7ad20085 | 03-Apr-2019 |
Cédric Le Goater <clg@kaod.org> |
i2c: Add a ir35221 device
Simple model of a PSU device of the witherspoon.
TODO:
- generate "real" values
- implement property visitors to generate faults.
Signed-off-by: Cédric Le Goater <c
i2c: Add a ir35221 device
Simple model of a PSU device of the witherspoon.
TODO:
- generate "real" values
- implement property visitors to generate faults.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| 6d0d0110 | 02-Apr-2019 |
Cédric Le Goater <clg@kaod.org> |
i2c: Add a IBM CFF Power Supply device
Simple model of a PSU device of the witherspoon.
TODO:
- generate "real" values
- implement property visitors to generate faults.
Signed-off-by: Cédric
i2c: Add a IBM CFF Power Supply device
Simple model of a PSU device of the witherspoon.
TODO:
- generate "real" values
- implement property visitors to generate faults.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| 3b24d12a | 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Controller (RC)
1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller
6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| 7a40ad4f | 07-Apr-2021 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual mac
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual machines described in :
https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
and implemented by the 'ipmi-bmc-extern' model on the host side.
To use, start the Aspeed BMC machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \
-global driver=aspeed.ibt,property=chardev,value=ipmi0
and the PowerNV machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \
-device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \
-device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults
Cc: Hao Wu <wuhaotsh@google.com>
Cc: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| bbe07828 | 27-Nov-2017 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add basic Aspeed PWM model
Just enough to quiet down the output when running with the logs.
Signed-off-by: Cédric Le Goater <clg@kaod.org> |
| 41d5c01f | 19-Jan-2023 |
Joel Stanley <joel@jms.id.au> |
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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| 6c2caa04 | 18-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only im
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only implements the enable bit of the control register. The
reload register uses a 0.1s unit instead of a 1us. Values are
converted on the fly when doing the accesses. The restart register is
the same.
TODO: This needs a rework since the FMC WDT2 device is an independent
watchdog logic embedded in the FMC device.
Cc: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| a8b088e6 | 18-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed: Initialize the watchdog device models before the FMC models
Next changes will map the WDT2 registers in the AST2600 FMC memory
region. Make sure the MemoryRegion pointers are correctly initi
aspeed: Initialize the watchdog device models before the FMC models
Next changes will map the WDT2 registers in the AST2600 FMC memory
region. Make sure the MemoryRegion pointers are correctly initialized
before setting the object links.
Do the same in the Aspeed AST2400 and AST2500 SoC models for
consistency.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
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| 4786f38f | 12-Nov-2024 |
Guenter Roeck <linux@roeck-us.net> |
aspeed: Add uhci support for ast2400 and ast2500
Add UHCI support for ast2400 and ast2500 SoCs. With this patch,
the UHCI port is successfully enabled on the ast2500-evb machine.
Note that the EHCI
aspeed: Add uhci support for ast2400 and ast2500
Add UHCI support for ast2400 and ast2500 SoCs. With this patch,
the UHCI port is successfully enabled on the ast2500-evb machine.
Note that the EHCI controller on AST2400 and AST2500 does not support
companion mode, so the UHCI controller is instantiated as stand-alone
device and creates an additional USB bus.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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| c7259b34 | 12-Nov-2024 |
Guenter Roeck <linux@roeck-us.net> |
aspeed: Add uhci support for ast2600
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter
aspeed: Add uhci support for ast2600
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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| 9795bd5c | 12-Nov-2024 |
Guenter Roeck <linux@roeck-us.net> |
usb/uhci: Add support for usb-uhci-sysbus
Signed-off-by: Guenter Roeck <linux@roeck-us.net> |
| 3c4fb143 | 14-Nov-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24).
According to the design of AST2600 EVB, the Write Protected pin is active
high by default. To support it, introduces a new "sdhci_wp_inverted"
property in ASPEED MACHINE State and set it true for AST2600 EVB
and set "wp_inverted" property true of sdhci-generic model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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| 7d61c46e | 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
aspeed/soc: Support eMMC for AST2700
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_0000 and its interrupt is
connect
aspeed/soc: Support eMMC for AST2700
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_0000 and its interrupt is
connected to GICINT 15.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
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|
| f2879f95 | 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
aspeed/soc: Support SDHCI for AST2700
Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
slot and registers base address is start at 0x1408_0000 and its interrupt is
conn
aspeed/soc: Support SDHCI for AST2700
Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
slot and registers base address is start at 0x1408_0000 and its interrupt is
connected to GICINT133_INTC at bit 1.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
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| 1f1a9ff0 | 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capab
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg" class member whose data type is uint_64 to set the
different Capability Registers to all ASPEED SOCs.
The value of Capability Register is "0x0000000001e80080" for AST2400 and
AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
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| a2cf3511 | 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/arm/aspeed: Fix coding style
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| c0c557c8 | 13-Nov-2024 |
Cédric Le Goater <clg@redhat.com> |
arm: Remove tacoma-bmc machine
Removal was scheduled for 10.0. Use the rainier-bmc machine or the
ast2600-evb as a replacement.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by
arm: Remove tacoma-bmc machine
Removal was scheduled for 10.0. Use the rainier-bmc machine or the
ast2600-evb as a replacement.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
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| 3c84a63e | 07-Mar-2025 |
Alex Bennée <alex.bennee@linaro.org> |
hw/arm: enable secure EL2 timers for sbsa machine
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydel
hw/arm: enable secure EL2 timers for sbsa machine
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-10-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 9a9d9e82093efa22e3e2bdaac0f24c823f8786f7)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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| 472a4207 | 07-Mar-2025 |
Alex Bennée <alex.bennee@linaro.org> |
hw/arm: enable secure EL2 timers for virt machine
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydel
hw/arm: enable secure EL2 timers for virt machine
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-9-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 5dcaea8bcd82972add29eef350547f922fb4caa2)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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| 437999ae | 09-Feb-2025 |
Bernhard Beschow <shentey@gmail.com> |
Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_S
Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix that by extracting CONFIG_USB_CHIPIDEA from CONFIG_IMX.
cc: qemu-stable@nongnu.org
Fixes: 616ec12d0fcc "hw/arm/xilinx_zynq: Fix USB port instantiation"
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250209103604.29545-1-shentey@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 464ce71a963b3dfc290cd59c3d1bfedf11c004df)
(Mjt: context fixup due to missing
v9.2.0-1303-g1b326f278d05 "hw/pci-host/designware: Expose MSI IRQ")
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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| 9eb9350c | 05-Nov-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, fixes, cleanups
CXL now can use Generic Port Affinity Structures.
CXL now allows c
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, fixes, cleanups
CXL now can use Generic Port Affinity Structures.
CXL now allows control of link speed and width
vhost-user-blk now supports live resize, by means of
a new device-sync-config command
amd iommu now supports interrupt remapping
pcie devices now report extended tag field support
intel_iommu dropped support for Transient Mapping, to match VTD spec
arch agnostic ACPI infrastructure for vCPU Hotplug
Fixes, cleanups all over the place.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# =zSX4
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 04 Nov 2024 21:03:33 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (65 commits)
intel_iommu: Add missed reserved bit check for IEC descriptor
intel_iommu: Add missed sanity check for 256-bit invalidation queue
intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL
hw/acpi: Update GED with vCPU Hotplug VMSD for migration
tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc,q35}
hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states
qtest: allow ACPI DSDT Table changes
hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug
hw/pci: Add parenthesis to PCI_BUILD_BDF macro
hw/cxl: Ensure there is enough data to read the input header in cmd_get_physical_port_state()
hw/cxl: Ensure there is enough data for the header in cmd_ccls_set_lsa()
hw/cxl: Check that writes do not go beyond end of target attributes
hw/cxl: Ensuring enough data to read parameters in cmd_tunnel_management_cmd()
hw/cxl: Avoid accesses beyond the end of cel_log.
hw/cxl: Check the length of data requested fits in get_log()
hw/cxl: Check enough data in cmd_firmware_update_transfer()
hw/cxl: Check input length is large enough in cmd_events_clear_records()
hw/cxl: Check input includes at least the header in cmd_features_set_feature()
hw/cxl: Check size of input data to dynamic capacity mailbox commands
hw/cxl/cxl-mailbox-util: Fix output buffer index update when retrieving DC extents
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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