arm64: dts: ti: k3-*: fix fss node dtbs check warnings

Fix these fss node warnings that dtbs_check throws:

fss@47000000: $nodename:0: 'fss@47000000' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|loca

arm64: dts: ti: k3-*: fix fss node dtbs check warnings

Fix these fss node warnings that dtbs_check throws:

fss@47000000: $nodename:0: 'fss@47000000' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$'

By renaming fss to bus.

Cc: Nishant Menon <nm@ti.com>
Suggested-by: Andrew Davis <afd@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Reid Tonking <reidt@ti.com>
Link: https://lore.kernel.org/r/20230810081847.277094-1-d-gole@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level

TSCADC nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pin

arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level

TSCADC nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and/or
device information.

Disable the TSCADC nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-12-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721e: Enable GPIO nodes at the board level

GPIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux

arm64: dts: ti: k3-j721e: Enable GPIO nodes at the board level

GPIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.

Disable the GPIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-9-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level

OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux

arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level

OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.

As the attached OSPI device is only known about at the board integration
level, these nodes should only be enabled when provided with this
information.

Disable the OSPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-6-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3: Add cfg reg region to ringacc node

Add register range of ringacc cfg node to all k3 SoC dtsi files. This is
normally under Device Management firmware control but some entities li

arm64: dts: ti: k3: Add cfg reg region to ringacc node

Add register range of ringacc cfg node to all k3 SoC dtsi files. This is
normally under Device Management firmware control but some entities like
bootloader have to access directly and thus required to be present in DT.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230809175932.2553156-3-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org

arm64: dts: ti: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

There are timer IO contro

arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.

The multiplexing is documented in Technical Reference Manual[1] under
"Timer IO Muxing Control Registers" and "Timer IO Muxing Control
Registers", and the "Timers Overview" chapters.

We do not expose the cascade_en bit due to the racy usage of
independent 32 bit registers in-line with the timer instantiation in
the device tree. The MCU timer controls are also marked as reserved for
usage by the MCU firmware.

[1] http://www.ti.com/lit/pdf/spruil1

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721e: Add general purpose timers

There are 20 general purpose timers on j721e that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten ti

arm64: dts: ti: k3-j721e: Add general purpose timers

There are 20 general purpose timers on j721e that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.

The odd numbered timers have the option of being cascaded to even
timers to create a 64 bit non-atomic counter which is racy in simple
usage, hence the clock muxes are explicitly setup to individual 32 bit
counters driven off system crystal (HFOSC) as default.

These instantiation differs from J7200 and other SoCs with the device
IDs and clocks involved for muxing.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721e-mcu: Add mcu_secproxy

MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the

arm64: dts: ti: k3-j721e-mcu: Add mcu_secproxy

MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the main domain NAVSS subsystem that is used for general
purpose communication.

Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node

J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
cont

arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node

J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
controller and keep it disabled and model the data path selection mux as a
reg-mux.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: j721e: Add VTM node

VTM stands for Voltage Thermal Management. Add the thermal zones.
Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F
respectively.

Signed-off-by

arm64: dts: ti: j721e: Add VTM node

VTM stands for Voltage Thermal Management. Add the thermal zones.
Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F
respectively.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[bb@ti.com: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-6-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721e: Add MCSPI nodes

J721E has 8 MCSPI instances in the main domain and 3 instances
in the MCU domain. Add the DT nodes for all the 11 instances and
keep them disabled. MAIN_MCS

arm64: dts: ti: k3-j721e: Add MCSPI nodes

J721E has 8 MCSPI instances in the main domain and 3 instances
in the MCU domain. Add the DT nodes for all the 11 instances and
keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2
by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out
externally.

Co-developed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Link: https://lore.kernel.org/r/20230321082827.14274-2-vaishnav.a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: Rename clock-names adc_tsc_fck to fck

Avoid the following warnings from dt-schema by just renaming the
clock-names string from adc_tsc_fck to fck so it matches the values in
ti,am335

arm64: dts: ti: Rename clock-names adc_tsc_fck to fck

Avoid the following warnings from dt-schema by just renaming the
clock-names string from adc_tsc_fck to fck so it matches the values in
ti,am3359-tscadc.yaml

tscadc@40200000: clock-names:0: 'fck' was expected

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Judith Mendez <jm@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20221024151648.394623-1-mranostay@ti.com

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arm64: dts: ti: k3-j721e: Enable MCAN nodes at the board level

MCAN nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux

arm64: dts: ti: k3-j721e: Enable MCAN nodes at the board level

MCAN nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the MCAN nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221020160305.18711-5-afd@ti.com

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arm64: dts: ti: k3-j721e: Enable I2C nodes at the board level

I2C nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
i

arm64: dts: ti: k3-j721e: Enable I2C nodes at the board level

I2C nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the I2C nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221020160305.18711-3-afd@ti.com

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arm64: dts: ti: k3-j721e: Enable UART nodes at the board level

UART nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux

arm64: dts: ti: k3-j721e: Enable UART nodes at the board level

UART nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the UART nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221020160305.18711-2-afd@ti.com

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arm64: dts: ti: Adjust whitespace around '='

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB

arm64: dts: ti: Adjust whitespace around '='

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org

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arm64: dts: ti: k3-j721e: Add support for MCAN nodes

Add support for 14 MCAN controllers in main domain and 2 MCAN controllers
present in mcu domain. All the MCAN controllers support classic CAN
mes

arm64: dts: ti: k3-j721e: Add support for MCAN nodes

Add support for 14 MCAN controllers in main domain and 2 MCAN controllers
present in mcu domain. All the MCAN controllers support classic CAN
messages as well as CAN_FD messages.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20211122134159.29936-4-a-govindraju@ti.com

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arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes

8250_omap compatible UART IPs on all SoCs have registers aligned at 4
byte address boundary and constant byte addressability. Thus there i

arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes

8250_omap compatible UART IPs on all SoCs have registers aligned at 4
byte address boundary and constant byte addressability. Thus there is no
need for reg-io-width or reg-shift DT properties. These properties are
not used by 8250_omap driver nor documented as part of binding document.
Therefore drop them.

This is in preparation to move omap-serial.txt to YAML format.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com

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arm64: dts: ti: k3*: Introduce reg definition for interrupt routers

Interrupt routers are memory mapped peripherals, that are organized
in our dts bus hierarchy to closely represents the actual hard

arm64: dts: ti: k3*: Introduce reg definition for interrupt routers

Interrupt routers are memory mapped peripherals, that are organized
in our dts bus hierarchy to closely represents the actual hardware
behavior.

However, without explicitly calling out the reg property, using
2021.03+ dt-schema package, this exposes the following problem with
dtbs_check:

/arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000:
interrupt-controller0: {'type': 'object'} is not allowed for
{'compatible': ['ti,sci-intr'], .....

Even though we don't use interrupt router directly via memory mapped
registers and have to use it via the system controller, the hardware
block is memory mapped, so describe the base address in device tree.

This is a valid, comprehensive description of hardware and permitted
by the existing ti,sci-intr schema.

Reviewed-by: Tero Kristo <kristo@kernel.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210511194821.13919-1-nm@ti.com

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arm64: dts: ti: k3-am65|j721e|am64: Map the dma / navigator subsystem via explicit ranges

Instead of using empty ranges property, lets map explicitly the address
range that is mapped onto the dma /

arm64: dts: ti: k3-am65|j721e|am64: Map the dma / navigator subsystem via explicit ranges

Instead of using empty ranges property, lets map explicitly the address
range that is mapped onto the dma / navigator subsystems (navss/dmss).

This is also exposed via the dtbs_check with dt-schema newer than
2021.03 version by throwing out following:
arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000: main-navss:
{'type': 'object'} is not allowed for
{'compatible': ['simple-mfd'], '#address-cells': [[2]], .....

This has already been correctly done for J7200, however was missed for
other k3 SoCs. Fix that oversight.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210510145429.8752-1-nm@ti.com

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arm64: dts: ti: k3-*: Rename the TI-SCI node

Lets rename the node name of TI-SCI node to be system-controller as it
is a better standardized name for the function that TI-SCI plays in the
SoC.

Sign

arm64: dts: ti: k3-*: Rename the TI-SCI node

Lets rename the node name of TI-SCI node to be system-controller as it
is a better standardized name for the function that TI-SCI plays in the
SoC.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210510145033.7426-5-nm@ti.com

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arm64: dts: ti: k3-*: Rename the TI-SCI clocks node name

We currently use clocks as the node name for the node representing
TI-SCI clock nodes. This is better renamed to being clock-controller
as th

arm64: dts: ti: k3-*: Rename the TI-SCI clocks node name

We currently use clocks as the node name for the node representing
TI-SCI clock nodes. This is better renamed to being clock-controller
as that is a better representative of the system controller function
as a clock controller for the SoC.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210510145033.7426-2-nm@ti.com

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arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible

The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by

arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible

The TI specific compatible should be followed by the generic
"cdns,qspi-nor" compatible.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210326130034.15231-2-p.yadav@ti.com

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arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node

The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the

arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node

The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes)
MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode)

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20201029033802.15366-6-s-anna@ti.com

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