1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x0 0x40f00000 0x0 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x0 0x43000014 0x0 0x4>; 54 }; 55 56 wkup_pmx0: pinctrl@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x178>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 66 mcu_timerio_input: pinctrl@40f04200 { 67 compatible = "pinctrl-single"; 68 reg = <0x00 0x40f04200 0x00 0x28>; 69 #pinctrl-cells = <1>; 70 pinctrl-single,register-width = <32>; 71 pinctrl-single,function-mask = <0x0000000f>; 72 /* Non-MPU Firmware usage */ 73 status = "reserved"; 74 }; 75 76 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 77 mcu_timerio_output: pinctrl@40f04280 { 78 compatible = "pinctrl-single"; 79 reg = <0x00 0x40f04280 0x00 0x28>; 80 #pinctrl-cells = <1>; 81 pinctrl-single,register-width = <32>; 82 pinctrl-single,function-mask = <0x0000000f>; 83 /* Non-MPU Firmware usage */ 84 status = "reserved"; 85 }; 86 87 mcu_ram: sram@41c00000 { 88 compatible = "mmio-sram"; 89 reg = <0x00 0x41c00000 0x00 0x100000>; 90 ranges = <0x0 0x00 0x41c00000 0x100000>; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 }; 94 95 mcu_timer0: timer@40400000 { 96 compatible = "ti,am654-timer"; 97 reg = <0x00 0x40400000 0x00 0x400>; 98 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&k3_clks 35 1>; 100 clock-names = "fck"; 101 assigned-clocks = <&k3_clks 35 1>; 102 assigned-clock-parents = <&k3_clks 35 2>; 103 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 104 ti,timer-pwm; 105 /* Non-MPU Firmware usage */ 106 status = "reserved"; 107 }; 108 109 mcu_timer1: timer@40410000 { 110 compatible = "ti,am654-timer"; 111 reg = <0x00 0x40410000 0x00 0x400>; 112 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&k3_clks 71 1>; 114 clock-names = "fck"; 115 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; 116 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; 117 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 118 ti,timer-pwm; 119 /* Non-MPU Firmware usage */ 120 status = "reserved"; 121 }; 122 123 mcu_timer2: timer@40420000 { 124 compatible = "ti,am654-timer"; 125 reg = <0x00 0x40420000 0x00 0x400>; 126 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&k3_clks 72 1>; 128 clock-names = "fck"; 129 assigned-clocks = <&k3_clks 72 1>; 130 assigned-clock-parents = <&k3_clks 72 2>; 131 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 132 ti,timer-pwm; 133 /* Non-MPU Firmware usage */ 134 status = "reserved"; 135 }; 136 137 mcu_timer3: timer@40430000 { 138 compatible = "ti,am654-timer"; 139 reg = <0x00 0x40430000 0x00 0x400>; 140 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&k3_clks 73 1>; 142 clock-names = "fck"; 143 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; 144 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; 145 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 146 ti,timer-pwm; 147 /* Non-MPU Firmware usage */ 148 status = "reserved"; 149 }; 150 151 mcu_timer4: timer@40440000 { 152 compatible = "ti,am654-timer"; 153 reg = <0x00 0x40440000 0x00 0x400>; 154 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&k3_clks 74 1>; 156 clock-names = "fck"; 157 assigned-clocks = <&k3_clks 74 1>; 158 assigned-clock-parents = <&k3_clks 74 2>; 159 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 160 ti,timer-pwm; 161 /* Non-MPU Firmware usage */ 162 status = "reserved"; 163 }; 164 165 mcu_timer5: timer@40450000 { 166 compatible = "ti,am654-timer"; 167 reg = <0x00 0x40450000 0x00 0x400>; 168 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&k3_clks 75 1>; 170 clock-names = "fck"; 171 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; 172 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; 173 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 174 ti,timer-pwm; 175 /* Non-MPU Firmware usage */ 176 status = "reserved"; 177 }; 178 179 mcu_timer6: timer@40460000 { 180 compatible = "ti,am654-timer"; 181 reg = <0x00 0x40460000 0x00 0x400>; 182 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&k3_clks 76 1>; 184 clock-names = "fck"; 185 assigned-clocks = <&k3_clks 76 1>; 186 assigned-clock-parents = <&k3_clks 76 2>; 187 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 188 ti,timer-pwm; 189 /* Non-MPU Firmware usage */ 190 status = "reserved"; 191 }; 192 193 mcu_timer7: timer@40470000 { 194 compatible = "ti,am654-timer"; 195 reg = <0x00 0x40470000 0x00 0x400>; 196 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&k3_clks 77 1>; 198 clock-names = "fck"; 199 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; 200 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; 201 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 202 ti,timer-pwm; 203 /* Non-MPU Firmware usage */ 204 status = "reserved"; 205 }; 206 207 mcu_timer8: timer@40480000 { 208 compatible = "ti,am654-timer"; 209 reg = <0x00 0x40480000 0x00 0x400>; 210 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&k3_clks 78 1>; 212 clock-names = "fck"; 213 assigned-clocks = <&k3_clks 78 1>; 214 assigned-clock-parents = <&k3_clks 78 2>; 215 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 216 ti,timer-pwm; 217 /* Non-MPU Firmware usage */ 218 status = "reserved"; 219 }; 220 221 mcu_timer9: timer@40490000 { 222 compatible = "ti,am654-timer"; 223 reg = <0x00 0x40490000 0x00 0x400>; 224 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&k3_clks 79 1>; 226 clock-names = "fck"; 227 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; 228 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; 229 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 230 ti,timer-pwm; 231 /* Non-MPU Firmware usage */ 232 status = "reserved"; 233 }; 234 wkup_uart0: serial@42300000 { 235 compatible = "ti,j721e-uart", "ti,am654-uart"; 236 reg = <0x00 0x42300000 0x00 0x100>; 237 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 238 clock-frequency = <48000000>; 239 current-speed = <115200>; 240 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 241 clocks = <&k3_clks 287 0>; 242 clock-names = "fclk"; 243 status = "disabled"; 244 }; 245 246 mcu_uart0: serial@40a00000 { 247 compatible = "ti,j721e-uart", "ti,am654-uart"; 248 reg = <0x00 0x40a00000 0x00 0x100>; 249 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 250 clock-frequency = <96000000>; 251 current-speed = <115200>; 252 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 253 clocks = <&k3_clks 149 0>; 254 clock-names = "fclk"; 255 status = "disabled"; 256 }; 257 258 wkup_gpio_intr: interrupt-controller@42200000 { 259 compatible = "ti,sci-intr"; 260 reg = <0x00 0x42200000 0x00 0x400>; 261 ti,intr-trigger-type = <1>; 262 interrupt-controller; 263 interrupt-parent = <&gic500>; 264 #interrupt-cells = <1>; 265 ti,sci = <&dmsc>; 266 ti,sci-dev-id = <137>; 267 ti,interrupt-ranges = <16 960 16>; 268 }; 269 270 wkup_gpio0: gpio@42110000 { 271 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 272 reg = <0x0 0x42110000 0x0 0x100>; 273 gpio-controller; 274 #gpio-cells = <2>; 275 interrupt-parent = <&wkup_gpio_intr>; 276 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 ti,ngpio = <84>; 280 ti,davinci-gpio-unbanked = <0>; 281 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 282 clocks = <&k3_clks 113 0>; 283 clock-names = "gpio"; 284 }; 285 286 wkup_gpio1: gpio@42100000 { 287 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 288 reg = <0x0 0x42100000 0x0 0x100>; 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-parent = <&wkup_gpio_intr>; 292 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 ti,ngpio = <84>; 296 ti,davinci-gpio-unbanked = <0>; 297 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 298 clocks = <&k3_clks 114 0>; 299 clock-names = "gpio"; 300 }; 301 302 mcu_i2c0: i2c@40b00000 { 303 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 304 reg = <0x0 0x40b00000 0x0 0x100>; 305 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 clock-names = "fck"; 309 clocks = <&k3_clks 194 0>; 310 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 311 status = "disabled"; 312 }; 313 314 mcu_i2c1: i2c@40b10000 { 315 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 316 reg = <0x0 0x40b10000 0x0 0x100>; 317 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 clock-names = "fck"; 321 clocks = <&k3_clks 195 0>; 322 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 323 status = "disabled"; 324 }; 325 326 wkup_i2c0: i2c@42120000 { 327 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 328 reg = <0x0 0x42120000 0x0 0x100>; 329 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 clock-names = "fck"; 333 clocks = <&k3_clks 197 0>; 334 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 335 status = "disabled"; 336 }; 337 338 fss: fss@47000000 { 339 compatible = "simple-bus"; 340 reg = <0x0 0x47000000 0x0 0x100>; 341 #address-cells = <2>; 342 #size-cells = <2>; 343 ranges; 344 345 hbmc_mux: mux-controller@47000004 { 346 compatible = "reg-mux"; 347 reg = <0x00 0x47000004 0x00 0x2>; 348 #mux-control-cells = <1>; 349 mux-reg-masks = <0x4 0x2>; /* HBMC select */ 350 }; 351 352 hbmc: hyperbus@47034000 { 353 compatible = "ti,am654-hbmc"; 354 reg = <0x00 0x47034000 0x00 0x100>, 355 <0x05 0x00000000 0x01 0x0000000>; 356 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 357 clocks = <&k3_clks 102 0>; 358 assigned-clocks = <&k3_clks 102 5>; 359 assigned-clock-rates = <333333333>; 360 #address-cells = <2>; 361 #size-cells = <1>; 362 mux-controls = <&hbmc_mux 0>; 363 status = "disabled"; 364 }; 365 366 ospi0: spi@47040000 { 367 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 368 reg = <0x0 0x47040000 0x0 0x100>, 369 <0x5 0x00000000 0x1 0x0000000>; 370 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 371 cdns,fifo-depth = <256>; 372 cdns,fifo-width = <4>; 373 cdns,trigger-address = <0x0>; 374 clocks = <&k3_clks 103 0>; 375 assigned-clocks = <&k3_clks 103 0>; 376 assigned-clock-parents = <&k3_clks 103 2>; 377 assigned-clock-rates = <166666666>; 378 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 }; 382 383 ospi1: spi@47050000 { 384 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 385 reg = <0x0 0x47050000 0x0 0x100>, 386 <0x7 0x00000000 0x1 0x00000000>; 387 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 388 cdns,fifo-depth = <256>; 389 cdns,fifo-width = <4>; 390 cdns,trigger-address = <0x0>; 391 clocks = <&k3_clks 104 0>; 392 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 }; 396 }; 397 398 tscadc0: tscadc@40200000 { 399 compatible = "ti,am3359-tscadc"; 400 reg = <0x0 0x40200000 0x0 0x1000>; 401 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 402 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 0 1>; 404 assigned-clocks = <&k3_clks 0 3>; 405 assigned-clock-rates = <60000000>; 406 clock-names = "fck"; 407 dmas = <&main_udmap 0x7400>, 408 <&main_udmap 0x7401>; 409 dma-names = "fifo0", "fifo1"; 410 411 adc { 412 #io-channel-cells = <1>; 413 compatible = "ti,am3359-adc"; 414 }; 415 }; 416 417 tscadc1: tscadc@40210000 { 418 compatible = "ti,am3359-tscadc"; 419 reg = <0x0 0x40210000 0x0 0x1000>; 420 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 421 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 422 clocks = <&k3_clks 1 1>; 423 assigned-clocks = <&k3_clks 1 3>; 424 assigned-clock-rates = <60000000>; 425 clock-names = "fck"; 426 dmas = <&main_udmap 0x7402>, 427 <&main_udmap 0x7403>; 428 dma-names = "fifo0", "fifo1"; 429 430 adc { 431 #io-channel-cells = <1>; 432 compatible = "ti,am3359-adc"; 433 }; 434 }; 435 436 mcu_navss: bus@28380000 { 437 compatible = "simple-mfd"; 438 #address-cells = <2>; 439 #size-cells = <2>; 440 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 441 dma-coherent; 442 dma-ranges; 443 444 ti,sci-dev-id = <232>; 445 446 mcu_ringacc: ringacc@2b800000 { 447 compatible = "ti,am654-navss-ringacc"; 448 reg = <0x0 0x2b800000 0x0 0x400000>, 449 <0x0 0x2b000000 0x0 0x400000>, 450 <0x0 0x28590000 0x0 0x100>, 451 <0x0 0x2a500000 0x0 0x40000>, 452 <0x0 0x28440000 0x0 0x40000>; 453 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 454 ti,num-rings = <286>; 455 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 456 ti,sci = <&dmsc>; 457 ti,sci-dev-id = <235>; 458 msi-parent = <&main_udmass_inta>; 459 }; 460 461 mcu_udmap: dma-controller@285c0000 { 462 compatible = "ti,j721e-navss-mcu-udmap"; 463 reg = <0x0 0x285c0000 0x0 0x100>, 464 <0x0 0x2a800000 0x0 0x40000>, 465 <0x0 0x2aa00000 0x0 0x40000>; 466 reg-names = "gcfg", "rchanrt", "tchanrt"; 467 msi-parent = <&main_udmass_inta>; 468 #dma-cells = <1>; 469 470 ti,sci = <&dmsc>; 471 ti,sci-dev-id = <236>; 472 ti,ringacc = <&mcu_ringacc>; 473 474 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 475 <0x0f>; /* TX_HCHAN */ 476 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 477 <0x0b>; /* RX_HCHAN */ 478 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 479 }; 480 }; 481 482 secure_proxy_mcu: mailbox@2a480000 { 483 compatible = "ti,am654-secure-proxy"; 484 #mbox-cells = <1>; 485 reg-names = "target_data", "rt", "scfg"; 486 reg = <0x0 0x2a480000 0x0 0x80000>, 487 <0x0 0x2a380000 0x0 0x80000>, 488 <0x0 0x2a400000 0x0 0x80000>; 489 /* 490 * Marked Disabled: 491 * Node is incomplete as it is meant for bootloaders and 492 * firmware on non-MPU processors 493 */ 494 status = "disabled"; 495 }; 496 497 mcu_cpsw: ethernet@46000000 { 498 compatible = "ti,j721e-cpsw-nuss"; 499 #address-cells = <2>; 500 #size-cells = <2>; 501 reg = <0x0 0x46000000 0x0 0x200000>; 502 reg-names = "cpsw_nuss"; 503 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 504 dma-coherent; 505 clocks = <&k3_clks 18 22>; 506 clock-names = "fck"; 507 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 508 509 dmas = <&mcu_udmap 0xf000>, 510 <&mcu_udmap 0xf001>, 511 <&mcu_udmap 0xf002>, 512 <&mcu_udmap 0xf003>, 513 <&mcu_udmap 0xf004>, 514 <&mcu_udmap 0xf005>, 515 <&mcu_udmap 0xf006>, 516 <&mcu_udmap 0xf007>, 517 <&mcu_udmap 0x7000>; 518 dma-names = "tx0", "tx1", "tx2", "tx3", 519 "tx4", "tx5", "tx6", "tx7", 520 "rx"; 521 522 ethernet-ports { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 526 cpsw_port1: port@1 { 527 reg = <1>; 528 ti,mac-only; 529 label = "port1"; 530 ti,syscon-efuse = <&mcu_conf 0x200>; 531 phys = <&phy_gmii_sel 1>; 532 }; 533 }; 534 535 davinci_mdio: mdio@f00 { 536 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 537 reg = <0x0 0xf00 0x0 0x100>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clocks = <&k3_clks 18 22>; 541 clock-names = "fck"; 542 bus_freq = <1000000>; 543 }; 544 545 cpts@3d000 { 546 compatible = "ti,am65-cpts"; 547 reg = <0x0 0x3d000 0x0 0x400>; 548 clocks = <&k3_clks 18 2>; 549 clock-names = "cpts"; 550 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "cpts"; 552 ti,cpts-ext-ts-inputs = <4>; 553 ti,cpts-periodic-outputs = <2>; 554 }; 555 }; 556 557 mcu_r5fss0: r5fss@41000000 { 558 compatible = "ti,j721e-r5fss"; 559 ti,cluster-mode = <1>; 560 #address-cells = <1>; 561 #size-cells = <1>; 562 ranges = <0x41000000 0x00 0x41000000 0x20000>, 563 <0x41400000 0x00 0x41400000 0x20000>; 564 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 565 566 mcu_r5fss0_core0: r5f@41000000 { 567 compatible = "ti,j721e-r5f"; 568 reg = <0x41000000 0x00008000>, 569 <0x41010000 0x00008000>; 570 reg-names = "atcm", "btcm"; 571 ti,sci = <&dmsc>; 572 ti,sci-dev-id = <250>; 573 ti,sci-proc-ids = <0x01 0xff>; 574 resets = <&k3_reset 250 1>; 575 firmware-name = "j7-mcu-r5f0_0-fw"; 576 ti,atcm-enable = <1>; 577 ti,btcm-enable = <1>; 578 ti,loczrama = <1>; 579 }; 580 581 mcu_r5fss0_core1: r5f@41400000 { 582 compatible = "ti,j721e-r5f"; 583 reg = <0x41400000 0x00008000>, 584 <0x41410000 0x00008000>; 585 reg-names = "atcm", "btcm"; 586 ti,sci = <&dmsc>; 587 ti,sci-dev-id = <251>; 588 ti,sci-proc-ids = <0x02 0xff>; 589 resets = <&k3_reset 251 1>; 590 firmware-name = "j7-mcu-r5f0_1-fw"; 591 ti,atcm-enable = <1>; 592 ti,btcm-enable = <1>; 593 ti,loczrama = <1>; 594 }; 595 }; 596 597 mcu_mcan0: can@40528000 { 598 compatible = "bosch,m_can"; 599 reg = <0x00 0x40528000 0x00 0x200>, 600 <0x00 0x40500000 0x00 0x8000>; 601 reg-names = "m_can", "message_ram"; 602 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 603 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; 604 clock-names = "hclk", "cclk"; 605 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "int0", "int1"; 608 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 609 status = "disabled"; 610 }; 611 612 mcu_mcan1: can@40568000 { 613 compatible = "bosch,m_can"; 614 reg = <0x00 0x40568000 0x00 0x200>, 615 <0x00 0x40540000 0x00 0x8000>; 616 reg-names = "m_can", "message_ram"; 617 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 618 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; 619 clock-names = "hclk", "cclk"; 620 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 622 interrupt-names = "int0", "int1"; 623 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 624 status = "disabled"; 625 }; 626 627 mcu_spi0: spi@40300000 { 628 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 629 reg = <0x00 0x040300000 0x00 0x400>; 630 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 634 clocks = <&k3_clks 274 0>; 635 status = "disabled"; 636 }; 637 638 mcu_spi1: spi@40310000 { 639 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 640 reg = <0x00 0x040310000 0x00 0x400>; 641 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 645 clocks = <&k3_clks 275 0>; 646 status = "disabled"; 647 }; 648 649 mcu_spi2: spi@40320000 { 650 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 651 reg = <0x00 0x040320000 0x00 0x400>; 652 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 656 clocks = <&k3_clks 276 0>; 657 status = "disabled"; 658 }; 659 660 wkup_vtm0: temperature-sensor@42040000 { 661 compatible = "ti,j721e-vtm"; 662 reg = <0x00 0x42040000 0x00 0x350>, 663 <0x00 0x42050000 0x00 0x350>, 664 <0x00 0x43000300 0x00 0x10>; 665 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 666 #thermal-sensor-cells = <1>; 667 }; 668}; 669