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Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10 |
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| #
43ffe817 |
| 10-Dec-2020 |
Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
arm64: dts: bitmain: Use generic "ngpios" rather than "snps,nr-gpios"
This is to remove similar errors as below:
OF: /.../gpio-port@0: could not find phandle
Commit 7569486d79ae ("gpio: dwapb: Add
arm64: dts: bitmain: Use generic "ngpios" rather than "snps,nr-gpios"
This is to remove similar errors as below:
OF: /.../gpio-port@0: could not find phandle
Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
explained the reason of above errors well and added the generic
"ngpios" property, let's use it.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20201210094056.54553-1-manivannan.sadhasivam@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
show more ...
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|
Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12 |
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| #
dee0be5c |
| 13-Jan-2020 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Source common clock for UART controllers
Remove fixed clock and source common clock for UART controllers.
Link: https://lore.kernel.org/r/20200114040311.6599-3-manivannan.sadha
arm64: dts: bitmain: Source common clock for UART controllers
Remove fixed clock and source common clock for UART controllers.
Link: https://lore.kernel.org/r/20200114040311.6599-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
show more ...
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| #
e1cd7b80 |
| 13-Jan-2020 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add clock controller support for BM1880 SoC
Add clock controller support for Bitmain BM1880 SoC.
Link: https://lore.kernel.org/r/20200114040311.6599-2-manivannan.sadhasivam@lin
arm64: dts: bitmain: Add clock controller support for BM1880 SoC
Add clock controller support for Bitmain BM1880 SoC.
Link: https://lore.kernel.org/r/20200114040311.6599-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
show more ...
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|
Revision tags: v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3 |
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| #
ca33f735 |
| 16-May-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Modify pin controller memory map
Earlier, the PWM registers were included as part of the pinctrl memory
map, but this turned to be useless as the muxing is being handled by the
arm64: dts: bitmain: Modify pin controller memory map
Earlier, the PWM registers were included as part of the pinctrl memory
map, but this turned to be useless as the muxing is being handled by the
SoC pin controller itself. Hence, this commit removes the pwm register
mapping from the pinctrl node to make it more clean.
Fixes: af2ff87de413 ("arm64: dts: bitmain: Add pinctrl support for BM1880 SoC")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
show more ...
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| #
7d545e77 |
| 03-Aug-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add reset controller support for BM1880 SoC
Add reset controller support for Bitmain BM1880 SoC. This commit also
adds reset support to UART peripherals.
Signed-off-by: Manivan
arm64: dts: bitmain: Add reset controller support for BM1880 SoC
Add reset controller support for Bitmain BM1880 SoC. This commit also
adds reset support to UART peripherals.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
show more ...
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|
Revision tags: v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10 |
|
| #
c1294fb5 |
| 24-Apr-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports
pinmuxing and the pinctrl registers are part of the sctrl block.
Signed-of
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports
pinmuxing and the pinctrl registers are part of the sctrl block.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
show more ...
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|
Revision tags: v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26 |
|
| #
367e5927 |
| 26-Feb-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.
Signe
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
show more ...
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|
Revision tags: v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18 |
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| #
c8ec3743 |
| 25-Jan-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add BM1880 SoC support
Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
Processor s
arm64: dts: bitmain: Add BM1880 SoC support
Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
Processor subsystem. Only ARM Cortex A53 Application processor subsystem
support is enabled for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
show more ...
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12 |
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| #
dee0be5c |
| 13-Jan-2020 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Source common clock for UART controllers
Remove fixed clock and source common clock for UART controllers.
Link: https://lore.kernel.org/r/20200114040311.6599-3-
arm64: dts: bitmain: Source common clock for UART controllers
Remove fixed clock and source common clock for UART controllers.
Link: https://lore.kernel.org/r/20200114040311.6599-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
show more ...
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| #
e1cd7b80 |
| 13-Jan-2020 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add clock controller support for BM1880 SoC
Add clock controller support for Bitmain BM1880 SoC.
Link: https://lore.kernel.org/r/20200114040311.6599-2-manivanna
arm64: dts: bitmain: Add clock controller support for BM1880 SoC
Add clock controller support for Bitmain BM1880 SoC.
Link: https://lore.kernel.org/r/20200114040311.6599-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
show more ...
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|
Revision tags: v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3 |
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| #
ca33f735 |
| 16-May-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Modify pin controller memory map
Earlier, the PWM registers were included as part of the pinctrl memory
map, but this turned to be useless as the muxing is being han
arm64: dts: bitmain: Modify pin controller memory map
Earlier, the PWM registers were included as part of the pinctrl memory
map, but this turned to be useless as the muxing is being handled by the
SoC pin controller itself. Hence, this commit removes the pwm register
mapping from the pinctrl node to make it more clean.
Fixes: af2ff87de413 ("arm64: dts: bitmain: Add pinctrl support for BM1880 SoC")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
show more ...
|
| #
7d545e77 |
| 03-Aug-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add reset controller support for BM1880 SoC
Add reset controller support for Bitmain BM1880 SoC. This commit also
adds reset support to UART peripherals.
Si
arm64: dts: bitmain: Add reset controller support for BM1880 SoC
Add reset controller support for Bitmain BM1880 SoC. This commit also
adds reset support to UART peripherals.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
show more ...
|
|
Revision tags: v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10 |
|
| #
c1294fb5 |
| 24-Apr-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports
pinmuxing and the pinctrl registers are part of the sctrl block
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports
pinmuxing and the pinctrl registers are part of the sctrl block.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
show more ...
|
|
Revision tags: v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26 |
|
| #
367e5927 |
| 26-Feb-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
show more ...
|
|
Revision tags: v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18 |
|
| #
c8ec3743 |
| 25-Jan-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: bitmain: Add BM1880 SoC support
Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
arm64: dts: bitmain: Add BM1880 SoC support
Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
Processor subsystem. Only ARM Cortex A53 Application processor subsystem
support is enabled for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
show more ...
|