1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Linaro Ltd. 4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 compatible = "bitmain,bm1880"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a53"; 22 reg = <0x0>; 23 enable-method = "psci"; 24 }; 25 26 cpu1: cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a53"; 29 reg = <0x1>; 30 enable-method = "psci"; 31 }; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 secmon@100000000 { 40 reg = <0x1 0x00000000 0x0 0x20000>; 41 no-map; 42 }; 43 44 jpu@130000000 { 45 reg = <0x1 0x30000000 0x0 0x08000000>; // 128M 46 no-map; 47 }; 48 49 vpu@138000000 { 50 reg = <0x1 0x38000000 0x0 0x08000000>; // 128M 51 no-map; 52 }; 53 }; 54 55 psci { 56 compatible = "arm,psci-0.2"; 57 method = "smc"; 58 }; 59 60 timer { 61 compatible = "arm,armv8-timer"; 62 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 63 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 64 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 65 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 66 }; 67 68 soc { 69 compatible = "simple-bus"; 70 #address-cells = <2>; 71 #size-cells = <2>; 72 ranges; 73 74 gic: interrupt-controller@50001000 { 75 compatible = "arm,gic-400"; 76 reg = <0x0 0x50001000 0x0 0x1000>, 77 <0x0 0x50002000 0x0 0x2000>; 78 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 79 interrupt-controller; 80 #interrupt-cells = <3>; 81 }; 82 83 gpio0: gpio@50027000 { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 compatible = "snps,dw-apb-gpio"; 87 reg = <0x0 0x50027000 0x0 0x400>; 88 89 porta: gpio-controller@0 { 90 compatible = "snps,dw-apb-gpio-port"; 91 gpio-controller; 92 #gpio-cells = <2>; 93 snps,nr-gpios = <32>; 94 reg = <0>; 95 interrupt-controller; 96 #interrupt-cells = <2>; 97 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 98 }; 99 }; 100 101 gpio1: gpio@50027400 { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 compatible = "snps,dw-apb-gpio"; 105 reg = <0x0 0x50027400 0x0 0x400>; 106 107 portb: gpio-controller@0 { 108 compatible = "snps,dw-apb-gpio-port"; 109 gpio-controller; 110 #gpio-cells = <2>; 111 snps,nr-gpios = <32>; 112 reg = <0>; 113 interrupt-controller; 114 #interrupt-cells = <2>; 115 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 116 }; 117 }; 118 119 gpio2: gpio@50027800 { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "snps,dw-apb-gpio"; 123 reg = <0x0 0x50027800 0x0 0x400>; 124 125 portc: gpio-controller@0 { 126 compatible = "snps,dw-apb-gpio-port"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 snps,nr-gpios = <8>; 130 reg = <0>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 134 }; 135 }; 136 137 uart0: serial@58018000 { 138 compatible = "snps,dw-apb-uart"; 139 reg = <0x0 0x58018000 0x0 0x2000>; 140 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 141 reg-shift = <2>; 142 reg-io-width = <4>; 143 status = "disabled"; 144 }; 145 146 uart1: serial@5801A000 { 147 compatible = "snps,dw-apb-uart"; 148 reg = <0x0 0x5801a000 0x0 0x2000>; 149 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 150 reg-shift = <2>; 151 reg-io-width = <4>; 152 status = "disabled"; 153 }; 154 155 uart2: serial@5801C000 { 156 compatible = "snps,dw-apb-uart"; 157 reg = <0x0 0x5801c000 0x0 0x2000>; 158 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 159 reg-shift = <2>; 160 reg-io-width = <4>; 161 status = "disabled"; 162 }; 163 164 uart3: serial@5801E000 { 165 compatible = "snps,dw-apb-uart"; 166 reg = <0x0 0x5801e000 0x0 0x2000>; 167 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 168 reg-shift = <2>; 169 reg-io-width = <4>; 170 status = "disabled"; 171 }; 172 }; 173}; 174