Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
88893986 |
| 21-Dec-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode.
This patch adds clock ID for this t
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
b4997797 |
| 21-Dec-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode.
This patch adds clock ID for this t
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6 |
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#
cd4d6f35 |
| 29-May-2019 |
Joseph Lo <josephl@nvidia.com> |
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by:
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
796705bc |
| 04-May-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock ID for this CSI TPG clock from PLLD.
Acked-by: Rob Herring <robh@ker
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock ID for this CSI TPG clock from PLLD.
Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
c9585405 |
| 14-Jan-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: clock: tegra: Remove PMC clock IDs
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so these clocks should be provided by the Tegra PMC. IDs for these clocks have been
dt-bindings: clock: tegra: Remove PMC clock IDs
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so these clocks should be provided by the Tegra PMC. IDs for these clocks have been defined in dt-bindings/soc/tegra-pmc.h.
This patch removes the IDs for these clocks from the Tegra clock device tree bindings.
Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
e5377ab2 |
| 14-Jan-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: clock: tegra: Add IDs for OSC clocks
Tegra has OSC, OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3 for
dt-bindings: clock: tegra: Add IDs for OSC clocks
Tegra has OSC, OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3 for Tegra30 through Tegra210.
So, this patch adds ids for these clocks.
Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
05308d7e |
| 24-Jun-2019 |
Thierry Reding <treding@nvidia.com> |
clk: tegra: Reimplement SOR clocks on Tegra210
In order to allow the display driver to deal uniformly with all SOR generations, implement the SOR clocks in a way that is compatible with Tegra186 and
clk: tegra: Reimplement SOR clocks on Tegra210
In order to allow the display driver to deal uniformly with all SOR generations, implement the SOR clocks in a way that is compatible with Tegra186 and later.
Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
991a051e |
| 28-Jun-2019 |
Thierry Reding <treding@nvidia.com> |
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
Later SoC generations implement this clock as SOR1_OUT. For consistency, the Tegra210 implementation was adapted to match the same name in co
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
Later SoC generations implement this clock as SOR1_OUT. For consistency, the Tegra210 implementation was adapted to match the same name in commit 4d1dc4018573 ("dt-bindings: clock: tegra: Add sor1_out clock").
Clean up the remaining pieces by adopting the new name for the internal identifiers and remove the old alias. Note that since both SOR1_SRC and SOR1_OUT were referring to the same device tree clock ID, this does not break device tree ABI.
Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
cdc2d668 |
| 29-Oct-2019 |
Thierry Reding <treding@nvidia.com> |
dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT
Tegra186 and later call this clock SOR0_OUT. Rename it on Tegra124 and Tegra210 to make the names consistent.
Keep the old name for now to ke
dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT
Tegra186 and later call this clock SOR0_OUT. Rename it on Tegra124 and Tegra210 to make the names consistent.
Keep the old name for now to keep device trees buildable until they have all been converted.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17, v4.16, v4.15 |
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#
89e423c3 |
| 25-Jan-2018 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add la clock for Tegra210
This clock is needed by the memory built-in self test work around.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonatha
clk: tegra: Add la clock for Tegra210
This clock is needed by the memory built-in self test work around.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.13.16, v4.14 |
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#
b2441318 |
| 01-Nov-2017 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license identifiers to apply.
- when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary:
SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became the concluded license(s).
- when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time.
In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related.
Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v4.13.5, v4.13 |
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#
4d1dc401 |
| 30-Aug-2017 |
Thierry Reding <treding@nvidia.com> |
dt-bindings: clock: tegra: Add sor1_out clock
The sor1_src clock implemented on Tegra210 is modelled the wrong way around, which causes some issues with HDMI and DP support. This clock implementatio
dt-bindings: clock: tegra: Add sor1_out clock
The sor1_src clock implemented on Tegra210 is modelled the wrong way around, which causes some issues with HDMI and DP support. This clock implementation is provided by BPMP on Tegra186, which models this in a more correct way. Since this introduces incompatibilities between the two SoC generations which we want to avoid, the Tegra210 will be fixed in subsequent patches.
This change adds sor1_out as an alias for sor1_src.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.12, v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7, v4.10.6 |
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#
88da44c5 |
| 22-Mar-2017 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add missing Tegra210 clocks
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp and adsp neon were not modelled. dp2 wasn't modelled for Tegra210.
Signed-off-by: P
clk: tegra: Add missing Tegra210 clocks
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp and adsp neon were not modelled. dp2 wasn't modelled for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.10.5, v4.10.4, v4.10.3, v4.10.2 |
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#
24c3ebef |
| 28-Feb-2017 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add aclk
This clock clocks the ADSP Cortex-A9.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttune
clk: tegra: Add aclk
This clock clocks the ADSP Cortex-A9.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
319af797 |
| 28-Feb-2017 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Define Tegra210 DMIC sync clocks
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we add a 3 n
clk: tegra: Define Tegra210 DMIC sync clocks
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we add a 3 new clocks similar to the audio* clocks which handle the same function for the I2S and SPDIF clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
bfa34832 |
| 28-Feb-2017 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Add CEC clock
This clock is used to clock the HDMI CEC interface.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested
clk: tegra: Add CEC clock
This clock is used to clock the HDMI CEC interface.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.10.1 |
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#
34ac2c27 |
| 23-Feb-2017 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Fix ISP clock modelling
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <pdes
clk: tegra: Fix ISP clock modelling
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.10, v4.9, openbmc-4.4-20161121-1, v4.4.33, v4.4.32, v4.4.31, v4.4.30, v4.4.29, v4.4.28, v4.4.27, v4.7.10, openbmc-4.4-20161021-1, v4.7.9, v4.4.26, v4.7.8, v4.4.25, v4.4.24, v4.7.7, v4.8, v4.4.23, v4.7.6, v4.7.5, v4.4.22, v4.4.21, v4.7.4, v4.7.3, v4.4.20, v4.7.2, v4.4.19, openbmc-4.4-20160819-1, v4.7.1, v4.4.18, v4.4.17, openbmc-4.4-20160804-1, v4.4.16, v4.7, openbmc-4.4-20160722-1, openbmc-20160722-1, openbmc-20160713-1, v4.4.15, v4.6.4, v4.6.3, v4.4.14 |
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e452b818 |
| 09-Jun-2016 |
Thierry Reding <treding@nvidia.com> |
clk: tegra: Enable sor1 and sor1_src on Tegra210
Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP.
Signed-off-by: Thierry Redi
clk: tegra: Enable sor1 and sor1_src on Tegra210
Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.6.2, v4.4.13, openbmc-20160606-1, v4.6.1, v4.4.12, openbmc-20160521-1, v4.4.11, openbmc-20160518-1, v4.6, v4.4.10, openbmc-20160511-1, openbmc-20160505-1, v4.4.9, v4.4.8, v4.4.7, openbmc-20160329-2, openbmc-20160329-1 |
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926655f9 |
| 21-Mar-2016 |
Rhyland Klein <rklein@nvidia.com> |
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields.
Additionally define
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields.
Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: define PLLRE_OUT1 register offset] Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: openbmc-20160321-1, v4.4.6, v4.5, v4.4.5, v4.4.4, v4.4.3, openbmc-20160222-1, v4.4.2, openbmc-20160212-1, openbmc-20160210-1, openbmc-20160202-2, openbmc-20160202-1, v4.4.1 |
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29569941 |
| 28-Jan-2016 |
Jon Hunter <jonathanh@nvidia.com> |
clk: tegra: Add the APB2APE audio clock on Tegra210
The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem o
clk: tegra: Add the APB2APE audio clock on Tegra210
The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: openbmc-20160127-1, openbmc-20160120-1, v4.4, openbmc-20151217-1, openbmc-20151210-1, openbmc-20151202-1, openbmc-20151123-1, openbmc-20151118-1 |
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1d15cb9c |
| 15-Nov-2015 |
Thierry Reding <treding@nvidia.com> |
clk: tegra: Add Tegra210 device tree binding
Add a header file that defines the clock numbers for Tegra210. It is meant to be included by device trees so that they can refer to the clocks by symboli
clk: tegra: Add Tegra210 device tree binding
Add a header file that defines the clock numbers for Tegra210. It is meant to be included by device trees so that they can refer to the clocks by symbolic name instead of numeric value.
Also add the device tree binding documentation which is largely the same as for earlier generations of Tegra.
Extracted from a larger patch by Rhyland Klein <rklein@nvidia.com>.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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6f630784 |
| 10-Jun-2020 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time around we have four lines of diff in the core framewo
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time around we have four lines of diff in the core framework, removing a function that isn't used anymore. Otherwise the main new thing for the common clk framework is that it is selectable in the Kconfig language now. Hopefully this will let clk drivers and clk consumers be testable on more than the architectures that support the clk framework. The goal is to introduce some Kunit tests for the framework. Outside of the core framework we have the usual set of various driver updates and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the largest addition this time around in terms of lines of code. After that the x86 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or upcoming SoCs. After that the dirstat shows the usual suspects working on their SoC support by fixing minor bugs, correcting data and converting some of their DT bindings to YAML. Core: - Allow the COMMON_CLK config to be selectable New Drivers: - Clk driver for Baikal-T1 SoCs - Mediatek MT6765 clock support - Support for Intel Agilex clks - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for the new Renesas RZ/G1H (R8A7742) SoC - Add support for Qualcomm's MSM8939 Generic Clock Controller Updates: - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - A single minor rounding fix for the legacy Allwinner clock support - A few patches from Abel Vesa as preparation of adding audiomix clock support on i.MX - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3 drivers - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates - A couple changes for EMC frequency scaling on Tegra210 - Support for CPU frequency scaling on Tegra20/Tegra30 - New clk gate for CSI test pattern generator on Tegra210 - Regression fixes for Samsung exynos542x and exynos5433 SoCs - Use of fallthrough; attribute for Samsung s3c24xx - Updates and fixup HDMI and video clocks on Meson8b - Fixup reset polarity on Meson8b - Fix GPU glitch free mux switch on Meson gx and g12 - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits) clk: mediatek: Remove ifr{0,1}_cfg_regs structures clk: baikal-t1: remove redundant assignment to variable 'divider' clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible" dt-bindings: clock: Add a missing include to MMP Audio Clock binding dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first clk: clk-si5341: Add support for the Si5345 series ...
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6 |
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cd4d6f35 |
| 29-May-2019 |
Joseph Lo <josephl@nvidia.com> |
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source. Signed-off-by: Joseph Lo <josephl@nvidia
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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796705bc |
| 04-May-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock ID for this CSI TPG clock from PLLD. Acked-by: R
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock ID for this CSI TPG clock from PLLD. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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c9585405 |
| 14-Jan-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: clock: tegra: Remove PMC clock IDs clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so these clocks should be provided by the Tegra PMC. IDs for these cloc
dt-bindings: clock: tegra: Remove PMC clock IDs clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so these clocks should be provided by the Tegra PMC. IDs for these clocks have been defined in dt-bindings/soc/tegra-pmc.h. This patch removes the IDs for these clocks from the Tegra clock device tree bindings. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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