1 /*
2  * This header provides constants for binding nvidia,tegra210-car.
3  *
4  * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7  * this case, those clocks are assigned IDs above 224 in order to highlight
8  * this issue. Implementations that interpret these clock IDs as bit values
9  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10  * explicitly handle these special cases.
11  *
12  * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
13  * above.
14  */
15 
16 #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
17 #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
18 
19 /* 0 */
20 /* 1 */
21 /* 2 */
22 #define TEGRA210_CLK_ISPB 3
23 #define TEGRA210_CLK_RTC 4
24 #define TEGRA210_CLK_TIMER 5
25 #define TEGRA210_CLK_UARTA 6
26 /* 7 (register bit affects uartb and vfir) */
27 #define TEGRA210_CLK_GPIO 8
28 #define TEGRA210_CLK_SDMMC2 9
29 /* 10 (register bit affects spdif_in and spdif_out) */
30 #define TEGRA210_CLK_I2S1 11
31 #define TEGRA210_CLK_I2C1 12
32 /* 13 */
33 #define TEGRA210_CLK_SDMMC1 14
34 #define TEGRA210_CLK_SDMMC4 15
35 /* 16 */
36 #define TEGRA210_CLK_PWM 17
37 #define TEGRA210_CLK_I2S2 18
38 /* 19 */
39 /* 20 (register bit affects vi and vi_sensor) */
40 /* 21 */
41 #define TEGRA210_CLK_USBD 22
42 #define TEGRA210_CLK_ISP 23
43 /* 24 */
44 /* 25 */
45 #define TEGRA210_CLK_DISP2 26
46 #define TEGRA210_CLK_DISP1 27
47 #define TEGRA210_CLK_HOST1X 28
48 /* 29 */
49 #define TEGRA210_CLK_I2S0 30
50 /* 31 */
51 
52 #define TEGRA210_CLK_MC 32
53 #define TEGRA210_CLK_AHBDMA 33
54 #define TEGRA210_CLK_APBDMA 34
55 /* 35 */
56 /* 36 */
57 /* 37 */
58 #define TEGRA210_CLK_PMC 38
59 /* 39 (register bit affects fuse and fuse_burn) */
60 #define TEGRA210_CLK_KFUSE 40
61 #define TEGRA210_CLK_SBC1 41
62 /* 42 */
63 /* 43 */
64 #define TEGRA210_CLK_SBC2 44
65 /* 45 */
66 #define TEGRA210_CLK_SBC3 46
67 #define TEGRA210_CLK_I2C5 47
68 #define TEGRA210_CLK_DSIA 48
69 /* 49 */
70 /* 50 */
71 /* 51 */
72 #define TEGRA210_CLK_CSI 52
73 /* 53 */
74 #define TEGRA210_CLK_I2C2 54
75 #define TEGRA210_CLK_UARTC 55
76 #define TEGRA210_CLK_MIPI_CAL 56
77 #define TEGRA210_CLK_EMC 57
78 #define TEGRA210_CLK_USB2 58
79 /* 59 */
80 /* 60 */
81 /* 61 */
82 /* 62 */
83 #define TEGRA210_CLK_BSEV 63
84 
85 /* 64 */
86 #define TEGRA210_CLK_UARTD 65
87 /* 66 */
88 #define TEGRA210_CLK_I2C3 67
89 #define TEGRA210_CLK_SBC4 68
90 #define TEGRA210_CLK_SDMMC3 69
91 #define TEGRA210_CLK_PCIE 70
92 #define TEGRA210_CLK_OWR 71
93 #define TEGRA210_CLK_AFI 72
94 #define TEGRA210_CLK_CSITE 73
95 /* 74 */
96 /* 75 */
97 /* 76 */
98 /* 77 */
99 #define TEGRA210_CLK_SOC_THERM 78
100 #define TEGRA210_CLK_DTV 79
101 /* 80 */
102 #define TEGRA210_CLK_I2CSLOW 81
103 #define TEGRA210_CLK_DSIB 82
104 #define TEGRA210_CLK_TSEC 83
105 /* 84 */
106 /* 85 */
107 /* 86 */
108 /* 87 */
109 /* 88 */
110 #define TEGRA210_CLK_XUSB_HOST 89
111 /* 90 */
112 /* 91 */
113 #define TEGRA210_CLK_CSUS 92
114 /* 93 */
115 /* 94 */
116 /* 95 (bit affects xusb_dev and xusb_dev_src) */
117 
118 /* 96 */
119 /* 97 */
120 /* 98 */
121 #define TEGRA210_CLK_MSELECT 99
122 #define TEGRA210_CLK_TSENSOR 100
123 #define TEGRA210_CLK_I2S3 101
124 #define TEGRA210_CLK_I2S4 102
125 #define TEGRA210_CLK_I2C4 103
126 /* 104 */
127 /* 105 */
128 #define TEGRA210_CLK_D_AUDIO 106
129 #define TEGRA210_CLK_APB2APE 107
130 /* 108 */
131 /* 109 */
132 /* 110 */
133 #define TEGRA210_CLK_HDA2CODEC_2X 111
134 /* 112 */
135 /* 113 */
136 /* 114 */
137 /* 115 */
138 /* 116 */
139 /* 117 */
140 #define TEGRA210_CLK_SPDIF_2X 118
141 #define TEGRA210_CLK_ACTMON 119
142 #define TEGRA210_CLK_EXTERN1 120
143 #define TEGRA210_CLK_EXTERN2 121
144 #define TEGRA210_CLK_EXTERN3 122
145 #define TEGRA210_CLK_SATA_OOB 123
146 #define TEGRA210_CLK_SATA 124
147 #define TEGRA210_CLK_HDA 125
148 /* 126 */
149 /* 127 */
150 
151 #define TEGRA210_CLK_HDA2HDMI 128
152 /* 129 */
153 /* 130 */
154 /* 131 */
155 /* 132 */
156 /* 133 */
157 /* 134 */
158 /* 135 */
159 /* 136 */
160 /* 137 */
161 /* 138 */
162 /* 139 */
163 /* 140 */
164 /* 141 */
165 /* 142 */
166 /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
167 #define TEGRA210_CLK_XUSB_GATE 143
168 #define TEGRA210_CLK_CILAB 144
169 #define TEGRA210_CLK_CILCD 145
170 #define TEGRA210_CLK_CILE 146
171 #define TEGRA210_CLK_DSIALP 147
172 #define TEGRA210_CLK_DSIBLP 148
173 #define TEGRA210_CLK_ENTROPY 149
174 /* 150 */
175 /* 151 */
176 /* 152 */
177 /* 153 */
178 /* 154 */
179 /* 155 (bit affects dfll_ref and dfll_soc) */
180 #define TEGRA210_CLK_XUSB_SS 156
181 /* 157 */
182 /* 158 */
183 /* 159 */
184 
185 /* 160 */
186 #define TEGRA210_CLK_DMIC1 161
187 #define TEGRA210_CLK_DMIC2 162
188 /* 163 */
189 /* 164 */
190 /* 165 */
191 #define TEGRA210_CLK_I2C6 166
192 /* 167 */
193 /* 168 */
194 /* 169 */
195 /* 170 */
196 #define TEGRA210_CLK_VIM2_CLK 171
197 /* 172 */
198 #define TEGRA210_CLK_MIPIBIF 173
199 /* 174 */
200 /* 175 */
201 /* 176 */
202 #define TEGRA210_CLK_CLK72MHZ 177
203 #define TEGRA210_CLK_VIC03 178
204 /* 179 */
205 /* 180 */
206 #define TEGRA210_CLK_DPAUX 181
207 #define TEGRA210_CLK_SOR0 182
208 #define TEGRA210_CLK_SOR1 183
209 #define TEGRA210_CLK_GPU 184
210 #define TEGRA210_CLK_DBGAPB 185
211 /* 186 */
212 #define TEGRA210_CLK_PLL_P_OUT_ADSP 187
213 /* 188 */
214 #define TEGRA210_CLK_PLL_G_REF 189
215 /* 190 */
216 /* 191 */
217 
218 /* 192 */
219 #define TEGRA210_CLK_SDMMC_LEGACY 193
220 #define TEGRA210_CLK_NVDEC 194
221 #define TEGRA210_CLK_NVJPG 195
222 /* 196 */
223 #define TEGRA210_CLK_DMIC3 197
224 #define TEGRA210_CLK_APE 198
225 /* 199 */
226 /* 200 */
227 /* 201 */
228 #define TEGRA210_CLK_MAUD 202
229 /* 203 */
230 /* 204 */
231 /* 205 */
232 #define TEGRA210_CLK_TSECB 206
233 #define TEGRA210_CLK_DPAUX1 207
234 #define TEGRA210_CLK_VI_I2C 208
235 #define TEGRA210_CLK_HSIC_TRK 209
236 #define TEGRA210_CLK_USB2_TRK 210
237 #define TEGRA210_CLK_QSPI 211
238 #define TEGRA210_CLK_UARTAPE 212
239 /* 213 */
240 /* 214 */
241 /* 215 */
242 /* 216 */
243 /* 217 */
244 /* 218 */
245 #define TEGRA210_CLK_NVENC 219
246 /* 220 */
247 /* 221 */
248 #define TEGRA210_CLK_SOR_SAFE 222
249 #define TEGRA210_CLK_PLL_P_OUT_CPU 223
250 
251 
252 #define TEGRA210_CLK_UARTB 224
253 #define TEGRA210_CLK_VFIR 225
254 #define TEGRA210_CLK_SPDIF_IN 226
255 #define TEGRA210_CLK_SPDIF_OUT 227
256 #define TEGRA210_CLK_VI 228
257 #define TEGRA210_CLK_VI_SENSOR 229
258 #define TEGRA210_CLK_FUSE 230
259 #define TEGRA210_CLK_FUSE_BURN 231
260 #define TEGRA210_CLK_CLK_32K 232
261 #define TEGRA210_CLK_CLK_M 233
262 #define TEGRA210_CLK_CLK_M_DIV2 234
263 #define TEGRA210_CLK_CLK_M_DIV4 235
264 #define TEGRA210_CLK_PLL_REF 236
265 #define TEGRA210_CLK_PLL_C 237
266 #define TEGRA210_CLK_PLL_C_OUT1 238
267 #define TEGRA210_CLK_PLL_C2 239
268 #define TEGRA210_CLK_PLL_C3 240
269 #define TEGRA210_CLK_PLL_M 241
270 #define TEGRA210_CLK_PLL_M_OUT1 242
271 #define TEGRA210_CLK_PLL_P 243
272 #define TEGRA210_CLK_PLL_P_OUT1 244
273 #define TEGRA210_CLK_PLL_P_OUT2 245
274 #define TEGRA210_CLK_PLL_P_OUT3 246
275 #define TEGRA210_CLK_PLL_P_OUT4 247
276 #define TEGRA210_CLK_PLL_A 248
277 #define TEGRA210_CLK_PLL_A_OUT0 249
278 #define TEGRA210_CLK_PLL_D 250
279 #define TEGRA210_CLK_PLL_D_OUT0 251
280 #define TEGRA210_CLK_PLL_D2 252
281 #define TEGRA210_CLK_PLL_D2_OUT0 253
282 #define TEGRA210_CLK_PLL_U 254
283 #define TEGRA210_CLK_PLL_U_480M 255
284 
285 #define TEGRA210_CLK_PLL_U_60M 256
286 #define TEGRA210_CLK_PLL_U_48M 257
287 /* 258 */
288 #define TEGRA210_CLK_PLL_X 259
289 #define TEGRA210_CLK_PLL_X_OUT0 260
290 #define TEGRA210_CLK_PLL_RE_VCO 261
291 #define TEGRA210_CLK_PLL_RE_OUT 262
292 #define TEGRA210_CLK_PLL_E 263
293 #define TEGRA210_CLK_SPDIF_IN_SYNC 264
294 #define TEGRA210_CLK_I2S0_SYNC 265
295 #define TEGRA210_CLK_I2S1_SYNC 266
296 #define TEGRA210_CLK_I2S2_SYNC 267
297 #define TEGRA210_CLK_I2S3_SYNC 268
298 #define TEGRA210_CLK_I2S4_SYNC 269
299 #define TEGRA210_CLK_VIMCLK_SYNC 270
300 #define TEGRA210_CLK_AUDIO0 271
301 #define TEGRA210_CLK_AUDIO1 272
302 #define TEGRA210_CLK_AUDIO2 273
303 #define TEGRA210_CLK_AUDIO3 274
304 #define TEGRA210_CLK_AUDIO4 275
305 #define TEGRA210_CLK_SPDIF 276
306 #define TEGRA210_CLK_CLK_OUT_1 277
307 #define TEGRA210_CLK_CLK_OUT_2 278
308 #define TEGRA210_CLK_CLK_OUT_3 279
309 #define TEGRA210_CLK_BLINK 280
310 /* 281 */
311 /* 282 */
312 /* 283 */
313 #define TEGRA210_CLK_XUSB_HOST_SRC 284
314 #define TEGRA210_CLK_XUSB_FALCON_SRC 285
315 #define TEGRA210_CLK_XUSB_FS_SRC 286
316 #define TEGRA210_CLK_XUSB_SS_SRC 287
317 
318 #define TEGRA210_CLK_XUSB_DEV_SRC 288
319 #define TEGRA210_CLK_XUSB_DEV 289
320 #define TEGRA210_CLK_XUSB_HS_SRC 290
321 #define TEGRA210_CLK_SCLK 291
322 #define TEGRA210_CLK_HCLK 292
323 #define TEGRA210_CLK_PCLK 293
324 #define TEGRA210_CLK_CCLK_G 294
325 #define TEGRA210_CLK_CCLK_LP 295
326 #define TEGRA210_CLK_DFLL_REF 296
327 #define TEGRA210_CLK_DFLL_SOC 297
328 #define TEGRA210_CLK_VI_SENSOR2 298
329 #define TEGRA210_CLK_PLL_P_OUT5 299
330 #define TEGRA210_CLK_CML0 300
331 #define TEGRA210_CLK_CML1 301
332 #define TEGRA210_CLK_PLL_C4 302
333 #define TEGRA210_CLK_PLL_DP 303
334 #define TEGRA210_CLK_PLL_E_MUX 304
335 #define TEGRA210_CLK_PLL_MB 305
336 #define TEGRA210_CLK_PLL_A1 306
337 #define TEGRA210_CLK_PLL_D_DSI_OUT 307
338 #define TEGRA210_CLK_PLL_C4_OUT0 308
339 #define TEGRA210_CLK_PLL_C4_OUT1 309
340 #define TEGRA210_CLK_PLL_C4_OUT2 310
341 #define TEGRA210_CLK_PLL_C4_OUT3 311
342 #define TEGRA210_CLK_PLL_U_OUT 312
343 #define TEGRA210_CLK_PLL_U_OUT1 313
344 #define TEGRA210_CLK_PLL_U_OUT2 314
345 #define TEGRA210_CLK_USB2_HSIC_TRK 315
346 #define TEGRA210_CLK_PLL_P_OUT_HSIO 316
347 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
348 #define TEGRA210_CLK_XUSB_SSP_SRC 318
349 /* 319 */
350 /* 320 */
351 /* 321 */
352 /* 322 */
353 /* 323 */
354 /* 324 */
355 /* 325 */
356 /* 326 */
357 /* 327 */
358 /* 328 */
359 /* 329 */
360 /* 330 */
361 /* 331 */
362 /* 332 */
363 /* 333 */
364 /* 334 */
365 /* 335 */
366 /* 336 */
367 /* 337 */
368 /* 338 */
369 /* 339 */
370 /* 340 */
371 /* 341 */
372 /* 342 */
373 /* 343 */
374 /* 344 */
375 /* 345 */
376 /* 346 */
377 /* 347 */
378 /* 348 */
379 /* 349 */
380 
381 #define TEGRA210_CLK_AUDIO0_MUX 350
382 #define TEGRA210_CLK_AUDIO1_MUX 351
383 #define TEGRA210_CLK_AUDIO2_MUX 352
384 #define TEGRA210_CLK_AUDIO3_MUX 353
385 #define TEGRA210_CLK_AUDIO4_MUX 354
386 #define TEGRA210_CLK_SPDIF_MUX 355
387 #define TEGRA210_CLK_CLK_OUT_1_MUX 356
388 #define TEGRA210_CLK_CLK_OUT_2_MUX 357
389 #define TEGRA210_CLK_CLK_OUT_3_MUX 358
390 #define TEGRA210_CLK_DSIA_MUX 359
391 #define TEGRA210_CLK_DSIB_MUX 360
392 #define TEGRA210_CLK_SOR0_LVDS 361
393 #define TEGRA210_CLK_XUSB_SS_DIV2 362
394 
395 #define TEGRA210_CLK_PLL_M_UD 363
396 #define TEGRA210_CLK_PLL_C_UD 364
397 #define TEGRA210_CLK_SCLK_MUX 365
398 
399 #define TEGRA210_CLK_CLK_MAX 366
400 
401 #endif	/* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
402