#
757db2da |
| 21-May-2018 |
John Garry <john.garry@huawei.com> |
scsi: hisi_sas: Introduce hisi_sas_phy_set_linkrate()
There is much common code and functionality between the HW versions to set the PHY linkrate.
As such, this patch factors out the common code in
scsi: hisi_sas: Introduce hisi_sas_phy_set_linkrate()
There is much common code and functionality between the HW versions to set the PHY linkrate.
As such, this patch factors out the common code into a generic function hisi_sas_phy_set_linkrate().
Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
e85d93b2 |
| 09-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: Use device lock to protect slot alloc/free
The IPTT of a slot is unique, and we currently use hisi_hba lock to protect it.
Now slot is managed on hisi_sas_device.list, so use DQ loc
scsi: hisi_sas: Use device lock to protect slot alloc/free
The IPTT of a slot is unique, and we currently use hisi_hba lock to protect it.
Now slot is managed on hisi_sas_device.list, so use DQ lock to protect for allocating and freeing the slot.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
fa222db0 |
| 09-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: Don't lock DQ for complete task sending
Currently we lock the DQ to protect whole delivery process. So this stops us building slots for the same queue in parallel, and can affect pe
scsi: hisi_sas: Don't lock DQ for complete task sending
Currently we lock the DQ to protect whole delivery process. So this stops us building slots for the same queue in parallel, and can affect performance.
To optimise it, only lock the DQ during special periods, specifically when allocating a slot from the DQ and when delivering a slot to the HW.
This approach is now safe, thanks to the previous patches to ensure that we always deliver a slot to the HW once allocated.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
a2b3820b |
| 09-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: make return type of prep functions void
Since the task prep functions now should not fail, adjust the return types to void.
In addition, some checks in the task prep functions are r
scsi: hisi_sas: make return type of prep functions void
Since the task prep functions now should not fail, adjust the return types to void.
In addition, some checks in the task prep functions are relocated to the main module; this is specifically the check for the number of elements in an sg list exceeded the HW SGE limit.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
7eee4b92 |
| 09-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: relocate smp sg map
Currently we use DQ lock to protect delivery of DQ entry one by one.
To optimise to allow more than one slot to be built for a single DQ in parallel, we need to
scsi: hisi_sas: relocate smp sg map
Currently we use DQ lock to protect delivery of DQ entry one by one.
To optimise to allow more than one slot to be built for a single DQ in parallel, we need to remove the DQ lock when preparing slots, prior to delivery.
To achieve this, we rearrange the slot build order to ensure that once we allocate a slot for a task, we do cannot fail to deliver the task.
In this patch, we rearrange the slot building for SMP tasks to ensure that sg mapping part (which can fail) happens before we allocate the slot in the DQ.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
f70c1251 |
| 02-May-2018 |
Xiaofei Tan <tanxiaofei@huawei.com> |
scsi: hisi_sas: workaround a v3 hw hilink bug
There is an SoC bug of v3 hw development version. When hot- unplugging a directly attached disk, the PHY down interrupt may not happen. It is very easy
scsi: hisi_sas: workaround a v3 hw hilink bug
There is an SoC bug of v3 hw development version. When hot- unplugging a directly attached disk, the PHY down interrupt may not happen. It is very easy to appear on some boards.
When this issue occurs, the controller will receive many invalid dword frames, and the "alos" fields of register HILINK_ERR_DFX can indicate that disk was unplugged.
As an workaround solution, this patch detects this issue in the channel interrupt, and workaround it by following steps:
- Disable the PHY - Clear error code and interrupt - Enable the PHY
Then the HW will reissue PHY down interrupt.
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
9b8addf3 |
| 02-May-2018 |
John Garry <john.garry@huawei.com> |
scsi: hisi_sas: add readl poll timeout helper wrappers
It is common to use readl poll timeout helpers in the driver, so create custom wrappers.
Signed-off-by: John Garry <john.garry@huawei.com> Sig
scsi: hisi_sas: add readl poll timeout helper wrappers
It is common to use readl poll timeout helpers in the driver, so create custom wrappers.
Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
bf081d5d |
| 02-May-2018 |
Xiaofei Tan <tanxiaofei@huawei.com> |
scsi: hisi_sas: remove redundant handling to event95 for v3
Event95 is used for DFX purpose. The relevant bit for this interrupt in the ENT_INT_SRC_MSK3 register has been disabled, so remove the pro
scsi: hisi_sas: remove redundant handling to event95 for v3
Event95 is used for DFX purpose. The relevant bit for this interrupt in the ENT_INT_SRC_MSK3 register has been disabled, so remove the processing.
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
94135327 |
| 02-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: config ATA de-reset as an constrained command for v3 hw
As a unconstrained command, a command can be sent to SATA disk even if SATA disk status is BUSY, ERR or DRQ.
If an ATA reset
scsi: hisi_sas: config ATA de-reset as an constrained command for v3 hw
As a unconstrained command, a command can be sent to SATA disk even if SATA disk status is BUSY, ERR or DRQ.
If an ATA reset assert is successful but ATA reset de-assert fails, then it will retry the reset de-assert. If reset de- assert retry is successful, we think it is okay to probe the device but actually it still has Err status.
Apparently we need to retry the ATA reset assertion and de- assertion instead for this mentioned scenario.
As such, we config ATA reset assert as a constrained command, if ATA reset de-assert fails, then ATA reset de-assert retry will also fail. Then we will retry the proper process of ATA reset assert and de-assert again.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
c2c1d9de |
| 02-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: update PHY linkrate after a controller reset
After the controller is reset, we currently may not honour the PHY max linkrate set via sysfs, in that after a reset we always revert to
scsi: hisi_sas: update PHY linkrate after a controller reset
After the controller is reset, we currently may not honour the PHY max linkrate set via sysfs, in that after a reset we always revert to max linkrate of 12Gbps, ignoring the value set via sysfs.
This patch modifies to policy to set the programmed PHY linkrate, honouring the max linkrate programmed via sysfs.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
cd938e53 |
| 02-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: check host frozen before calling "done" function
When the host is frozen in SCSI EH state, at any point after the LLDD sets SAS_TASK_STATE_DONE for the sas_task task state, libsas ma
scsi: hisi_sas: check host frozen before calling "done" function
When the host is frozen in SCSI EH state, at any point after the LLDD sets SAS_TASK_STATE_DONE for the sas_task task state, libsas may free the task; see sas_scsi_find_task().
This puts the LLDD in a difficult position, in that once it sets SAS_TASK_STATE_DONE for the task state it should not reference the sas_task again. But the LLDD needs will check the sas_task indirectly in calling task->task_done()->sas_scsi_task_done() or sas_ata_task_done() (to check if the host is frozen state actually).
And the LLDD cannot set SAS_TASK_STATE_DONE for the task state after task->task_done() is called (as the sas_task is free'd at this point).
This situation would seem to be a problem made by libsas.
To work around, check in the LLDD whether the host is in frozen state to ensure it is ok to call task->task_done() function. If in the frozen state, we rely on SCSI EH and libsas to free the sas_task directly.
We do not do this for the following IO types:
- SMP - they are managed in libsas directly, outside SCSI EH - Any internally originated IO, for similar reason
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
b81b6cce |
| 02-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: Add some checks to avoid free'ing a sas_task twice
If the SCSI host enters EH, any pending IO will be processed by SCSI EH. However it is possible that SCSI EH will try to abort the
scsi: hisi_sas: Add some checks to avoid free'ing a sas_task twice
If the SCSI host enters EH, any pending IO will be processed by SCSI EH. However it is possible that SCSI EH will try to abort the IO and also at the same time the IO completes in the driver. In this situation there is a small chance of freeing the sas_task twice.
Then if another IO re-uses freed sas_task before the second time of free'ing sas_task, it is possible to free incorrect sas_task.
To avoid this situation, add some checks to increase reliability. The sas_task task state flag SAS_TASK_STATE_ABORTED is used to mutually protect the LLDD and libsas freeing the task.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
24cf4361 |
| 02-May-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: optimise the usage of DQ locking
In the DQ tasklet processing it is not necessary to take the DQ lock, as there is no contention between adding slots to the CQ and removing slots fro
scsi: hisi_sas: optimise the usage of DQ locking
In the DQ tasklet processing it is not necessary to take the DQ lock, as there is no contention between adding slots to the CQ and removing slots from the matching DQ.
In addition, since we run each DQ in a separate tasklet context, there would be no possible contention between DQ processing running for the same queue in parallel.
It is still necessary to take hisi_hba lock when free'ing slots.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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Revision tags: v4.16 |
|
#
c90a0bea |
| 23-Mar-2018 |
John Garry <john.garry@huawei.com> |
scsi: hisi_sas: remove some unneeded structure members
This patch removes unneeded structure elements:
- hisi_sas_phy.dev_sas_addr: only ever written - Also remove associated function which writes
scsi: hisi_sas: remove some unneeded structure members
This patch removes unneeded structure elements:
- hisi_sas_phy.dev_sas_addr: only ever written - Also remove associated function which writes it, hisi_sas_init_add().
- hisi_sas_device.attached_phy: only ever written - Also remove code to set it in hisi_sas_dev_found()
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
381ed6c0 |
| 23-Mar-2018 |
John Garry <john.garry@huawei.com> |
scsi: hisi_sas: print device id for errors
When we find an erroneous slot completion, to help aid debugging add the device index to the current debug log.
Signed-off-by: John Garry <john.garry@huaw
scsi: hisi_sas: print device id for errors
When we find an erroneous slot completion, to help aid debugging add the device index to the current debug log.
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
327f242f |
| 23-Mar-2018 |
Xiaofei Tan <tanxiaofei@huawei.com> |
scsi: hisi_sas: check IPTT is valid before using it for v3 hw
There is a bug of v3 hw development version. When AXI error happen, hw may return an abnormal CQ that IPTT value is 0xffff. This will c
scsi: hisi_sas: check IPTT is valid before using it for v3 hw
There is a bug of v3 hw development version. When AXI error happen, hw may return an abnormal CQ that IPTT value is 0xffff. This will cause IPTT out-of-bounds reference.
This patch adds a check of IPTT in cq_tasklet_v3_hw() and discards invalid slot. This workaround scheme is just to enhance fault-tolerance of the driver. So, we will apply this scheme for all version of v3 hw, although release version has fixed this SoC bug.
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
5df41af4 |
| 23-Mar-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: delete timer when removing hisi_sas driver
Delete timer for v1 and v3 hw when removing hisi_sas driver.
Signed-off-by: Xiang chen <chenxiang66@hisilicon.com> Signed-off-by: John Gar
scsi: hisi_sas: delete timer when removing hisi_sas driver
Delete timer for v1 and v3 hw when removing hisi_sas driver.
Signed-off-by: Xiang chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
61573630 |
| 23-Mar-2018 |
Xiaofei Tan <tanxiaofei@huawei.com> |
scsi: hisi_sas: update RAS feature for later revision of v3 HW
There is an modification for later revision of v3 hw. More HW errors are reported through RAS interrupt. These errors were originally r
scsi: hisi_sas: update RAS feature for later revision of v3 HW
There is an modification for later revision of v3 hw. More HW errors are reported through RAS interrupt. These errors were originally reported only through MSI.
When report to RAS, some combinations are done to port AXI errors and FIFO OMIT errors. For example, each port has 4 AXI errors, and they are combined to one when report to RAS.
This patch does two things:
1. Enable RAS interrupt of these errors and handle them in PCI error handlers.
2. Disable MSI interrupts of these errors for this later revision hw.
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
40ec66b1 |
| 07-Mar-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: add v3 hw MODULE_DEVICE_TABLE()
Export device table of v3 hw to userspace, or auto probe will fail for v3 hw.
Also change the module alias to include "pci", instead of "platform".
scsi: hisi_sas: add v3 hw MODULE_DEVICE_TABLE()
Export device table of v3 hw to userspace, or auto probe will fail for v3 hw.
Also change the module alias to include "pci", instead of "platform".
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
15c38e31 |
| 07-Mar-2018 |
Xiaofei Tan <tanxiaofei@huawei.com> |
scsi: hisi_sas: modify some register config for hip08
Do some modifications for register configuring for hip08.
In future, to reduce kernel churn with patches to modify registers, any registers whi
scsi: hisi_sas: modify some register config for hip08
Do some modifications for register configuring for hip08.
In future, to reduce kernel churn with patches to modify registers, any registers which may change between board models (mostly PHY/SERDES related) should be set in ACPI reset handler.
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
edafeef4 |
| 07-Mar-2018 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: Code cleanup and minor bug fixes
The patch does some code cleanup and fixes some small bugs:
- Correct return status of phy_up_v3_hw() and phy_bcast_v3_hw() - Add static for functio
scsi: hisi_sas: Code cleanup and minor bug fixes
The patch does some code cleanup and fixes some small bugs:
- Correct return status of phy_up_v3_hw() and phy_bcast_v3_hw() - Add static for function phy_get_max_linkrate_v3_hw() - Change exception return status when no reset method - Change magic value to ts->stat in slot_complete_vx_hw() - Remove unnecessary check for dev_is_sata() - Fix some issues of alignment and indents (Authored by Xiaofei Tan in another patch, but added here to be practical)
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
0006ce29 |
| 07-Mar-2018 |
Xiaofei Tan <tanxiaofei@huawei.com> |
scsi: hisi_sas: fix the issue of setting linkrate register
It is not right to set the register PROG_PHY_LINK_RATE while PHY is still enabled. So if we want to change PHY linkrate, we need to disable
scsi: hisi_sas: fix the issue of setting linkrate register
It is not right to set the register PROG_PHY_LINK_RATE while PHY is still enabled. So if we want to change PHY linkrate, we need to disable PHY before setting the register PROG_PHY_LINK_RATE, and then start-up PHY. This patch is to fix this issue.
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
eba8c20c |
| 07-Mar-2018 |
Xiaofei Tan <tanxiaofei@huawei.com> |
scsi: hisi_sas: fix the issue of link rate inconsistency
In sysfs, there are two files about minimum linkrate, and also two files for maximum linkrate. Take maximum linkrate example, maximum_linkrat
scsi: hisi_sas: fix the issue of link rate inconsistency
In sysfs, there are two files about minimum linkrate, and also two files for maximum linkrate. Take maximum linkrate example, maximum_linkrate_hw is read-only and indicated by the register HARD_PHY_LINKRATE, and maximum_linkrate is read-write and corresponding to the register PROG_PHY_LINK_RATE.
But in the function phy_up_v*_hw(), we get *_linkrate value from HARD_PHY_LINKRATE. It is not right. This patch is to fix this issue.
Unreferenced PHY-interrupt enum is also removed for v3 hw.
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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Revision tags: v4.15 |
|
#
468f4b8d |
| 28-Dec-2017 |
chenxiang <chenxiang66@hisilicon.com> |
scsi: hisi_sas: Change frame type for SET MAX commands
According to ATA protocol, SET MAX commands belong to different frame types. So judge features field of SET MAX commands to decide which frame
scsi: hisi_sas: Change frame type for SET MAX commands
According to ATA protocol, SET MAX commands belong to different frame types. So judge features field of SET MAX commands to decide which frame type they belongs to.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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#
4d0951ee |
| 08-Dec-2017 |
Xiang Chen <chenxiang66@hisilicon.com> |
scsi: hisi_sas: add v3 hw suspend and resume
For v3 hw SAS, it supports configuring power state from D0 to D3 for entering Low Power status and power state from D3 to D0 for quit Low Power status.
scsi: hisi_sas: add v3 hw suspend and resume
For v3 hw SAS, it supports configuring power state from D0 to D3 for entering Low Power status and power state from D3 to D0 for quit Low Power status.
When power state from D0 to D3, HW will send FLR to clear the registers of ECAM and BAR space, and when power state from D3 to D0, it will clear the registers of ECAM space only.
So when suspend, need to do like controller reset (including disable interrupts/DQ/PHY/BUS), and also release slots after FLR. When resume, re-config the registers of BAR space.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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