1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CFG_AGING_TIME 0xbc 46 #define HGC_DFX_CFG2 0xc0 47 #define CFG_ABT_SET_QUERY_IPTT 0xd4 48 #define CFG_SET_ABORTED_IPTT_OFF 0 49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 50 #define CFG_SET_ABORTED_EN_OFF 12 51 #define CFG_ABT_SET_IPTT_DONE 0xd8 52 #define CFG_ABT_SET_IPTT_DONE_OFF 0 53 #define HGC_IOMB_PROC1_STATUS 0x104 54 #define CFG_1US_TIMER_TRSH 0xcc 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 97 #define DLVRY_Q_0_DEPTH 0x268 98 #define DLVRY_Q_0_WR_PTR 0x26c 99 #define DLVRY_Q_0_RD_PTR 0x270 100 #define HYPER_STREAM_ID_EN_CFG 0xc80 101 #define OQ0_INT_SRC_MSK 0xc90 102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 104 #define COMPL_Q_0_DEPTH 0x4e8 105 #define COMPL_Q_0_WR_PTR 0x4ec 106 #define COMPL_Q_0_RD_PTR 0x4f0 107 #define AWQOS_AWCACHE_CFG 0xc84 108 #define ARQOS_ARCACHE_CFG 0xc88 109 #define HILINK_ERR_DFX 0xe04 110 111 /* phy registers requiring init */ 112 #define PORT_BASE (0x2000) 113 #define PHY_CFG (PORT_BASE + 0x0) 114 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 115 #define PHY_CFG_ENA_OFF 0 116 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 117 #define PHY_CFG_DC_OPT_OFF 2 118 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 119 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 120 #define PHY_CTRL (PORT_BASE + 0x14) 121 #define PHY_CTRL_RESET_OFF 0 122 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 123 #define SL_CFG (PORT_BASE + 0x84) 124 #define SL_CONTROL (PORT_BASE + 0x94) 125 #define SL_CONTROL_NOTIFY_EN_OFF 0 126 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 127 #define SL_CTA_OFF 17 128 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 129 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 130 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 131 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 132 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 133 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 134 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 135 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 136 #define TXID_AUTO (PORT_BASE + 0xb8) 137 #define CT3_OFF 1 138 #define CT3_MSK (0x1 << CT3_OFF) 139 #define TX_HARDRST_OFF 2 140 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 141 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 142 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 143 #define STP_LINK_TIMER (PORT_BASE + 0x120) 144 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 145 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 146 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 147 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 148 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 149 #define CHL_INT0 (PORT_BASE + 0x1b4) 150 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 151 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 152 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 153 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 154 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 155 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 156 #define CHL_INT0_NOT_RDY_OFF 4 157 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 158 #define CHL_INT0_PHY_RDY_OFF 5 159 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 160 #define CHL_INT1 (PORT_BASE + 0x1b8) 161 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 162 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 163 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 164 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 165 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 166 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 167 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 168 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 169 #define CHL_INT2 (PORT_BASE + 0x1bc) 170 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 171 #define CHL_INT2_RX_INVLD_DW_OFF 30 172 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 173 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 174 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 175 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 176 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 177 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 178 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 179 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 180 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 181 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 182 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 183 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 184 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 185 #define DMA_TX_STATUS_BUSY_OFF 0 186 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 187 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 188 #define DMA_RX_STATUS_BUSY_OFF 0 189 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 190 191 #define COARSETUNE_TIME (PORT_BASE + 0x304) 192 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 193 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 194 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 195 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 196 197 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 198 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 199 #error Max ITCT exceeded 200 #endif 201 202 #define AXI_MASTER_CFG_BASE (0x5000) 203 #define AM_CTRL_GLOBAL (0x0) 204 #define AM_CURR_TRANS_RETURN (0x150) 205 206 #define AM_CFG_MAX_TRANS (0x5010) 207 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 208 #define AXI_CFG (0x5100) 209 #define AM_ROB_ECC_ERR_ADDR (0x510c) 210 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 211 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 212 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 213 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 214 215 /* RAS registers need init */ 216 #define RAS_BASE (0x6000) 217 #define SAS_RAS_INTR0 (RAS_BASE) 218 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 219 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 220 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 221 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 222 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 223 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 224 225 /* HW dma structures */ 226 /* Delivery queue header */ 227 /* dw0 */ 228 #define CMD_HDR_ABORT_FLAG_OFF 0 229 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 230 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 231 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 232 #define CMD_HDR_RESP_REPORT_OFF 5 233 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 234 #define CMD_HDR_TLR_CTRL_OFF 6 235 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 236 #define CMD_HDR_PORT_OFF 18 237 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 238 #define CMD_HDR_PRIORITY_OFF 27 239 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 240 #define CMD_HDR_CMD_OFF 29 241 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 242 /* dw1 */ 243 #define CMD_HDR_UNCON_CMD_OFF 3 244 #define CMD_HDR_DIR_OFF 5 245 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 246 #define CMD_HDR_RESET_OFF 7 247 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 248 #define CMD_HDR_VDTL_OFF 10 249 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 250 #define CMD_HDR_FRAME_TYPE_OFF 11 251 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 252 #define CMD_HDR_DEV_ID_OFF 16 253 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 254 /* dw2 */ 255 #define CMD_HDR_CFL_OFF 0 256 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 257 #define CMD_HDR_NCQ_TAG_OFF 10 258 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 259 #define CMD_HDR_MRFL_OFF 15 260 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 261 #define CMD_HDR_SG_MOD_OFF 24 262 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 263 /* dw3 */ 264 #define CMD_HDR_IPTT_OFF 0 265 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 266 /* dw6 */ 267 #define CMD_HDR_DIF_SGL_LEN_OFF 0 268 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 269 #define CMD_HDR_DATA_SGL_LEN_OFF 16 270 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 271 /* dw7 */ 272 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 273 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 274 #define CMD_HDR_ABORT_IPTT_OFF 16 275 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 276 277 /* Completion header */ 278 /* dw0 */ 279 #define CMPLT_HDR_CMPLT_OFF 0 280 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 281 #define CMPLT_HDR_ERROR_PHASE_OFF 2 282 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 283 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 284 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 285 #define CMPLT_HDR_ERX_OFF 12 286 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 287 #define CMPLT_HDR_ABORT_STAT_OFF 13 288 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 289 /* abort_stat */ 290 #define STAT_IO_NOT_VALID 0x1 291 #define STAT_IO_NO_DEVICE 0x2 292 #define STAT_IO_COMPLETE 0x3 293 #define STAT_IO_ABORTED 0x4 294 /* dw1 */ 295 #define CMPLT_HDR_IPTT_OFF 0 296 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 297 #define CMPLT_HDR_DEV_ID_OFF 16 298 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 299 /* dw3 */ 300 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 301 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 302 303 /* ITCT header */ 304 /* qw0 */ 305 #define ITCT_HDR_DEV_TYPE_OFF 0 306 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 307 #define ITCT_HDR_VALID_OFF 2 308 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 309 #define ITCT_HDR_MCR_OFF 5 310 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 311 #define ITCT_HDR_VLN_OFF 9 312 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 313 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 314 #define ITCT_HDR_AWT_CONTINUE_OFF 25 315 #define ITCT_HDR_PORT_ID_OFF 28 316 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 317 /* qw2 */ 318 #define ITCT_HDR_INLT_OFF 0 319 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 320 #define ITCT_HDR_RTOLT_OFF 48 321 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 322 323 struct hisi_sas_complete_v3_hdr { 324 __le32 dw0; 325 __le32 dw1; 326 __le32 act; 327 __le32 dw3; 328 }; 329 330 struct hisi_sas_err_record_v3 { 331 /* dw0 */ 332 __le32 trans_tx_fail_type; 333 334 /* dw1 */ 335 __le32 trans_rx_fail_type; 336 337 /* dw2 */ 338 __le16 dma_tx_err_type; 339 __le16 sipc_rx_err_type; 340 341 /* dw3 */ 342 __le32 dma_rx_err_type; 343 }; 344 345 #define RX_DATA_LEN_UNDERFLOW_OFF 6 346 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 347 348 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 349 #define HISI_SAS_MSI_COUNT_V3_HW 32 350 351 #define DIR_NO_DATA 0 352 #define DIR_TO_INI 1 353 #define DIR_TO_DEVICE 2 354 #define DIR_RESERVED 3 355 356 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 357 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 358 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 359 ((fis.command == ATA_CMD_DEV_RESET) && \ 360 ((fis.control & ATA_SRST) != 0))) 361 362 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 363 { 364 void __iomem *regs = hisi_hba->regs + off; 365 366 return readl(regs); 367 } 368 369 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 370 { 371 void __iomem *regs = hisi_hba->regs + off; 372 373 return readl_relaxed(regs); 374 } 375 376 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 377 { 378 void __iomem *regs = hisi_hba->regs + off; 379 380 writel(val, regs); 381 } 382 383 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 384 u32 off, u32 val) 385 { 386 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 387 388 writel(val, regs); 389 } 390 391 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 392 int phy_no, u32 off) 393 { 394 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 395 396 return readl(regs); 397 } 398 399 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 400 timeout_us) \ 401 ({ \ 402 void __iomem *regs = hisi_hba->regs + off; \ 403 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 404 }) 405 406 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 407 timeout_us) \ 408 ({ \ 409 void __iomem *regs = hisi_hba->regs + off; \ 410 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 411 }) 412 413 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 414 { 415 struct pci_dev *pdev = hisi_hba->pci_dev; 416 int i; 417 418 /* Global registers init */ 419 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 420 (u32)((1ULL << hisi_hba->queue_count) - 1)); 421 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 422 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 423 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd); 424 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 425 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 426 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 427 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 428 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 429 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 430 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 431 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 432 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 433 if (pdev->revision >= 0x21) 434 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff); 435 else 436 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 437 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 438 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 439 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 440 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 441 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 442 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 443 for (i = 0; i < hisi_hba->queue_count; i++) 444 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 445 446 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 447 448 for (i = 0; i < hisi_hba->n_phy; i++) { 449 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 450 struct asd_sas_phy *sas_phy = &phy->sas_phy; 451 u32 prog_phy_link_rate = 0x800; 452 453 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 454 SAS_LINK_RATE_1_5_GBPS)) { 455 prog_phy_link_rate = 0x855; 456 } else { 457 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 458 459 prog_phy_link_rate = 460 hisi_sas_get_prog_phy_linkrate_mask(max) | 461 0x800; 462 } 463 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 464 prog_phy_link_rate); 465 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 466 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 467 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 468 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 469 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 470 if (pdev->revision >= 0x21) 471 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 472 0xffffffff); 473 else 474 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 475 0xff87ffff); 476 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 477 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 478 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 479 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 480 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 481 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 482 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 483 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 484 485 /* used for 12G negotiate */ 486 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 487 } 488 489 for (i = 0; i < hisi_hba->queue_count; i++) { 490 /* Delivery queue */ 491 hisi_sas_write32(hisi_hba, 492 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 493 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 494 495 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 496 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 497 498 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 499 HISI_SAS_QUEUE_SLOTS); 500 501 /* Completion queue */ 502 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 503 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 504 505 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 506 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 507 508 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 509 HISI_SAS_QUEUE_SLOTS); 510 } 511 512 /* itct */ 513 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 514 lower_32_bits(hisi_hba->itct_dma)); 515 516 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 517 upper_32_bits(hisi_hba->itct_dma)); 518 519 /* iost */ 520 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 521 lower_32_bits(hisi_hba->iost_dma)); 522 523 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 524 upper_32_bits(hisi_hba->iost_dma)); 525 526 /* breakpoint */ 527 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 528 lower_32_bits(hisi_hba->breakpoint_dma)); 529 530 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 531 upper_32_bits(hisi_hba->breakpoint_dma)); 532 533 /* SATA broken msg */ 534 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 535 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 536 537 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 538 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 539 540 /* SATA initial fis */ 541 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 542 lower_32_bits(hisi_hba->initial_fis_dma)); 543 544 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 545 upper_32_bits(hisi_hba->initial_fis_dma)); 546 547 /* RAS registers init */ 548 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 549 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 550 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 551 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 552 } 553 554 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 555 { 556 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 557 558 cfg &= ~PHY_CFG_DC_OPT_MSK; 559 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 560 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 561 } 562 563 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 564 { 565 struct sas_identify_frame identify_frame; 566 u32 *identify_buffer; 567 568 memset(&identify_frame, 0, sizeof(identify_frame)); 569 identify_frame.dev_type = SAS_END_DEVICE; 570 identify_frame.frame_type = 0; 571 identify_frame._un1 = 1; 572 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 573 identify_frame.target_bits = SAS_PROTOCOL_NONE; 574 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 575 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 576 identify_frame.phy_id = phy_no; 577 identify_buffer = (u32 *)(&identify_frame); 578 579 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 580 __swab32(identify_buffer[0])); 581 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 582 __swab32(identify_buffer[1])); 583 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 584 __swab32(identify_buffer[2])); 585 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 586 __swab32(identify_buffer[3])); 587 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 588 __swab32(identify_buffer[4])); 589 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 590 __swab32(identify_buffer[5])); 591 } 592 593 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 594 struct hisi_sas_device *sas_dev) 595 { 596 struct domain_device *device = sas_dev->sas_device; 597 struct device *dev = hisi_hba->dev; 598 u64 qw0, device_id = sas_dev->device_id; 599 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 600 struct domain_device *parent_dev = device->parent; 601 struct asd_sas_port *sas_port = device->port; 602 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 603 604 memset(itct, 0, sizeof(*itct)); 605 606 /* qw0 */ 607 qw0 = 0; 608 switch (sas_dev->dev_type) { 609 case SAS_END_DEVICE: 610 case SAS_EDGE_EXPANDER_DEVICE: 611 case SAS_FANOUT_EXPANDER_DEVICE: 612 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 613 break; 614 case SAS_SATA_DEV: 615 case SAS_SATA_PENDING: 616 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 617 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 618 else 619 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 620 break; 621 default: 622 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 623 sas_dev->dev_type); 624 } 625 626 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 627 (device->linkrate << ITCT_HDR_MCR_OFF) | 628 (1 << ITCT_HDR_VLN_OFF) | 629 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 630 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 631 (port->id << ITCT_HDR_PORT_ID_OFF)); 632 itct->qw0 = cpu_to_le64(qw0); 633 634 /* qw1 */ 635 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 636 itct->sas_addr = __swab64(itct->sas_addr); 637 638 /* qw2 */ 639 if (!dev_is_sata(device)) 640 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 641 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 642 } 643 644 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 645 struct hisi_sas_device *sas_dev) 646 { 647 DECLARE_COMPLETION_ONSTACK(completion); 648 u64 dev_id = sas_dev->device_id; 649 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 650 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 651 652 sas_dev->completion = &completion; 653 654 /* clear the itct interrupt state */ 655 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 656 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 657 ENT_INT_SRC3_ITC_INT_MSK); 658 659 /* clear the itct table*/ 660 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 661 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 662 663 wait_for_completion(sas_dev->completion); 664 memset(itct, 0, sizeof(struct hisi_sas_itct)); 665 } 666 667 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 668 struct domain_device *device) 669 { 670 struct hisi_sas_slot *slot, *slot2; 671 struct hisi_sas_device *sas_dev = device->lldd_dev; 672 u32 cfg_abt_set_query_iptt; 673 674 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 675 CFG_ABT_SET_QUERY_IPTT); 676 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 677 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 678 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 679 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 680 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 681 cfg_abt_set_query_iptt); 682 } 683 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 684 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 685 cfg_abt_set_query_iptt); 686 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 687 1 << CFG_ABT_SET_IPTT_DONE_OFF); 688 } 689 690 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 691 { 692 struct device *dev = hisi_hba->dev; 693 int ret; 694 u32 val; 695 696 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 697 698 /* Disable all of the PHYs */ 699 hisi_sas_stop_phys(hisi_hba); 700 udelay(50); 701 702 /* Ensure axi bus idle */ 703 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 704 20000, 1000000); 705 if (ret) { 706 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 707 return -EIO; 708 } 709 710 if (ACPI_HANDLE(dev)) { 711 acpi_status s; 712 713 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 714 if (ACPI_FAILURE(s)) { 715 dev_err(dev, "Reset failed\n"); 716 return -EIO; 717 } 718 } else { 719 dev_err(dev, "no reset method!\n"); 720 return -EINVAL; 721 } 722 723 return 0; 724 } 725 726 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 727 { 728 struct device *dev = hisi_hba->dev; 729 int rc; 730 731 rc = reset_hw_v3_hw(hisi_hba); 732 if (rc) { 733 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 734 return rc; 735 } 736 737 msleep(100); 738 init_reg_v3_hw(hisi_hba); 739 740 return 0; 741 } 742 743 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 744 { 745 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 746 747 cfg |= PHY_CFG_ENA_MSK; 748 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 749 } 750 751 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 752 { 753 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 754 755 cfg &= ~PHY_CFG_ENA_MSK; 756 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 757 } 758 759 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 760 { 761 config_id_frame_v3_hw(hisi_hba, phy_no); 762 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 763 enable_phy_v3_hw(hisi_hba, phy_no); 764 } 765 766 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 767 { 768 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 769 u32 txid_auto; 770 771 disable_phy_v3_hw(hisi_hba, phy_no); 772 if (phy->identify.device_type == SAS_END_DEVICE) { 773 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 774 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 775 txid_auto | TX_HARDRST_MSK); 776 } 777 msleep(100); 778 start_phy_v3_hw(hisi_hba, phy_no); 779 } 780 781 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 782 { 783 return SAS_LINK_RATE_12_0_GBPS; 784 } 785 786 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 787 { 788 int i; 789 790 for (i = 0; i < hisi_hba->n_phy; i++) { 791 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 792 struct asd_sas_phy *sas_phy = &phy->sas_phy; 793 794 if (!sas_phy->phy->enabled) 795 continue; 796 797 start_phy_v3_hw(hisi_hba, i); 798 } 799 } 800 801 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 802 { 803 u32 sl_control; 804 805 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 806 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 807 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 808 msleep(1); 809 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 810 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 811 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 812 } 813 814 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 815 { 816 int i, bitmap = 0; 817 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 818 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 819 820 for (i = 0; i < hisi_hba->n_phy; i++) 821 if (phy_state & BIT(i)) 822 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 823 bitmap |= BIT(i); 824 825 return bitmap; 826 } 827 828 /** 829 * The callpath to this function and upto writing the write 830 * queue pointer should be safe from interruption. 831 */ 832 static int 833 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 834 { 835 struct device *dev = hisi_hba->dev; 836 int queue = dq->id; 837 u32 r, w; 838 839 w = dq->wr_point; 840 r = hisi_sas_read32_relaxed(hisi_hba, 841 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 842 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 843 dev_warn(dev, "full queue=%d r=%d w=%d\n\n", 844 queue, r, w); 845 return -EAGAIN; 846 } 847 848 return 0; 849 } 850 851 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 852 { 853 struct hisi_hba *hisi_hba = dq->hisi_hba; 854 int dlvry_queue = dq->slot_prep->dlvry_queue; 855 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; 856 857 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; 858 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), 859 dq->wr_point); 860 } 861 862 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 863 struct hisi_sas_slot *slot, 864 struct hisi_sas_cmd_hdr *hdr, 865 struct scatterlist *scatter, 866 int n_elem) 867 { 868 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 869 struct scatterlist *sg; 870 int i; 871 872 for_each_sg(scatter, sg, n_elem, i) { 873 struct hisi_sas_sge *entry = &sge_page->sge[i]; 874 875 entry->addr = cpu_to_le64(sg_dma_address(sg)); 876 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 877 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 878 entry->data_off = 0; 879 } 880 881 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 882 883 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 884 } 885 886 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 887 struct hisi_sas_slot *slot, int is_tmf, 888 struct hisi_sas_tmf_task *tmf) 889 { 890 struct sas_task *task = slot->task; 891 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 892 struct domain_device *device = task->dev; 893 struct hisi_sas_device *sas_dev = device->lldd_dev; 894 struct hisi_sas_port *port = slot->port; 895 struct sas_ssp_task *ssp_task = &task->ssp_task; 896 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 897 int has_data = 0, priority = is_tmf; 898 u8 *buf_cmd; 899 u32 dw1 = 0, dw2 = 0; 900 901 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 902 (2 << CMD_HDR_TLR_CTRL_OFF) | 903 (port->id << CMD_HDR_PORT_OFF) | 904 (priority << CMD_HDR_PRIORITY_OFF) | 905 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 906 907 dw1 = 1 << CMD_HDR_VDTL_OFF; 908 if (is_tmf) { 909 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 910 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 911 } else { 912 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 913 switch (scsi_cmnd->sc_data_direction) { 914 case DMA_TO_DEVICE: 915 has_data = 1; 916 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 917 break; 918 case DMA_FROM_DEVICE: 919 has_data = 1; 920 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 921 break; 922 default: 923 dw1 &= ~CMD_HDR_DIR_MSK; 924 } 925 } 926 927 /* map itct entry */ 928 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 929 hdr->dw1 = cpu_to_le32(dw1); 930 931 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 932 + 3) / 4) << CMD_HDR_CFL_OFF) | 933 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 934 (2 << CMD_HDR_SG_MOD_OFF); 935 hdr->dw2 = cpu_to_le32(dw2); 936 hdr->transfer_tags = cpu_to_le32(slot->idx); 937 938 if (has_data) 939 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 940 slot->n_elem); 941 942 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 943 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 944 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 945 946 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 947 sizeof(struct ssp_frame_hdr); 948 949 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 950 if (!is_tmf) { 951 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 952 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 953 } else { 954 buf_cmd[10] = tmf->tmf; 955 switch (tmf->tmf) { 956 case TMF_ABORT_TASK: 957 case TMF_QUERY_TASK: 958 buf_cmd[12] = 959 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 960 buf_cmd[13] = 961 tmf->tag_of_task_to_be_managed & 0xff; 962 break; 963 default: 964 break; 965 } 966 } 967 } 968 969 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 970 struct hisi_sas_slot *slot) 971 { 972 struct sas_task *task = slot->task; 973 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 974 struct domain_device *device = task->dev; 975 struct hisi_sas_port *port = slot->port; 976 struct scatterlist *sg_req; 977 struct hisi_sas_device *sas_dev = device->lldd_dev; 978 dma_addr_t req_dma_addr; 979 unsigned int req_len; 980 981 /* req */ 982 sg_req = &task->smp_task.smp_req; 983 req_len = sg_dma_len(sg_req); 984 req_dma_addr = sg_dma_address(sg_req); 985 986 /* create header */ 987 /* dw0 */ 988 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 989 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 990 (2 << CMD_HDR_CMD_OFF)); /* smp */ 991 992 /* map itct entry */ 993 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 994 (1 << CMD_HDR_FRAME_TYPE_OFF) | 995 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 996 997 /* dw2 */ 998 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 999 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1000 CMD_HDR_MRFL_OFF)); 1001 1002 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1003 1004 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1005 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1006 1007 } 1008 1009 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1010 struct hisi_sas_slot *slot) 1011 { 1012 struct sas_task *task = slot->task; 1013 struct domain_device *device = task->dev; 1014 struct domain_device *parent_dev = device->parent; 1015 struct hisi_sas_device *sas_dev = device->lldd_dev; 1016 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1017 struct asd_sas_port *sas_port = device->port; 1018 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1019 u8 *buf_cmd; 1020 int has_data = 0, hdr_tag = 0; 1021 u32 dw1 = 0, dw2 = 0; 1022 1023 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1024 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1025 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1026 else 1027 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1028 1029 switch (task->data_dir) { 1030 case DMA_TO_DEVICE: 1031 has_data = 1; 1032 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1033 break; 1034 case DMA_FROM_DEVICE: 1035 has_data = 1; 1036 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1037 break; 1038 default: 1039 dw1 &= ~CMD_HDR_DIR_MSK; 1040 } 1041 1042 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1043 (task->ata_task.fis.control & ATA_SRST)) 1044 dw1 |= 1 << CMD_HDR_RESET_OFF; 1045 1046 dw1 |= (hisi_sas_get_ata_protocol( 1047 &task->ata_task.fis, task->data_dir)) 1048 << CMD_HDR_FRAME_TYPE_OFF; 1049 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1050 1051 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1052 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1053 1054 hdr->dw1 = cpu_to_le32(dw1); 1055 1056 /* dw2 */ 1057 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1058 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1059 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1060 } 1061 1062 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1063 2 << CMD_HDR_SG_MOD_OFF; 1064 hdr->dw2 = cpu_to_le32(dw2); 1065 1066 /* dw3 */ 1067 hdr->transfer_tags = cpu_to_le32(slot->idx); 1068 1069 if (has_data) 1070 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1071 slot->n_elem); 1072 1073 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1074 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1075 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1076 1077 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1078 1079 if (likely(!task->ata_task.device_control_reg_update)) 1080 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1081 /* fill in command FIS */ 1082 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1083 } 1084 1085 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1086 struct hisi_sas_slot *slot, 1087 int device_id, int abort_flag, int tag_to_abort) 1088 { 1089 struct sas_task *task = slot->task; 1090 struct domain_device *dev = task->dev; 1091 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1092 struct hisi_sas_port *port = slot->port; 1093 1094 /* dw0 */ 1095 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1096 (port->id << CMD_HDR_PORT_OFF) | 1097 (dev_is_sata(dev) 1098 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1099 (abort_flag 1100 << CMD_HDR_ABORT_FLAG_OFF)); 1101 1102 /* dw1 */ 1103 hdr->dw1 = cpu_to_le32(device_id 1104 << CMD_HDR_DEV_ID_OFF); 1105 1106 /* dw7 */ 1107 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1108 hdr->transfer_tags = cpu_to_le32(slot->idx); 1109 1110 } 1111 1112 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1113 { 1114 int i, res; 1115 u32 context, port_id, link_rate; 1116 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1117 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1118 struct device *dev = hisi_hba->dev; 1119 1120 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1121 1122 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1123 port_id = (port_id >> (4 * phy_no)) & 0xf; 1124 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1125 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1126 1127 if (port_id == 0xf) { 1128 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1129 res = IRQ_NONE; 1130 goto end; 1131 } 1132 sas_phy->linkrate = link_rate; 1133 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1134 1135 /* Check for SATA dev */ 1136 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1137 if (context & (1 << phy_no)) { 1138 struct hisi_sas_initial_fis *initial_fis; 1139 struct dev_to_host_fis *fis; 1140 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1141 1142 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1143 initial_fis = &hisi_hba->initial_fis[phy_no]; 1144 fis = &initial_fis->fis; 1145 sas_phy->oob_mode = SATA_OOB_MODE; 1146 attached_sas_addr[0] = 0x50; 1147 attached_sas_addr[7] = phy_no; 1148 memcpy(sas_phy->attached_sas_addr, 1149 attached_sas_addr, 1150 SAS_ADDR_SIZE); 1151 memcpy(sas_phy->frame_rcvd, fis, 1152 sizeof(struct dev_to_host_fis)); 1153 phy->phy_type |= PORT_TYPE_SATA; 1154 phy->identify.device_type = SAS_SATA_DEV; 1155 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1156 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1157 } else { 1158 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1159 struct sas_identify_frame *id = 1160 (struct sas_identify_frame *)frame_rcvd; 1161 1162 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1163 for (i = 0; i < 6; i++) { 1164 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1165 RX_IDAF_DWORD0 + (i * 4)); 1166 frame_rcvd[i] = __swab32(idaf); 1167 } 1168 sas_phy->oob_mode = SAS_OOB_MODE; 1169 memcpy(sas_phy->attached_sas_addr, 1170 &id->sas_addr, 1171 SAS_ADDR_SIZE); 1172 phy->phy_type |= PORT_TYPE_SAS; 1173 phy->identify.device_type = id->dev_type; 1174 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1175 if (phy->identify.device_type == SAS_END_DEVICE) 1176 phy->identify.target_port_protocols = 1177 SAS_PROTOCOL_SSP; 1178 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1179 phy->identify.target_port_protocols = 1180 SAS_PROTOCOL_SMP; 1181 } 1182 1183 phy->port_id = port_id; 1184 phy->phy_attached = 1; 1185 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1186 res = IRQ_HANDLED; 1187 end: 1188 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1189 CHL_INT0_SL_PHY_ENABLE_MSK); 1190 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1191 1192 return res; 1193 } 1194 1195 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1196 { 1197 u32 phy_state, sl_ctrl, txid_auto; 1198 struct device *dev = hisi_hba->dev; 1199 1200 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1201 1202 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1203 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1204 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1205 1206 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1207 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1208 sl_ctrl&(~SL_CTA_MSK)); 1209 1210 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1211 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1212 txid_auto | CT3_MSK); 1213 1214 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1215 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1216 1217 return IRQ_HANDLED; 1218 } 1219 1220 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1221 { 1222 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1223 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1224 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1225 1226 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1227 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1228 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1229 CHL_INT0_SL_RX_BCST_ACK_MSK); 1230 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1231 1232 return IRQ_HANDLED; 1233 } 1234 1235 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1236 { 1237 struct hisi_hba *hisi_hba = p; 1238 u32 irq_msk; 1239 int phy_no = 0; 1240 irqreturn_t res = IRQ_NONE; 1241 1242 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1243 & 0x11111111; 1244 while (irq_msk) { 1245 if (irq_msk & 1) { 1246 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1247 CHL_INT0); 1248 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1249 int rdy = phy_state & (1 << phy_no); 1250 1251 if (rdy) { 1252 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1253 /* phy up */ 1254 if (phy_up_v3_hw(phy_no, hisi_hba) 1255 == IRQ_HANDLED) 1256 res = IRQ_HANDLED; 1257 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1258 /* phy bcast */ 1259 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1260 == IRQ_HANDLED) 1261 res = IRQ_HANDLED; 1262 } else { 1263 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1264 /* phy down */ 1265 if (phy_down_v3_hw(phy_no, hisi_hba) 1266 == IRQ_HANDLED) 1267 res = IRQ_HANDLED; 1268 } 1269 } 1270 irq_msk >>= 4; 1271 phy_no++; 1272 } 1273 1274 return res; 1275 } 1276 1277 static const struct hisi_sas_hw_error port_axi_error[] = { 1278 { 1279 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1280 .msg = "dma_tx_axi_wr_err", 1281 }, 1282 { 1283 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1284 .msg = "dma_tx_axi_rd_err", 1285 }, 1286 { 1287 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1288 .msg = "dma_rx_axi_wr_err", 1289 }, 1290 { 1291 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1292 .msg = "dma_rx_axi_rd_err", 1293 }, 1294 }; 1295 1296 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1297 { 1298 struct hisi_hba *hisi_hba = p; 1299 struct device *dev = hisi_hba->dev; 1300 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1301 u32 irq_msk; 1302 int phy_no = 0; 1303 1304 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1305 & 0xeeeeeeee; 1306 1307 while (irq_msk) { 1308 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1309 CHL_INT0); 1310 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1311 CHL_INT1); 1312 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1313 CHL_INT2); 1314 u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1315 CHL_INT1_MSK); 1316 u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1317 CHL_INT2_MSK); 1318 1319 irq_value1 &= ~irq_msk1; 1320 irq_value2 &= ~irq_msk2; 1321 1322 if ((irq_msk & (4 << (phy_no * 4))) && 1323 irq_value1) { 1324 int i; 1325 1326 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1327 const struct hisi_sas_hw_error *error = 1328 &port_axi_error[i]; 1329 1330 if (!(irq_value1 & error->irq_msk)) 1331 continue; 1332 1333 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1334 error->msg, phy_no, irq_value1); 1335 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1336 } 1337 1338 hisi_sas_phy_write32(hisi_hba, phy_no, 1339 CHL_INT1, irq_value1); 1340 } 1341 1342 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) { 1343 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1344 1345 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1346 dev_warn(dev, "phy%d identify timeout\n", 1347 phy_no); 1348 hisi_sas_notify_phy_event(phy, 1349 HISI_PHYE_LINK_RESET); 1350 1351 } 1352 1353 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1354 u32 reg_value = hisi_sas_phy_read32(hisi_hba, 1355 phy_no, STP_LINK_TIMEOUT_STATE); 1356 1357 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1358 phy_no, reg_value); 1359 if (reg_value & BIT(4)) 1360 hisi_sas_notify_phy_event(phy, 1361 HISI_PHYE_LINK_RESET); 1362 } 1363 1364 hisi_sas_phy_write32(hisi_hba, phy_no, 1365 CHL_INT2, irq_value2); 1366 1367 if ((irq_value2 & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1368 (pci_dev->revision == 0x20)) { 1369 u32 reg_value; 1370 int rc; 1371 1372 rc = hisi_sas_read32_poll_timeout_atomic( 1373 HILINK_ERR_DFX, reg_value, 1374 !((reg_value >> 8) & BIT(phy_no)), 1375 1000, 10000); 1376 if (rc) { 1377 disable_phy_v3_hw(hisi_hba, phy_no); 1378 hisi_sas_phy_write32(hisi_hba, phy_no, 1379 CHL_INT2, 1380 BIT(CHL_INT2_RX_INVLD_DW_OFF)); 1381 hisi_sas_phy_read32(hisi_hba, phy_no, 1382 ERR_CNT_INVLD_DW); 1383 mdelay(1); 1384 enable_phy_v3_hw(hisi_hba, phy_no); 1385 } 1386 } 1387 } 1388 1389 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { 1390 hisi_sas_phy_write32(hisi_hba, phy_no, 1391 CHL_INT0, irq_value0 1392 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1393 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1394 & (~CHL_INT0_NOT_RDY_MSK)); 1395 } 1396 irq_msk &= ~(0xe << (phy_no * 4)); 1397 phy_no++; 1398 } 1399 1400 return IRQ_HANDLED; 1401 } 1402 1403 static const struct hisi_sas_hw_error axi_error[] = { 1404 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1405 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1406 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1407 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1408 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1409 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1410 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1411 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1412 {}, 1413 }; 1414 1415 static const struct hisi_sas_hw_error fifo_error[] = { 1416 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1417 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1418 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1419 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1420 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1421 {}, 1422 }; 1423 1424 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1425 { 1426 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1427 .msg = "write pointer and depth", 1428 }, 1429 { 1430 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1431 .msg = "iptt no match slot", 1432 }, 1433 { 1434 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1435 .msg = "read pointer and depth", 1436 }, 1437 { 1438 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1439 .reg = HGC_AXI_FIFO_ERR_INFO, 1440 .sub = axi_error, 1441 }, 1442 { 1443 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1444 .reg = HGC_AXI_FIFO_ERR_INFO, 1445 .sub = fifo_error, 1446 }, 1447 { 1448 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1449 .msg = "LM add/fetch list", 1450 }, 1451 { 1452 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1453 .msg = "SAS_HGC_ABT fetch LM list", 1454 }, 1455 }; 1456 1457 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1458 { 1459 u32 irq_value, irq_msk; 1460 struct hisi_hba *hisi_hba = p; 1461 struct device *dev = hisi_hba->dev; 1462 int i; 1463 1464 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1465 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1466 1467 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1468 irq_value &= ~irq_msk; 1469 1470 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1471 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1472 1473 if (!(irq_value & error->irq_msk)) 1474 continue; 1475 1476 if (error->sub) { 1477 const struct hisi_sas_hw_error *sub = error->sub; 1478 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1479 1480 for (; sub->msk || sub->msg; sub++) { 1481 if (!(err_value & sub->msk)) 1482 continue; 1483 1484 dev_err(dev, "%s error (0x%x) found!\n", 1485 sub->msg, irq_value); 1486 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1487 } 1488 } else { 1489 dev_err(dev, "%s error (0x%x) found!\n", 1490 error->msg, irq_value); 1491 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1492 } 1493 } 1494 1495 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1496 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1497 u32 dev_id = reg_val & ITCT_DEV_MSK; 1498 struct hisi_sas_device *sas_dev = 1499 &hisi_hba->devices[dev_id]; 1500 1501 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1502 dev_dbg(dev, "clear ITCT ok\n"); 1503 complete(sas_dev->completion); 1504 } 1505 1506 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1507 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1508 1509 return IRQ_HANDLED; 1510 } 1511 1512 static void 1513 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1514 struct hisi_sas_slot *slot) 1515 { 1516 struct task_status_struct *ts = &task->task_status; 1517 struct hisi_sas_complete_v3_hdr *complete_queue = 1518 hisi_hba->complete_hdr[slot->cmplt_queue]; 1519 struct hisi_sas_complete_v3_hdr *complete_hdr = 1520 &complete_queue[slot->cmplt_queue_slot]; 1521 struct hisi_sas_err_record_v3 *record = 1522 hisi_sas_status_buf_addr_mem(slot); 1523 u32 dma_rx_err_type = record->dma_rx_err_type; 1524 u32 trans_tx_fail_type = record->trans_tx_fail_type; 1525 1526 switch (task->task_proto) { 1527 case SAS_PROTOCOL_SSP: 1528 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1529 ts->residual = trans_tx_fail_type; 1530 ts->stat = SAS_DATA_UNDERRUN; 1531 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1532 ts->stat = SAS_QUEUE_FULL; 1533 slot->abort = 1; 1534 } else { 1535 ts->stat = SAS_OPEN_REJECT; 1536 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1537 } 1538 break; 1539 case SAS_PROTOCOL_SATA: 1540 case SAS_PROTOCOL_STP: 1541 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1542 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1543 ts->residual = trans_tx_fail_type; 1544 ts->stat = SAS_DATA_UNDERRUN; 1545 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1546 ts->stat = SAS_PHY_DOWN; 1547 slot->abort = 1; 1548 } else { 1549 ts->stat = SAS_OPEN_REJECT; 1550 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1551 } 1552 hisi_sas_sata_done(task, slot); 1553 break; 1554 case SAS_PROTOCOL_SMP: 1555 ts->stat = SAM_STAT_CHECK_CONDITION; 1556 break; 1557 default: 1558 break; 1559 } 1560 } 1561 1562 static int 1563 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1564 { 1565 struct sas_task *task = slot->task; 1566 struct hisi_sas_device *sas_dev; 1567 struct device *dev = hisi_hba->dev; 1568 struct task_status_struct *ts; 1569 struct domain_device *device; 1570 struct sas_ha_struct *ha; 1571 enum exec_status sts; 1572 struct hisi_sas_complete_v3_hdr *complete_queue = 1573 hisi_hba->complete_hdr[slot->cmplt_queue]; 1574 struct hisi_sas_complete_v3_hdr *complete_hdr = 1575 &complete_queue[slot->cmplt_queue_slot]; 1576 unsigned long flags; 1577 bool is_internal = slot->is_internal; 1578 1579 if (unlikely(!task || !task->lldd_task || !task->dev)) 1580 return -EINVAL; 1581 1582 ts = &task->task_status; 1583 device = task->dev; 1584 ha = device->port->ha; 1585 sas_dev = device->lldd_dev; 1586 1587 spin_lock_irqsave(&task->task_state_lock, flags); 1588 task->task_state_flags &= 1589 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1590 spin_unlock_irqrestore(&task->task_state_lock, flags); 1591 1592 memset(ts, 0, sizeof(*ts)); 1593 ts->resp = SAS_TASK_COMPLETE; 1594 1595 if (unlikely(!sas_dev)) { 1596 dev_dbg(dev, "slot complete: port has not device\n"); 1597 ts->stat = SAS_PHY_DOWN; 1598 goto out; 1599 } 1600 1601 /* 1602 * Use SAS+TMF status codes 1603 */ 1604 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1605 >> CMPLT_HDR_ABORT_STAT_OFF) { 1606 case STAT_IO_ABORTED: 1607 /* this IO has been aborted by abort command */ 1608 ts->stat = SAS_ABORTED_TASK; 1609 goto out; 1610 case STAT_IO_COMPLETE: 1611 /* internal abort command complete */ 1612 ts->stat = TMF_RESP_FUNC_SUCC; 1613 goto out; 1614 case STAT_IO_NO_DEVICE: 1615 ts->stat = TMF_RESP_FUNC_COMPLETE; 1616 goto out; 1617 case STAT_IO_NOT_VALID: 1618 /* 1619 * abort single IO, the controller can't find the IO 1620 */ 1621 ts->stat = TMF_RESP_FUNC_FAILED; 1622 goto out; 1623 default: 1624 break; 1625 } 1626 1627 /* check for erroneous completion */ 1628 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1629 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1630 1631 slot_err_v3_hw(hisi_hba, task, slot); 1632 if (ts->stat != SAS_DATA_UNDERRUN) 1633 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1634 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1635 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1636 slot->idx, task, sas_dev->device_id, 1637 complete_hdr->dw0, complete_hdr->dw1, 1638 complete_hdr->act, complete_hdr->dw3, 1639 error_info[0], error_info[1], 1640 error_info[2], error_info[3]); 1641 if (unlikely(slot->abort)) 1642 return ts->stat; 1643 goto out; 1644 } 1645 1646 switch (task->task_proto) { 1647 case SAS_PROTOCOL_SSP: { 1648 struct ssp_response_iu *iu = 1649 hisi_sas_status_buf_addr_mem(slot) + 1650 sizeof(struct hisi_sas_err_record); 1651 1652 sas_ssp_task_response(dev, task, iu); 1653 break; 1654 } 1655 case SAS_PROTOCOL_SMP: { 1656 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1657 void *to; 1658 1659 ts->stat = SAM_STAT_GOOD; 1660 to = kmap_atomic(sg_page(sg_resp)); 1661 1662 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1663 DMA_FROM_DEVICE); 1664 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1665 DMA_TO_DEVICE); 1666 memcpy(to + sg_resp->offset, 1667 hisi_sas_status_buf_addr_mem(slot) + 1668 sizeof(struct hisi_sas_err_record), 1669 sg_dma_len(sg_resp)); 1670 kunmap_atomic(to); 1671 break; 1672 } 1673 case SAS_PROTOCOL_SATA: 1674 case SAS_PROTOCOL_STP: 1675 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1676 ts->stat = SAM_STAT_GOOD; 1677 hisi_sas_sata_done(task, slot); 1678 break; 1679 default: 1680 ts->stat = SAM_STAT_CHECK_CONDITION; 1681 break; 1682 } 1683 1684 if (!slot->port->port_attached) { 1685 dev_warn(dev, "slot complete: port %d has removed\n", 1686 slot->port->sas_port.id); 1687 ts->stat = SAS_PHY_DOWN; 1688 } 1689 1690 out: 1691 hisi_sas_slot_task_free(hisi_hba, task, slot); 1692 sts = ts->stat; 1693 spin_lock_irqsave(&task->task_state_lock, flags); 1694 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1695 spin_unlock_irqrestore(&task->task_state_lock, flags); 1696 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1697 return SAS_ABORTED_TASK; 1698 } 1699 task->task_state_flags |= SAS_TASK_STATE_DONE; 1700 spin_unlock_irqrestore(&task->task_state_lock, flags); 1701 1702 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1703 spin_lock_irqsave(&device->done_lock, flags); 1704 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1705 spin_unlock_irqrestore(&device->done_lock, flags); 1706 dev_info(dev, "slot complete: task(%p) ignored\n ", 1707 task); 1708 return sts; 1709 } 1710 spin_unlock_irqrestore(&device->done_lock, flags); 1711 } 1712 1713 if (task->task_done) 1714 task->task_done(task); 1715 1716 return sts; 1717 } 1718 1719 static void cq_tasklet_v3_hw(unsigned long val) 1720 { 1721 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1722 struct hisi_hba *hisi_hba = cq->hisi_hba; 1723 struct hisi_sas_slot *slot; 1724 struct hisi_sas_complete_v3_hdr *complete_queue; 1725 u32 rd_point = cq->rd_point, wr_point; 1726 int queue = cq->id; 1727 1728 complete_queue = hisi_hba->complete_hdr[queue]; 1729 1730 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1731 (0x14 * queue)); 1732 1733 while (rd_point != wr_point) { 1734 struct hisi_sas_complete_v3_hdr *complete_hdr; 1735 struct device *dev = hisi_hba->dev; 1736 int iptt; 1737 1738 complete_hdr = &complete_queue[rd_point]; 1739 1740 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 1741 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 1742 slot = &hisi_hba->slot_info[iptt]; 1743 slot->cmplt_queue_slot = rd_point; 1744 slot->cmplt_queue = queue; 1745 slot_complete_v3_hw(hisi_hba, slot); 1746 } else 1747 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 1748 1749 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1750 rd_point = 0; 1751 } 1752 1753 /* update rd_point */ 1754 cq->rd_point = rd_point; 1755 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1756 } 1757 1758 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 1759 { 1760 struct hisi_sas_cq *cq = p; 1761 struct hisi_hba *hisi_hba = cq->hisi_hba; 1762 int queue = cq->id; 1763 1764 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1765 1766 tasklet_schedule(&cq->tasklet); 1767 1768 return IRQ_HANDLED; 1769 } 1770 1771 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 1772 { 1773 struct device *dev = hisi_hba->dev; 1774 struct pci_dev *pdev = hisi_hba->pci_dev; 1775 int vectors, rc; 1776 int i, k; 1777 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 1778 1779 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 1780 max_msi, PCI_IRQ_MSI); 1781 if (vectors < max_msi) { 1782 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 1783 return -ENOENT; 1784 } 1785 1786 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 1787 int_phy_up_down_bcast_v3_hw, 0, 1788 DRV_NAME " phy", hisi_hba); 1789 if (rc) { 1790 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 1791 rc = -ENOENT; 1792 goto free_irq_vectors; 1793 } 1794 1795 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 1796 int_chnl_int_v3_hw, 0, 1797 DRV_NAME " channel", hisi_hba); 1798 if (rc) { 1799 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 1800 rc = -ENOENT; 1801 goto free_phy_irq; 1802 } 1803 1804 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 1805 fatal_axi_int_v3_hw, 0, 1806 DRV_NAME " fatal", hisi_hba); 1807 if (rc) { 1808 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 1809 rc = -ENOENT; 1810 goto free_chnl_interrupt; 1811 } 1812 1813 /* Init tasklets for cq only */ 1814 for (i = 0; i < hisi_hba->queue_count; i++) { 1815 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 1816 struct tasklet_struct *t = &cq->tasklet; 1817 1818 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), 1819 cq_interrupt_v3_hw, 0, 1820 DRV_NAME " cq", cq); 1821 if (rc) { 1822 dev_err(dev, 1823 "could not request cq%d interrupt, rc=%d\n", 1824 i, rc); 1825 rc = -ENOENT; 1826 goto free_cq_irqs; 1827 } 1828 1829 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 1830 } 1831 1832 return 0; 1833 1834 free_cq_irqs: 1835 for (k = 0; k < i; k++) { 1836 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 1837 1838 free_irq(pci_irq_vector(pdev, k+16), cq); 1839 } 1840 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 1841 free_chnl_interrupt: 1842 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 1843 free_phy_irq: 1844 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 1845 free_irq_vectors: 1846 pci_free_irq_vectors(pdev); 1847 return rc; 1848 } 1849 1850 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 1851 { 1852 int rc; 1853 1854 rc = hw_init_v3_hw(hisi_hba); 1855 if (rc) 1856 return rc; 1857 1858 rc = interrupt_init_v3_hw(hisi_hba); 1859 if (rc) 1860 return rc; 1861 1862 return 0; 1863 } 1864 1865 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 1866 struct sas_phy_linkrates *r) 1867 { 1868 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1869 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1870 enum sas_linkrate min, max; 1871 u32 prog_phy_link_rate = 0x800; 1872 1873 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) { 1874 max = sas_phy->phy->maximum_linkrate; 1875 min = r->minimum_linkrate; 1876 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) { 1877 max = r->maximum_linkrate; 1878 min = sas_phy->phy->minimum_linkrate; 1879 } else 1880 return; 1881 1882 sas_phy->phy->maximum_linkrate = max; 1883 sas_phy->phy->minimum_linkrate = min; 1884 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 1885 1886 disable_phy_v3_hw(hisi_hba, phy_no); 1887 msleep(100); 1888 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1889 prog_phy_link_rate); 1890 start_phy_v3_hw(hisi_hba, phy_no); 1891 } 1892 1893 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 1894 { 1895 struct pci_dev *pdev = hisi_hba->pci_dev; 1896 int i; 1897 1898 synchronize_irq(pci_irq_vector(pdev, 1)); 1899 synchronize_irq(pci_irq_vector(pdev, 2)); 1900 synchronize_irq(pci_irq_vector(pdev, 11)); 1901 for (i = 0; i < hisi_hba->queue_count; i++) { 1902 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 1903 synchronize_irq(pci_irq_vector(pdev, i + 16)); 1904 } 1905 1906 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 1907 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 1908 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 1909 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 1910 1911 for (i = 0; i < hisi_hba->n_phy; i++) { 1912 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 1913 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 1914 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 1915 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 1916 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 1917 } 1918 } 1919 1920 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 1921 { 1922 return hisi_sas_read32(hisi_hba, PHY_STATE); 1923 } 1924 1925 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1926 { 1927 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1928 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1929 struct sas_phy *sphy = sas_phy->phy; 1930 u32 reg_value; 1931 1932 /* loss dword sync */ 1933 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1934 sphy->loss_of_dword_sync_count += reg_value; 1935 1936 /* phy reset problem */ 1937 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1938 sphy->phy_reset_problem_count += reg_value; 1939 1940 /* invalid dword */ 1941 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1942 sphy->invalid_dword_count += reg_value; 1943 1944 /* disparity err */ 1945 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1946 sphy->running_disparity_error_count += reg_value; 1947 1948 } 1949 1950 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 1951 { 1952 struct device *dev = hisi_hba->dev; 1953 int rc; 1954 u32 status; 1955 1956 interrupt_disable_v3_hw(hisi_hba); 1957 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 1958 hisi_sas_kill_tasklets(hisi_hba); 1959 1960 hisi_sas_stop_phys(hisi_hba); 1961 1962 mdelay(10); 1963 1964 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); 1965 1966 /* wait until bus idle */ 1967 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 1968 AM_CURR_TRANS_RETURN, status, 1969 status == 0x3, 10, 100); 1970 if (rc) { 1971 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 1972 return rc; 1973 } 1974 1975 hisi_sas_init_mem(hisi_hba); 1976 1977 return hw_init_v3_hw(hisi_hba); 1978 } 1979 1980 static const struct hisi_sas_hw hisi_sas_v3_hw = { 1981 .hw_init = hisi_sas_v3_init, 1982 .setup_itct = setup_itct_v3_hw, 1983 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 1984 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 1985 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 1986 .clear_itct = clear_itct_v3_hw, 1987 .sl_notify = sl_notify_v3_hw, 1988 .prep_ssp = prep_ssp_v3_hw, 1989 .prep_smp = prep_smp_v3_hw, 1990 .prep_stp = prep_ata_v3_hw, 1991 .prep_abort = prep_abort_v3_hw, 1992 .get_free_slot = get_free_slot_v3_hw, 1993 .start_delivery = start_delivery_v3_hw, 1994 .slot_complete = slot_complete_v3_hw, 1995 .phys_init = phys_init_v3_hw, 1996 .phy_start = start_phy_v3_hw, 1997 .phy_disable = disable_phy_v3_hw, 1998 .phy_hard_reset = phy_hard_reset_v3_hw, 1999 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2000 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2001 .dereg_device = dereg_device_v3_hw, 2002 .soft_reset = soft_reset_v3_hw, 2003 .get_phys_state = get_phys_state_v3_hw, 2004 .get_events = phy_get_events_v3_hw, 2005 }; 2006 2007 static struct Scsi_Host * 2008 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2009 { 2010 struct Scsi_Host *shost; 2011 struct hisi_hba *hisi_hba; 2012 struct device *dev = &pdev->dev; 2013 2014 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba)); 2015 if (!shost) { 2016 dev_err(dev, "shost alloc failed\n"); 2017 return NULL; 2018 } 2019 hisi_hba = shost_priv(shost); 2020 2021 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2022 hisi_hba->hw = &hisi_sas_v3_hw; 2023 hisi_hba->pci_dev = pdev; 2024 hisi_hba->dev = dev; 2025 hisi_hba->shost = shost; 2026 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2027 2028 timer_setup(&hisi_hba->timer, NULL, 0); 2029 2030 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2031 goto err_out; 2032 2033 if (hisi_sas_alloc(hisi_hba, shost)) { 2034 hisi_sas_free(hisi_hba); 2035 goto err_out; 2036 } 2037 2038 return shost; 2039 err_out: 2040 scsi_host_put(shost); 2041 dev_err(dev, "shost alloc failed\n"); 2042 return NULL; 2043 } 2044 2045 static int 2046 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2047 { 2048 struct Scsi_Host *shost; 2049 struct hisi_hba *hisi_hba; 2050 struct device *dev = &pdev->dev; 2051 struct asd_sas_phy **arr_phy; 2052 struct asd_sas_port **arr_port; 2053 struct sas_ha_struct *sha; 2054 int rc, phy_nr, port_nr, i; 2055 2056 rc = pci_enable_device(pdev); 2057 if (rc) 2058 goto err_out; 2059 2060 pci_set_master(pdev); 2061 2062 rc = pci_request_regions(pdev, DRV_NAME); 2063 if (rc) 2064 goto err_out_disable_device; 2065 2066 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 2067 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 2068 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 2069 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { 2070 dev_err(dev, "No usable DMA addressing method\n"); 2071 rc = -EIO; 2072 goto err_out_regions; 2073 } 2074 } 2075 2076 shost = hisi_sas_shost_alloc_pci(pdev); 2077 if (!shost) { 2078 rc = -ENOMEM; 2079 goto err_out_regions; 2080 } 2081 2082 sha = SHOST_TO_SAS_HA(shost); 2083 hisi_hba = shost_priv(shost); 2084 dev_set_drvdata(dev, sha); 2085 2086 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2087 if (!hisi_hba->regs) { 2088 dev_err(dev, "cannot map register.\n"); 2089 rc = -ENOMEM; 2090 goto err_out_ha; 2091 } 2092 2093 phy_nr = port_nr = hisi_hba->n_phy; 2094 2095 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2096 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2097 if (!arr_phy || !arr_port) { 2098 rc = -ENOMEM; 2099 goto err_out_ha; 2100 } 2101 2102 sha->sas_phy = arr_phy; 2103 sha->sas_port = arr_port; 2104 sha->core.shost = shost; 2105 sha->lldd_ha = hisi_hba; 2106 2107 shost->transportt = hisi_sas_stt; 2108 shost->max_id = HISI_SAS_MAX_DEVICES; 2109 shost->max_lun = ~0; 2110 shost->max_channel = 1; 2111 shost->max_cmd_len = 16; 2112 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); 2113 shost->can_queue = hisi_hba->hw->max_command_entries; 2114 shost->cmd_per_lun = hisi_hba->hw->max_command_entries; 2115 2116 sha->sas_ha_name = DRV_NAME; 2117 sha->dev = dev; 2118 sha->lldd_module = THIS_MODULE; 2119 sha->sas_addr = &hisi_hba->sas_addr[0]; 2120 sha->num_phys = hisi_hba->n_phy; 2121 sha->core.shost = hisi_hba->shost; 2122 2123 for (i = 0; i < hisi_hba->n_phy; i++) { 2124 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2125 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2126 } 2127 2128 rc = scsi_add_host(shost, dev); 2129 if (rc) 2130 goto err_out_ha; 2131 2132 rc = sas_register_ha(sha); 2133 if (rc) 2134 goto err_out_register_ha; 2135 2136 rc = hisi_hba->hw->hw_init(hisi_hba); 2137 if (rc) 2138 goto err_out_register_ha; 2139 2140 scsi_scan_host(shost); 2141 2142 return 0; 2143 2144 err_out_register_ha: 2145 scsi_remove_host(shost); 2146 err_out_ha: 2147 scsi_host_put(shost); 2148 err_out_regions: 2149 pci_release_regions(pdev); 2150 err_out_disable_device: 2151 pci_disable_device(pdev); 2152 err_out: 2153 return rc; 2154 } 2155 2156 static void 2157 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2158 { 2159 int i; 2160 2161 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2162 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2163 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2164 for (i = 0; i < hisi_hba->queue_count; i++) { 2165 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2166 2167 free_irq(pci_irq_vector(pdev, i+16), cq); 2168 } 2169 pci_free_irq_vectors(pdev); 2170 } 2171 2172 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2173 { 2174 struct device *dev = &pdev->dev; 2175 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2176 struct hisi_hba *hisi_hba = sha->lldd_ha; 2177 struct Scsi_Host *shost = sha->core.shost; 2178 2179 if (timer_pending(&hisi_hba->timer)) 2180 del_timer(&hisi_hba->timer); 2181 2182 sas_unregister_ha(sha); 2183 sas_remove_host(sha->core.shost); 2184 2185 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2186 hisi_sas_kill_tasklets(hisi_hba); 2187 pci_release_regions(pdev); 2188 pci_disable_device(pdev); 2189 hisi_sas_free(hisi_hba); 2190 scsi_host_put(shost); 2191 } 2192 2193 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2194 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2195 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2196 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2197 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2198 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2199 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2200 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2201 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2202 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2203 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2204 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2205 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2206 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2207 }; 2208 2209 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2210 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2211 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2212 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2213 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2214 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2215 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2216 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2217 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2218 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2219 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2220 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2221 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2222 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2223 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2224 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2225 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2226 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2227 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2228 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2229 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2230 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2231 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2232 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2233 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2234 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2235 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2236 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2237 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2238 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2239 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2240 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2241 }; 2242 2243 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2244 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2245 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2246 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2247 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2248 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2249 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2250 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2251 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2252 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2253 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2254 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2255 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2256 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2257 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2258 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2259 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2260 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2261 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2262 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2263 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2264 }; 2265 2266 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2267 { 2268 struct device *dev = hisi_hba->dev; 2269 const struct hisi_sas_hw_error *ras_error; 2270 bool need_reset = false; 2271 u32 irq_value; 2272 int i; 2273 2274 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2275 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2276 ras_error = &sas_ras_intr0_nfe[i]; 2277 if (ras_error->irq_msk & irq_value) { 2278 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2279 ras_error->msg, irq_value); 2280 need_reset = true; 2281 } 2282 } 2283 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2284 2285 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2286 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2287 ras_error = &sas_ras_intr1_nfe[i]; 2288 if (ras_error->irq_msk & irq_value) { 2289 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2290 ras_error->msg, irq_value); 2291 need_reset = true; 2292 } 2293 } 2294 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2295 2296 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2297 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2298 ras_error = &sas_ras_intr2_nfe[i]; 2299 if (ras_error->irq_msk & irq_value) { 2300 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2301 ras_error->msg, irq_value); 2302 need_reset = true; 2303 } 2304 } 2305 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2306 2307 return need_reset; 2308 } 2309 2310 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2311 pci_channel_state_t state) 2312 { 2313 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2314 struct hisi_hba *hisi_hba = sha->lldd_ha; 2315 struct device *dev = hisi_hba->dev; 2316 2317 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2318 if (state == pci_channel_io_perm_failure) 2319 return PCI_ERS_RESULT_DISCONNECT; 2320 2321 if (process_non_fatal_error_v3_hw(hisi_hba)) 2322 return PCI_ERS_RESULT_NEED_RESET; 2323 2324 return PCI_ERS_RESULT_CAN_RECOVER; 2325 } 2326 2327 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2328 { 2329 return PCI_ERS_RESULT_RECOVERED; 2330 } 2331 2332 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2333 { 2334 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2335 struct hisi_hba *hisi_hba = sha->lldd_ha; 2336 struct device *dev = hisi_hba->dev; 2337 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2338 2339 dev_info(dev, "PCI error: slot reset callback!!\n"); 2340 queue_work(hisi_hba->wq, &r.work); 2341 wait_for_completion(r.completion); 2342 if (r.done) 2343 return PCI_ERS_RESULT_RECOVERED; 2344 2345 return PCI_ERS_RESULT_DISCONNECT; 2346 } 2347 2348 enum { 2349 /* instances of the controller */ 2350 hip08, 2351 }; 2352 2353 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 2354 { 2355 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2356 struct hisi_hba *hisi_hba = sha->lldd_ha; 2357 struct device *dev = hisi_hba->dev; 2358 struct Scsi_Host *shost = hisi_hba->shost; 2359 u32 device_state, status; 2360 int rc; 2361 u32 reg_val; 2362 unsigned long flags; 2363 2364 if (!pdev->pm_cap) { 2365 dev_err(dev, "PCI PM not supported\n"); 2366 return -ENODEV; 2367 } 2368 2369 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2370 scsi_block_requests(shost); 2371 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2372 flush_workqueue(hisi_hba->wq); 2373 /* disable DQ/PHY/bus */ 2374 interrupt_disable_v3_hw(hisi_hba); 2375 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2376 hisi_sas_kill_tasklets(hisi_hba); 2377 2378 hisi_sas_stop_phys(hisi_hba); 2379 2380 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2381 AM_CTRL_GLOBAL); 2382 reg_val |= 0x1; 2383 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2384 AM_CTRL_GLOBAL, reg_val); 2385 2386 /* wait until bus idle */ 2387 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2388 AM_CURR_TRANS_RETURN, status, 2389 status == 0x3, 10, 100); 2390 if (rc) { 2391 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 2392 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2393 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2394 scsi_unblock_requests(shost); 2395 return rc; 2396 } 2397 2398 hisi_sas_init_mem(hisi_hba); 2399 2400 device_state = pci_choose_state(pdev, state); 2401 dev_warn(dev, "entering operating state [D%d]\n", 2402 device_state); 2403 pci_save_state(pdev); 2404 pci_disable_device(pdev); 2405 pci_set_power_state(pdev, device_state); 2406 2407 spin_lock_irqsave(&hisi_hba->lock, flags); 2408 hisi_sas_release_tasks(hisi_hba); 2409 spin_unlock_irqrestore(&hisi_hba->lock, flags); 2410 2411 sas_suspend_ha(sha); 2412 return 0; 2413 } 2414 2415 static int hisi_sas_v3_resume(struct pci_dev *pdev) 2416 { 2417 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2418 struct hisi_hba *hisi_hba = sha->lldd_ha; 2419 struct Scsi_Host *shost = hisi_hba->shost; 2420 struct device *dev = hisi_hba->dev; 2421 unsigned int rc; 2422 u32 device_state = pdev->current_state; 2423 2424 dev_warn(dev, "resuming from operating state [D%d]\n", 2425 device_state); 2426 pci_set_power_state(pdev, PCI_D0); 2427 pci_enable_wake(pdev, PCI_D0, 0); 2428 pci_restore_state(pdev); 2429 rc = pci_enable_device(pdev); 2430 if (rc) 2431 dev_err(dev, "enable device failed during resume (%d)\n", rc); 2432 2433 pci_set_master(pdev); 2434 scsi_unblock_requests(shost); 2435 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2436 2437 sas_prep_resume_ha(sha); 2438 init_reg_v3_hw(hisi_hba); 2439 hisi_hba->hw->phys_init(hisi_hba); 2440 sas_resume_ha(sha); 2441 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2442 2443 return 0; 2444 } 2445 2446 static const struct pci_device_id sas_v3_pci_table[] = { 2447 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 2448 {} 2449 }; 2450 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 2451 2452 static const struct pci_error_handlers hisi_sas_err_handler = { 2453 .error_detected = hisi_sas_error_detected_v3_hw, 2454 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 2455 .slot_reset = hisi_sas_slot_reset_v3_hw, 2456 }; 2457 2458 static struct pci_driver sas_v3_pci_driver = { 2459 .name = DRV_NAME, 2460 .id_table = sas_v3_pci_table, 2461 .probe = hisi_sas_v3_probe, 2462 .remove = hisi_sas_v3_remove, 2463 .suspend = hisi_sas_v3_suspend, 2464 .resume = hisi_sas_v3_resume, 2465 .err_handler = &hisi_sas_err_handler, 2466 }; 2467 2468 module_pci_driver(sas_v3_pci_driver); 2469 2470 MODULE_LICENSE("GPL"); 2471 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2472 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 2473 MODULE_ALIAS("pci:" DRV_NAME); 2474