1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CFG_AGING_TIME 0xbc 46 #define HGC_DFX_CFG2 0xc0 47 #define CFG_ABT_SET_QUERY_IPTT 0xd4 48 #define CFG_SET_ABORTED_IPTT_OFF 0 49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 50 #define CFG_SET_ABORTED_EN_OFF 12 51 #define CFG_ABT_SET_IPTT_DONE 0xd8 52 #define CFG_ABT_SET_IPTT_DONE_OFF 0 53 #define HGC_IOMB_PROC1_STATUS 0x104 54 #define CFG_1US_TIMER_TRSH 0xcc 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 97 #define DLVRY_Q_0_DEPTH 0x268 98 #define DLVRY_Q_0_WR_PTR 0x26c 99 #define DLVRY_Q_0_RD_PTR 0x270 100 #define HYPER_STREAM_ID_EN_CFG 0xc80 101 #define OQ0_INT_SRC_MSK 0xc90 102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 104 #define COMPL_Q_0_DEPTH 0x4e8 105 #define COMPL_Q_0_WR_PTR 0x4ec 106 #define COMPL_Q_0_RD_PTR 0x4f0 107 #define AWQOS_AWCACHE_CFG 0xc84 108 #define ARQOS_ARCACHE_CFG 0xc88 109 110 /* phy registers requiring init */ 111 #define PORT_BASE (0x2000) 112 #define PHY_CFG (PORT_BASE + 0x0) 113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 114 #define PHY_CFG_ENA_OFF 0 115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 116 #define PHY_CFG_DC_OPT_OFF 2 117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 119 #define PHY_CTRL (PORT_BASE + 0x14) 120 #define PHY_CTRL_RESET_OFF 0 121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 122 #define SL_CFG (PORT_BASE + 0x84) 123 #define SL_CONTROL (PORT_BASE + 0x94) 124 #define SL_CONTROL_NOTIFY_EN_OFF 0 125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 126 #define SL_CTA_OFF 17 127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 135 #define TXID_AUTO (PORT_BASE + 0xb8) 136 #define CT3_OFF 1 137 #define CT3_MSK (0x1 << CT3_OFF) 138 #define TX_HARDRST_OFF 2 139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 142 #define STP_LINK_TIMER (PORT_BASE + 0x120) 143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 144 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 148 #define CHL_INT0 (PORT_BASE + 0x1b4) 149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 155 #define CHL_INT0_NOT_RDY_OFF 4 156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 157 #define CHL_INT0_PHY_RDY_OFF 5 158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 159 #define CHL_INT1 (PORT_BASE + 0x1b8) 160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 168 #define CHL_INT2 (PORT_BASE + 0x1bc) 169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 175 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 176 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 177 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 178 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 179 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 180 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 181 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 182 #define DMA_TX_STATUS_BUSY_OFF 0 183 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 184 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 185 #define DMA_RX_STATUS_BUSY_OFF 0 186 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 187 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 188 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 189 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 190 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 191 192 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 193 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 194 #error Max ITCT exceeded 195 #endif 196 197 #define AXI_MASTER_CFG_BASE (0x5000) 198 #define AM_CTRL_GLOBAL (0x0) 199 #define AM_CURR_TRANS_RETURN (0x150) 200 201 #define AM_CFG_MAX_TRANS (0x5010) 202 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 203 #define AXI_CFG (0x5100) 204 #define AM_ROB_ECC_ERR_ADDR (0x510c) 205 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 206 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 207 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 208 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 209 210 /* RAS registers need init */ 211 #define RAS_BASE (0x6000) 212 #define SAS_RAS_INTR0 (RAS_BASE) 213 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 214 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 215 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 216 217 /* HW dma structures */ 218 /* Delivery queue header */ 219 /* dw0 */ 220 #define CMD_HDR_ABORT_FLAG_OFF 0 221 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 222 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 223 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 224 #define CMD_HDR_RESP_REPORT_OFF 5 225 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 226 #define CMD_HDR_TLR_CTRL_OFF 6 227 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 228 #define CMD_HDR_PORT_OFF 18 229 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 230 #define CMD_HDR_PRIORITY_OFF 27 231 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 232 #define CMD_HDR_CMD_OFF 29 233 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 234 /* dw1 */ 235 #define CMD_HDR_UNCON_CMD_OFF 3 236 #define CMD_HDR_DIR_OFF 5 237 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 238 #define CMD_HDR_RESET_OFF 7 239 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 240 #define CMD_HDR_VDTL_OFF 10 241 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 242 #define CMD_HDR_FRAME_TYPE_OFF 11 243 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 244 #define CMD_HDR_DEV_ID_OFF 16 245 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 246 /* dw2 */ 247 #define CMD_HDR_CFL_OFF 0 248 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 249 #define CMD_HDR_NCQ_TAG_OFF 10 250 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 251 #define CMD_HDR_MRFL_OFF 15 252 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 253 #define CMD_HDR_SG_MOD_OFF 24 254 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 255 /* dw3 */ 256 #define CMD_HDR_IPTT_OFF 0 257 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 258 /* dw6 */ 259 #define CMD_HDR_DIF_SGL_LEN_OFF 0 260 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 261 #define CMD_HDR_DATA_SGL_LEN_OFF 16 262 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 263 /* dw7 */ 264 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 265 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 266 #define CMD_HDR_ABORT_IPTT_OFF 16 267 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 268 269 /* Completion header */ 270 /* dw0 */ 271 #define CMPLT_HDR_CMPLT_OFF 0 272 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 273 #define CMPLT_HDR_ERROR_PHASE_OFF 2 274 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 275 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 276 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 277 #define CMPLT_HDR_ERX_OFF 12 278 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 279 #define CMPLT_HDR_ABORT_STAT_OFF 13 280 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 281 /* abort_stat */ 282 #define STAT_IO_NOT_VALID 0x1 283 #define STAT_IO_NO_DEVICE 0x2 284 #define STAT_IO_COMPLETE 0x3 285 #define STAT_IO_ABORTED 0x4 286 /* dw1 */ 287 #define CMPLT_HDR_IPTT_OFF 0 288 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 289 #define CMPLT_HDR_DEV_ID_OFF 16 290 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 291 /* dw3 */ 292 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 293 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 294 295 /* ITCT header */ 296 /* qw0 */ 297 #define ITCT_HDR_DEV_TYPE_OFF 0 298 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 299 #define ITCT_HDR_VALID_OFF 2 300 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 301 #define ITCT_HDR_MCR_OFF 5 302 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 303 #define ITCT_HDR_VLN_OFF 9 304 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 305 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 306 #define ITCT_HDR_AWT_CONTINUE_OFF 25 307 #define ITCT_HDR_PORT_ID_OFF 28 308 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 309 /* qw2 */ 310 #define ITCT_HDR_INLT_OFF 0 311 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 312 #define ITCT_HDR_RTOLT_OFF 48 313 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 314 315 struct hisi_sas_complete_v3_hdr { 316 __le32 dw0; 317 __le32 dw1; 318 __le32 act; 319 __le32 dw3; 320 }; 321 322 struct hisi_sas_err_record_v3 { 323 /* dw0 */ 324 __le32 trans_tx_fail_type; 325 326 /* dw1 */ 327 __le32 trans_rx_fail_type; 328 329 /* dw2 */ 330 __le16 dma_tx_err_type; 331 __le16 sipc_rx_err_type; 332 333 /* dw3 */ 334 __le32 dma_rx_err_type; 335 }; 336 337 #define RX_DATA_LEN_UNDERFLOW_OFF 6 338 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 339 340 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 341 #define HISI_SAS_MSI_COUNT_V3_HW 32 342 343 #define DIR_NO_DATA 0 344 #define DIR_TO_INI 1 345 #define DIR_TO_DEVICE 2 346 #define DIR_RESERVED 3 347 348 #define CMD_IS_UNCONSTRAINT(cmd) \ 349 ((cmd == ATA_CMD_READ_LOG_EXT) || \ 350 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \ 351 (cmd == ATA_CMD_DEV_RESET)) 352 353 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 354 { 355 void __iomem *regs = hisi_hba->regs + off; 356 357 return readl(regs); 358 } 359 360 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 361 { 362 void __iomem *regs = hisi_hba->regs + off; 363 364 return readl_relaxed(regs); 365 } 366 367 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 368 { 369 void __iomem *regs = hisi_hba->regs + off; 370 371 writel(val, regs); 372 } 373 374 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 375 u32 off, u32 val) 376 { 377 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 378 379 writel(val, regs); 380 } 381 382 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 383 int phy_no, u32 off) 384 { 385 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 386 387 return readl(regs); 388 } 389 390 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 391 { 392 int i; 393 394 /* Global registers init */ 395 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 396 (u32)((1ULL << hisi_hba->queue_count) - 1)); 397 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 398 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 399 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd); 400 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 401 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 402 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 403 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 404 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 405 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 406 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 407 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 408 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 409 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 410 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 411 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 412 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 413 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 414 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 415 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 416 for (i = 0; i < hisi_hba->queue_count; i++) 417 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 418 419 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 420 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000); 421 422 for (i = 0; i < hisi_hba->n_phy; i++) { 423 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801); 424 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 425 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 426 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 427 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 428 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff); 429 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 430 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 431 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 432 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 433 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 434 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 435 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); 436 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa); 437 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 438 0xa03e8); 439 hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG, 440 0xa03e8); 441 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 442 0x7f7a120); 443 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 444 0x2a0a80); 445 } 446 for (i = 0; i < hisi_hba->queue_count; i++) { 447 /* Delivery queue */ 448 hisi_sas_write32(hisi_hba, 449 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 450 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 451 452 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 453 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 454 455 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 456 HISI_SAS_QUEUE_SLOTS); 457 458 /* Completion queue */ 459 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 460 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 461 462 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 463 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 464 465 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 466 HISI_SAS_QUEUE_SLOTS); 467 } 468 469 /* itct */ 470 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 471 lower_32_bits(hisi_hba->itct_dma)); 472 473 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 474 upper_32_bits(hisi_hba->itct_dma)); 475 476 /* iost */ 477 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 478 lower_32_bits(hisi_hba->iost_dma)); 479 480 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 481 upper_32_bits(hisi_hba->iost_dma)); 482 483 /* breakpoint */ 484 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 485 lower_32_bits(hisi_hba->breakpoint_dma)); 486 487 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 488 upper_32_bits(hisi_hba->breakpoint_dma)); 489 490 /* SATA broken msg */ 491 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 492 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 493 494 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 495 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 496 497 /* SATA initial fis */ 498 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 499 lower_32_bits(hisi_hba->initial_fis_dma)); 500 501 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 502 upper_32_bits(hisi_hba->initial_fis_dma)); 503 504 /* RAS registers init */ 505 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 506 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 507 } 508 509 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 510 { 511 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 512 513 cfg &= ~PHY_CFG_DC_OPT_MSK; 514 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 515 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 516 } 517 518 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 519 { 520 struct sas_identify_frame identify_frame; 521 u32 *identify_buffer; 522 523 memset(&identify_frame, 0, sizeof(identify_frame)); 524 identify_frame.dev_type = SAS_END_DEVICE; 525 identify_frame.frame_type = 0; 526 identify_frame._un1 = 1; 527 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 528 identify_frame.target_bits = SAS_PROTOCOL_NONE; 529 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 530 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 531 identify_frame.phy_id = phy_no; 532 identify_buffer = (u32 *)(&identify_frame); 533 534 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 535 __swab32(identify_buffer[0])); 536 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 537 __swab32(identify_buffer[1])); 538 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 539 __swab32(identify_buffer[2])); 540 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 541 __swab32(identify_buffer[3])); 542 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 543 __swab32(identify_buffer[4])); 544 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 545 __swab32(identify_buffer[5])); 546 } 547 548 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 549 struct hisi_sas_device *sas_dev) 550 { 551 struct domain_device *device = sas_dev->sas_device; 552 struct device *dev = hisi_hba->dev; 553 u64 qw0, device_id = sas_dev->device_id; 554 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 555 struct domain_device *parent_dev = device->parent; 556 struct asd_sas_port *sas_port = device->port; 557 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 558 559 memset(itct, 0, sizeof(*itct)); 560 561 /* qw0 */ 562 qw0 = 0; 563 switch (sas_dev->dev_type) { 564 case SAS_END_DEVICE: 565 case SAS_EDGE_EXPANDER_DEVICE: 566 case SAS_FANOUT_EXPANDER_DEVICE: 567 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 568 break; 569 case SAS_SATA_DEV: 570 case SAS_SATA_PENDING: 571 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 572 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 573 else 574 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 575 break; 576 default: 577 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 578 sas_dev->dev_type); 579 } 580 581 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 582 (device->linkrate << ITCT_HDR_MCR_OFF) | 583 (1 << ITCT_HDR_VLN_OFF) | 584 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 585 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 586 (port->id << ITCT_HDR_PORT_ID_OFF)); 587 itct->qw0 = cpu_to_le64(qw0); 588 589 /* qw1 */ 590 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 591 itct->sas_addr = __swab64(itct->sas_addr); 592 593 /* qw2 */ 594 if (!dev_is_sata(device)) 595 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 596 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 597 } 598 599 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 600 struct hisi_sas_device *sas_dev) 601 { 602 DECLARE_COMPLETION_ONSTACK(completion); 603 u64 dev_id = sas_dev->device_id; 604 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 605 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 606 607 sas_dev->completion = &completion; 608 609 /* clear the itct interrupt state */ 610 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 611 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 612 ENT_INT_SRC3_ITC_INT_MSK); 613 614 /* clear the itct table*/ 615 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 616 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 617 618 wait_for_completion(sas_dev->completion); 619 memset(itct, 0, sizeof(struct hisi_sas_itct)); 620 } 621 622 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 623 struct domain_device *device) 624 { 625 struct hisi_sas_slot *slot, *slot2; 626 struct hisi_sas_device *sas_dev = device->lldd_dev; 627 u32 cfg_abt_set_query_iptt; 628 629 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 630 CFG_ABT_SET_QUERY_IPTT); 631 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 632 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 633 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 634 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 635 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 636 cfg_abt_set_query_iptt); 637 } 638 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 639 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 640 cfg_abt_set_query_iptt); 641 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 642 1 << CFG_ABT_SET_IPTT_DONE_OFF); 643 } 644 645 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 646 { 647 struct device *dev = hisi_hba->dev; 648 int ret; 649 u32 val; 650 651 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 652 653 /* Disable all of the PHYs */ 654 hisi_sas_stop_phys(hisi_hba); 655 udelay(50); 656 657 /* Ensure axi bus idle */ 658 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val, 659 20000, 1000000); 660 if (ret) { 661 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 662 return -EIO; 663 } 664 665 if (ACPI_HANDLE(dev)) { 666 acpi_status s; 667 668 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 669 if (ACPI_FAILURE(s)) { 670 dev_err(dev, "Reset failed\n"); 671 return -EIO; 672 } 673 } else 674 dev_err(dev, "no reset method!\n"); 675 676 return 0; 677 } 678 679 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 680 { 681 struct device *dev = hisi_hba->dev; 682 int rc; 683 684 rc = reset_hw_v3_hw(hisi_hba); 685 if (rc) { 686 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 687 return rc; 688 } 689 690 msleep(100); 691 init_reg_v3_hw(hisi_hba); 692 693 return 0; 694 } 695 696 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 697 { 698 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 699 700 cfg |= PHY_CFG_ENA_MSK; 701 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 702 } 703 704 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 705 { 706 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 707 708 cfg &= ~PHY_CFG_ENA_MSK; 709 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 710 } 711 712 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 713 { 714 config_id_frame_v3_hw(hisi_hba, phy_no); 715 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 716 enable_phy_v3_hw(hisi_hba, phy_no); 717 } 718 719 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 720 { 721 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 722 u32 txid_auto; 723 724 disable_phy_v3_hw(hisi_hba, phy_no); 725 if (phy->identify.device_type == SAS_END_DEVICE) { 726 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 727 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 728 txid_auto | TX_HARDRST_MSK); 729 } 730 msleep(100); 731 start_phy_v3_hw(hisi_hba, phy_no); 732 } 733 734 enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 735 { 736 return SAS_LINK_RATE_12_0_GBPS; 737 } 738 739 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 740 { 741 int i; 742 743 for (i = 0; i < hisi_hba->n_phy; i++) { 744 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 745 struct asd_sas_phy *sas_phy = &phy->sas_phy; 746 747 if (!sas_phy->phy->enabled) 748 continue; 749 750 start_phy_v3_hw(hisi_hba, i); 751 } 752 } 753 754 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 755 { 756 u32 sl_control; 757 758 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 759 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 760 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 761 msleep(1); 762 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 763 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 764 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 765 } 766 767 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 768 { 769 int i, bitmap = 0; 770 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 771 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 772 773 for (i = 0; i < hisi_hba->n_phy; i++) 774 if (phy_state & BIT(i)) 775 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 776 bitmap |= BIT(i); 777 778 return bitmap; 779 } 780 781 /** 782 * The callpath to this function and upto writing the write 783 * queue pointer should be safe from interruption. 784 */ 785 static int 786 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 787 { 788 struct device *dev = hisi_hba->dev; 789 int queue = dq->id; 790 u32 r, w; 791 792 w = dq->wr_point; 793 r = hisi_sas_read32_relaxed(hisi_hba, 794 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 795 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 796 dev_warn(dev, "full queue=%d r=%d w=%d\n\n", 797 queue, r, w); 798 return -EAGAIN; 799 } 800 801 return 0; 802 } 803 804 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 805 { 806 struct hisi_hba *hisi_hba = dq->hisi_hba; 807 int dlvry_queue = dq->slot_prep->dlvry_queue; 808 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; 809 810 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; 811 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), 812 dq->wr_point); 813 } 814 815 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 816 struct hisi_sas_slot *slot, 817 struct hisi_sas_cmd_hdr *hdr, 818 struct scatterlist *scatter, 819 int n_elem) 820 { 821 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 822 struct device *dev = hisi_hba->dev; 823 struct scatterlist *sg; 824 int i; 825 826 if (n_elem > HISI_SAS_SGE_PAGE_CNT) { 827 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", 828 n_elem); 829 return -EINVAL; 830 } 831 832 for_each_sg(scatter, sg, n_elem, i) { 833 struct hisi_sas_sge *entry = &sge_page->sge[i]; 834 835 entry->addr = cpu_to_le64(sg_dma_address(sg)); 836 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 837 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 838 entry->data_off = 0; 839 } 840 841 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 842 843 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 844 845 return 0; 846 } 847 848 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 849 struct hisi_sas_slot *slot, int is_tmf, 850 struct hisi_sas_tmf_task *tmf) 851 { 852 struct sas_task *task = slot->task; 853 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 854 struct domain_device *device = task->dev; 855 struct hisi_sas_device *sas_dev = device->lldd_dev; 856 struct hisi_sas_port *port = slot->port; 857 struct sas_ssp_task *ssp_task = &task->ssp_task; 858 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 859 int has_data = 0, rc, priority = is_tmf; 860 u8 *buf_cmd; 861 u32 dw1 = 0, dw2 = 0; 862 863 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 864 (2 << CMD_HDR_TLR_CTRL_OFF) | 865 (port->id << CMD_HDR_PORT_OFF) | 866 (priority << CMD_HDR_PRIORITY_OFF) | 867 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 868 869 dw1 = 1 << CMD_HDR_VDTL_OFF; 870 if (is_tmf) { 871 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 872 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 873 } else { 874 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 875 switch (scsi_cmnd->sc_data_direction) { 876 case DMA_TO_DEVICE: 877 has_data = 1; 878 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 879 break; 880 case DMA_FROM_DEVICE: 881 has_data = 1; 882 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 883 break; 884 default: 885 dw1 &= ~CMD_HDR_DIR_MSK; 886 } 887 } 888 889 /* map itct entry */ 890 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 891 hdr->dw1 = cpu_to_le32(dw1); 892 893 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 894 + 3) / 4) << CMD_HDR_CFL_OFF) | 895 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 896 (2 << CMD_HDR_SG_MOD_OFF); 897 hdr->dw2 = cpu_to_le32(dw2); 898 hdr->transfer_tags = cpu_to_le32(slot->idx); 899 900 if (has_data) { 901 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 902 slot->n_elem); 903 if (rc) 904 return rc; 905 } 906 907 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 908 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 909 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 910 911 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 912 sizeof(struct ssp_frame_hdr); 913 914 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 915 if (!is_tmf) { 916 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 917 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 918 } else { 919 buf_cmd[10] = tmf->tmf; 920 switch (tmf->tmf) { 921 case TMF_ABORT_TASK: 922 case TMF_QUERY_TASK: 923 buf_cmd[12] = 924 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 925 buf_cmd[13] = 926 tmf->tag_of_task_to_be_managed & 0xff; 927 break; 928 default: 929 break; 930 } 931 } 932 933 return 0; 934 } 935 936 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba, 937 struct hisi_sas_slot *slot) 938 { 939 struct sas_task *task = slot->task; 940 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 941 struct domain_device *device = task->dev; 942 struct device *dev = hisi_hba->dev; 943 struct hisi_sas_port *port = slot->port; 944 struct scatterlist *sg_req, *sg_resp; 945 struct hisi_sas_device *sas_dev = device->lldd_dev; 946 dma_addr_t req_dma_addr; 947 unsigned int req_len, resp_len; 948 int elem, rc; 949 950 /* 951 * DMA-map SMP request, response buffers 952 */ 953 /* req */ 954 sg_req = &task->smp_task.smp_req; 955 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); 956 if (!elem) 957 return -ENOMEM; 958 req_len = sg_dma_len(sg_req); 959 req_dma_addr = sg_dma_address(sg_req); 960 961 /* resp */ 962 sg_resp = &task->smp_task.smp_resp; 963 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); 964 if (!elem) { 965 rc = -ENOMEM; 966 goto err_out_req; 967 } 968 resp_len = sg_dma_len(sg_resp); 969 if ((req_len & 0x3) || (resp_len & 0x3)) { 970 rc = -EINVAL; 971 goto err_out_resp; 972 } 973 974 /* create header */ 975 /* dw0 */ 976 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 977 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 978 (2 << CMD_HDR_CMD_OFF)); /* smp */ 979 980 /* map itct entry */ 981 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 982 (1 << CMD_HDR_FRAME_TYPE_OFF) | 983 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 984 985 /* dw2 */ 986 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 987 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 988 CMD_HDR_MRFL_OFF)); 989 990 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 991 992 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 993 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 994 995 return 0; 996 997 err_out_resp: 998 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, 999 DMA_FROM_DEVICE); 1000 err_out_req: 1001 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, 1002 DMA_TO_DEVICE); 1003 return rc; 1004 } 1005 1006 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1007 struct hisi_sas_slot *slot) 1008 { 1009 struct sas_task *task = slot->task; 1010 struct domain_device *device = task->dev; 1011 struct domain_device *parent_dev = device->parent; 1012 struct hisi_sas_device *sas_dev = device->lldd_dev; 1013 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1014 struct asd_sas_port *sas_port = device->port; 1015 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1016 u8 *buf_cmd; 1017 int has_data = 0, rc = 0, hdr_tag = 0; 1018 u32 dw1 = 0, dw2 = 0; 1019 1020 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1021 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1022 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1023 else 1024 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1025 1026 switch (task->data_dir) { 1027 case DMA_TO_DEVICE: 1028 has_data = 1; 1029 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1030 break; 1031 case DMA_FROM_DEVICE: 1032 has_data = 1; 1033 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1034 break; 1035 default: 1036 dw1 &= ~CMD_HDR_DIR_MSK; 1037 } 1038 1039 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1040 (task->ata_task.fis.control & ATA_SRST)) 1041 dw1 |= 1 << CMD_HDR_RESET_OFF; 1042 1043 dw1 |= (hisi_sas_get_ata_protocol( 1044 &task->ata_task.fis, task->data_dir)) 1045 << CMD_HDR_FRAME_TYPE_OFF; 1046 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1047 1048 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command)) 1049 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1050 1051 hdr->dw1 = cpu_to_le32(dw1); 1052 1053 /* dw2 */ 1054 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1055 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1056 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1057 } 1058 1059 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1060 2 << CMD_HDR_SG_MOD_OFF; 1061 hdr->dw2 = cpu_to_le32(dw2); 1062 1063 /* dw3 */ 1064 hdr->transfer_tags = cpu_to_le32(slot->idx); 1065 1066 if (has_data) { 1067 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1068 slot->n_elem); 1069 if (rc) 1070 return rc; 1071 } 1072 1073 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1074 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1075 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1076 1077 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1078 1079 if (likely(!task->ata_task.device_control_reg_update)) 1080 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1081 /* fill in command FIS */ 1082 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1083 1084 return 0; 1085 } 1086 1087 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1088 struct hisi_sas_slot *slot, 1089 int device_id, int abort_flag, int tag_to_abort) 1090 { 1091 struct sas_task *task = slot->task; 1092 struct domain_device *dev = task->dev; 1093 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1094 struct hisi_sas_port *port = slot->port; 1095 1096 /* dw0 */ 1097 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1098 (port->id << CMD_HDR_PORT_OFF) | 1099 ((dev_is_sata(dev) ? 1:0) 1100 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1101 (abort_flag 1102 << CMD_HDR_ABORT_FLAG_OFF)); 1103 1104 /* dw1 */ 1105 hdr->dw1 = cpu_to_le32(device_id 1106 << CMD_HDR_DEV_ID_OFF); 1107 1108 /* dw7 */ 1109 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1110 hdr->transfer_tags = cpu_to_le32(slot->idx); 1111 1112 return 0; 1113 } 1114 1115 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1116 { 1117 int i, res = 0; 1118 u32 context, port_id, link_rate; 1119 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1120 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1121 struct device *dev = hisi_hba->dev; 1122 1123 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1124 1125 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1126 port_id = (port_id >> (4 * phy_no)) & 0xf; 1127 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1128 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1129 1130 if (port_id == 0xf) { 1131 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1132 res = IRQ_NONE; 1133 goto end; 1134 } 1135 sas_phy->linkrate = link_rate; 1136 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1137 1138 /* Check for SATA dev */ 1139 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1140 if (context & (1 << phy_no)) { 1141 struct hisi_sas_initial_fis *initial_fis; 1142 struct dev_to_host_fis *fis; 1143 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1144 1145 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1146 initial_fis = &hisi_hba->initial_fis[phy_no]; 1147 fis = &initial_fis->fis; 1148 sas_phy->oob_mode = SATA_OOB_MODE; 1149 attached_sas_addr[0] = 0x50; 1150 attached_sas_addr[7] = phy_no; 1151 memcpy(sas_phy->attached_sas_addr, 1152 attached_sas_addr, 1153 SAS_ADDR_SIZE); 1154 memcpy(sas_phy->frame_rcvd, fis, 1155 sizeof(struct dev_to_host_fis)); 1156 phy->phy_type |= PORT_TYPE_SATA; 1157 phy->identify.device_type = SAS_SATA_DEV; 1158 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1159 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1160 } else { 1161 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1162 struct sas_identify_frame *id = 1163 (struct sas_identify_frame *)frame_rcvd; 1164 1165 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1166 for (i = 0; i < 6; i++) { 1167 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1168 RX_IDAF_DWORD0 + (i * 4)); 1169 frame_rcvd[i] = __swab32(idaf); 1170 } 1171 sas_phy->oob_mode = SAS_OOB_MODE; 1172 memcpy(sas_phy->attached_sas_addr, 1173 &id->sas_addr, 1174 SAS_ADDR_SIZE); 1175 phy->phy_type |= PORT_TYPE_SAS; 1176 phy->identify.device_type = id->dev_type; 1177 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1178 if (phy->identify.device_type == SAS_END_DEVICE) 1179 phy->identify.target_port_protocols = 1180 SAS_PROTOCOL_SSP; 1181 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1182 phy->identify.target_port_protocols = 1183 SAS_PROTOCOL_SMP; 1184 } 1185 1186 phy->port_id = port_id; 1187 phy->phy_attached = 1; 1188 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1189 1190 end: 1191 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1192 CHL_INT0_SL_PHY_ENABLE_MSK); 1193 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1194 1195 return res; 1196 } 1197 1198 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1199 { 1200 u32 phy_state, sl_ctrl, txid_auto; 1201 struct device *dev = hisi_hba->dev; 1202 1203 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1204 1205 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1206 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1207 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1208 1209 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1210 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1211 sl_ctrl&(~SL_CTA_MSK)); 1212 1213 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1214 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1215 txid_auto | CT3_MSK); 1216 1217 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1218 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1219 1220 return 0; 1221 } 1222 1223 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1224 { 1225 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1226 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1227 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1228 1229 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1230 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1231 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1232 CHL_INT0_SL_RX_BCST_ACK_MSK); 1233 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1234 } 1235 1236 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1237 { 1238 struct hisi_hba *hisi_hba = p; 1239 u32 irq_msk; 1240 int phy_no = 0; 1241 irqreturn_t res = IRQ_NONE; 1242 1243 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1244 & 0x11111111; 1245 while (irq_msk) { 1246 if (irq_msk & 1) { 1247 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1248 CHL_INT0); 1249 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1250 int rdy = phy_state & (1 << phy_no); 1251 1252 if (rdy) { 1253 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1254 /* phy up */ 1255 if (phy_up_v3_hw(phy_no, hisi_hba) 1256 == IRQ_HANDLED) 1257 res = IRQ_HANDLED; 1258 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1259 /* phy bcast */ 1260 phy_bcast_v3_hw(phy_no, hisi_hba); 1261 } else { 1262 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1263 /* phy down */ 1264 if (phy_down_v3_hw(phy_no, hisi_hba) 1265 == IRQ_HANDLED) 1266 res = IRQ_HANDLED; 1267 } 1268 } 1269 irq_msk >>= 4; 1270 phy_no++; 1271 } 1272 1273 return res; 1274 } 1275 1276 static const struct hisi_sas_hw_error port_axi_error[] = { 1277 { 1278 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1279 .msg = "dma_tx_axi_wr_err", 1280 }, 1281 { 1282 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1283 .msg = "dma_tx_axi_rd_err", 1284 }, 1285 { 1286 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1287 .msg = "dma_rx_axi_wr_err", 1288 }, 1289 { 1290 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1291 .msg = "dma_rx_axi_rd_err", 1292 }, 1293 }; 1294 1295 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1296 { 1297 struct hisi_hba *hisi_hba = p; 1298 struct device *dev = hisi_hba->dev; 1299 u32 ent_msk, ent_tmp, irq_msk; 1300 int phy_no = 0; 1301 1302 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1303 ent_tmp = ent_msk; 1304 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK; 1305 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk); 1306 1307 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1308 & 0xeeeeeeee; 1309 1310 while (irq_msk) { 1311 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1312 CHL_INT0); 1313 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1314 CHL_INT1); 1315 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1316 CHL_INT2); 1317 1318 if ((irq_msk & (4 << (phy_no * 4))) && 1319 irq_value1) { 1320 int i; 1321 1322 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1323 const struct hisi_sas_hw_error *error = 1324 &port_axi_error[i]; 1325 1326 if (!(irq_value1 & error->irq_msk)) 1327 continue; 1328 1329 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1330 error->msg, phy_no, irq_value1); 1331 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1332 } 1333 1334 hisi_sas_phy_write32(hisi_hba, phy_no, 1335 CHL_INT1, irq_value1); 1336 } 1337 1338 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) { 1339 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1340 1341 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1342 dev_warn(dev, "phy%d identify timeout\n", 1343 phy_no); 1344 hisi_sas_notify_phy_event(phy, 1345 HISI_PHYE_LINK_RESET); 1346 1347 } 1348 1349 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1350 u32 reg_value = hisi_sas_phy_read32(hisi_hba, 1351 phy_no, STP_LINK_TIMEOUT_STATE); 1352 1353 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1354 phy_no, reg_value); 1355 if (reg_value & BIT(4)) 1356 hisi_sas_notify_phy_event(phy, 1357 HISI_PHYE_LINK_RESET); 1358 } 1359 1360 hisi_sas_phy_write32(hisi_hba, phy_no, 1361 CHL_INT2, irq_value2); 1362 } 1363 1364 1365 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { 1366 hisi_sas_phy_write32(hisi_hba, phy_no, 1367 CHL_INT0, irq_value0 1368 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1369 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1370 & (~CHL_INT0_NOT_RDY_MSK)); 1371 } 1372 irq_msk &= ~(0xe << (phy_no * 4)); 1373 phy_no++; 1374 } 1375 1376 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp); 1377 1378 return IRQ_HANDLED; 1379 } 1380 1381 static const struct hisi_sas_hw_error axi_error[] = { 1382 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1383 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1384 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1385 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1386 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1387 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1388 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1389 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1390 {}, 1391 }; 1392 1393 static const struct hisi_sas_hw_error fifo_error[] = { 1394 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1395 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1396 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1397 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1398 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1399 {}, 1400 }; 1401 1402 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1403 { 1404 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1405 .msg = "write pointer and depth", 1406 }, 1407 { 1408 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1409 .msg = "iptt no match slot", 1410 }, 1411 { 1412 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1413 .msg = "read pointer and depth", 1414 }, 1415 { 1416 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1417 .reg = HGC_AXI_FIFO_ERR_INFO, 1418 .sub = axi_error, 1419 }, 1420 { 1421 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1422 .reg = HGC_AXI_FIFO_ERR_INFO, 1423 .sub = fifo_error, 1424 }, 1425 { 1426 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1427 .msg = "LM add/fetch list", 1428 }, 1429 { 1430 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1431 .msg = "SAS_HGC_ABT fetch LM list", 1432 }, 1433 }; 1434 1435 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1436 { 1437 u32 irq_value, irq_msk; 1438 struct hisi_hba *hisi_hba = p; 1439 struct device *dev = hisi_hba->dev; 1440 int i; 1441 1442 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1443 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1444 1445 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1446 1447 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1448 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1449 1450 if (!(irq_value & error->irq_msk)) 1451 continue; 1452 1453 if (error->sub) { 1454 const struct hisi_sas_hw_error *sub = error->sub; 1455 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1456 1457 for (; sub->msk || sub->msg; sub++) { 1458 if (!(err_value & sub->msk)) 1459 continue; 1460 1461 dev_err(dev, "%s error (0x%x) found!\n", 1462 sub->msg, irq_value); 1463 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1464 } 1465 } else { 1466 dev_err(dev, "%s error (0x%x) found!\n", 1467 error->msg, irq_value); 1468 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1469 } 1470 } 1471 1472 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1473 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1474 u32 dev_id = reg_val & ITCT_DEV_MSK; 1475 struct hisi_sas_device *sas_dev = 1476 &hisi_hba->devices[dev_id]; 1477 1478 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1479 dev_dbg(dev, "clear ITCT ok\n"); 1480 complete(sas_dev->completion); 1481 } 1482 1483 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1484 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1485 1486 return IRQ_HANDLED; 1487 } 1488 1489 static void 1490 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1491 struct hisi_sas_slot *slot) 1492 { 1493 struct task_status_struct *ts = &task->task_status; 1494 struct hisi_sas_complete_v3_hdr *complete_queue = 1495 hisi_hba->complete_hdr[slot->cmplt_queue]; 1496 struct hisi_sas_complete_v3_hdr *complete_hdr = 1497 &complete_queue[slot->cmplt_queue_slot]; 1498 struct hisi_sas_err_record_v3 *record = 1499 hisi_sas_status_buf_addr_mem(slot); 1500 u32 dma_rx_err_type = record->dma_rx_err_type; 1501 u32 trans_tx_fail_type = record->trans_tx_fail_type; 1502 1503 switch (task->task_proto) { 1504 case SAS_PROTOCOL_SSP: 1505 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1506 ts->residual = trans_tx_fail_type; 1507 ts->stat = SAS_DATA_UNDERRUN; 1508 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1509 ts->stat = SAS_QUEUE_FULL; 1510 slot->abort = 1; 1511 } else { 1512 ts->stat = SAS_OPEN_REJECT; 1513 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1514 } 1515 break; 1516 case SAS_PROTOCOL_SATA: 1517 case SAS_PROTOCOL_STP: 1518 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1519 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1520 ts->residual = trans_tx_fail_type; 1521 ts->stat = SAS_DATA_UNDERRUN; 1522 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1523 ts->stat = SAS_PHY_DOWN; 1524 slot->abort = 1; 1525 } else { 1526 ts->stat = SAS_OPEN_REJECT; 1527 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1528 } 1529 hisi_sas_sata_done(task, slot); 1530 break; 1531 case SAS_PROTOCOL_SMP: 1532 ts->stat = SAM_STAT_CHECK_CONDITION; 1533 break; 1534 default: 1535 break; 1536 } 1537 } 1538 1539 static int 1540 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1541 { 1542 struct sas_task *task = slot->task; 1543 struct hisi_sas_device *sas_dev; 1544 struct device *dev = hisi_hba->dev; 1545 struct task_status_struct *ts; 1546 struct domain_device *device; 1547 enum exec_status sts; 1548 struct hisi_sas_complete_v3_hdr *complete_queue = 1549 hisi_hba->complete_hdr[slot->cmplt_queue]; 1550 struct hisi_sas_complete_v3_hdr *complete_hdr = 1551 &complete_queue[slot->cmplt_queue_slot]; 1552 int aborted; 1553 unsigned long flags; 1554 1555 if (unlikely(!task || !task->lldd_task || !task->dev)) 1556 return -EINVAL; 1557 1558 ts = &task->task_status; 1559 device = task->dev; 1560 sas_dev = device->lldd_dev; 1561 1562 spin_lock_irqsave(&task->task_state_lock, flags); 1563 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED; 1564 task->task_state_flags &= 1565 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1566 spin_unlock_irqrestore(&task->task_state_lock, flags); 1567 1568 memset(ts, 0, sizeof(*ts)); 1569 ts->resp = SAS_TASK_COMPLETE; 1570 if (unlikely(aborted)) { 1571 dev_dbg(dev, "slot complete: task(%p) aborted\n", task); 1572 ts->stat = SAS_ABORTED_TASK; 1573 spin_lock_irqsave(&hisi_hba->lock, flags); 1574 hisi_sas_slot_task_free(hisi_hba, task, slot); 1575 spin_unlock_irqrestore(&hisi_hba->lock, flags); 1576 return -1; 1577 } 1578 1579 if (unlikely(!sas_dev)) { 1580 dev_dbg(dev, "slot complete: port has not device\n"); 1581 ts->stat = SAS_PHY_DOWN; 1582 goto out; 1583 } 1584 1585 /* 1586 * Use SAS+TMF status codes 1587 */ 1588 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1589 >> CMPLT_HDR_ABORT_STAT_OFF) { 1590 case STAT_IO_ABORTED: 1591 /* this IO has been aborted by abort command */ 1592 ts->stat = SAS_ABORTED_TASK; 1593 goto out; 1594 case STAT_IO_COMPLETE: 1595 /* internal abort command complete */ 1596 ts->stat = TMF_RESP_FUNC_SUCC; 1597 goto out; 1598 case STAT_IO_NO_DEVICE: 1599 ts->stat = TMF_RESP_FUNC_COMPLETE; 1600 goto out; 1601 case STAT_IO_NOT_VALID: 1602 /* 1603 * abort single IO, the controller can't find the IO 1604 */ 1605 ts->stat = TMF_RESP_FUNC_FAILED; 1606 goto out; 1607 default: 1608 break; 1609 } 1610 1611 /* check for erroneous completion */ 1612 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1613 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1614 1615 slot_err_v3_hw(hisi_hba, task, slot); 1616 if (ts->stat != SAS_DATA_UNDERRUN) 1617 dev_info(dev, "erroneous completion iptt=%d task=%p " 1618 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1619 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1620 slot->idx, task, 1621 complete_hdr->dw0, complete_hdr->dw1, 1622 complete_hdr->act, complete_hdr->dw3, 1623 error_info[0], error_info[1], 1624 error_info[2], error_info[3]); 1625 if (unlikely(slot->abort)) 1626 return ts->stat; 1627 goto out; 1628 } 1629 1630 switch (task->task_proto) { 1631 case SAS_PROTOCOL_SSP: { 1632 struct ssp_response_iu *iu = 1633 hisi_sas_status_buf_addr_mem(slot) + 1634 sizeof(struct hisi_sas_err_record); 1635 1636 sas_ssp_task_response(dev, task, iu); 1637 break; 1638 } 1639 case SAS_PROTOCOL_SMP: { 1640 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1641 void *to; 1642 1643 ts->stat = SAM_STAT_GOOD; 1644 to = kmap_atomic(sg_page(sg_resp)); 1645 1646 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1647 DMA_FROM_DEVICE); 1648 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1649 DMA_TO_DEVICE); 1650 memcpy(to + sg_resp->offset, 1651 hisi_sas_status_buf_addr_mem(slot) + 1652 sizeof(struct hisi_sas_err_record), 1653 sg_dma_len(sg_resp)); 1654 kunmap_atomic(to); 1655 break; 1656 } 1657 case SAS_PROTOCOL_SATA: 1658 case SAS_PROTOCOL_STP: 1659 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1660 ts->stat = SAM_STAT_GOOD; 1661 hisi_sas_sata_done(task, slot); 1662 break; 1663 default: 1664 ts->stat = SAM_STAT_CHECK_CONDITION; 1665 break; 1666 } 1667 1668 if (!slot->port->port_attached) { 1669 dev_warn(dev, "slot complete: port %d has removed\n", 1670 slot->port->sas_port.id); 1671 ts->stat = SAS_PHY_DOWN; 1672 } 1673 1674 out: 1675 spin_lock_irqsave(&task->task_state_lock, flags); 1676 task->task_state_flags |= SAS_TASK_STATE_DONE; 1677 spin_unlock_irqrestore(&task->task_state_lock, flags); 1678 spin_lock_irqsave(&hisi_hba->lock, flags); 1679 hisi_sas_slot_task_free(hisi_hba, task, slot); 1680 spin_unlock_irqrestore(&hisi_hba->lock, flags); 1681 sts = ts->stat; 1682 1683 if (task->task_done) 1684 task->task_done(task); 1685 1686 return sts; 1687 } 1688 1689 static void cq_tasklet_v3_hw(unsigned long val) 1690 { 1691 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1692 struct hisi_hba *hisi_hba = cq->hisi_hba; 1693 struct hisi_sas_slot *slot; 1694 struct hisi_sas_complete_v3_hdr *complete_queue; 1695 u32 rd_point = cq->rd_point, wr_point; 1696 int queue = cq->id; 1697 struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; 1698 1699 complete_queue = hisi_hba->complete_hdr[queue]; 1700 1701 spin_lock(&dq->lock); 1702 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1703 (0x14 * queue)); 1704 1705 while (rd_point != wr_point) { 1706 struct hisi_sas_complete_v3_hdr *complete_hdr; 1707 int iptt; 1708 1709 complete_hdr = &complete_queue[rd_point]; 1710 1711 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 1712 slot = &hisi_hba->slot_info[iptt]; 1713 slot->cmplt_queue_slot = rd_point; 1714 slot->cmplt_queue = queue; 1715 slot_complete_v3_hw(hisi_hba, slot); 1716 1717 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1718 rd_point = 0; 1719 } 1720 1721 /* update rd_point */ 1722 cq->rd_point = rd_point; 1723 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1724 spin_unlock(&dq->lock); 1725 } 1726 1727 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 1728 { 1729 struct hisi_sas_cq *cq = p; 1730 struct hisi_hba *hisi_hba = cq->hisi_hba; 1731 int queue = cq->id; 1732 1733 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1734 1735 tasklet_schedule(&cq->tasklet); 1736 1737 return IRQ_HANDLED; 1738 } 1739 1740 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 1741 { 1742 struct device *dev = hisi_hba->dev; 1743 struct pci_dev *pdev = hisi_hba->pci_dev; 1744 int vectors, rc; 1745 int i, k; 1746 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 1747 1748 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 1749 max_msi, PCI_IRQ_MSI); 1750 if (vectors < max_msi) { 1751 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 1752 return -ENOENT; 1753 } 1754 1755 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 1756 int_phy_up_down_bcast_v3_hw, 0, 1757 DRV_NAME " phy", hisi_hba); 1758 if (rc) { 1759 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 1760 rc = -ENOENT; 1761 goto free_irq_vectors; 1762 } 1763 1764 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 1765 int_chnl_int_v3_hw, 0, 1766 DRV_NAME " channel", hisi_hba); 1767 if (rc) { 1768 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 1769 rc = -ENOENT; 1770 goto free_phy_irq; 1771 } 1772 1773 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 1774 fatal_axi_int_v3_hw, 0, 1775 DRV_NAME " fatal", hisi_hba); 1776 if (rc) { 1777 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 1778 rc = -ENOENT; 1779 goto free_chnl_interrupt; 1780 } 1781 1782 /* Init tasklets for cq only */ 1783 for (i = 0; i < hisi_hba->queue_count; i++) { 1784 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 1785 struct tasklet_struct *t = &cq->tasklet; 1786 1787 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), 1788 cq_interrupt_v3_hw, 0, 1789 DRV_NAME " cq", cq); 1790 if (rc) { 1791 dev_err(dev, 1792 "could not request cq%d interrupt, rc=%d\n", 1793 i, rc); 1794 rc = -ENOENT; 1795 goto free_cq_irqs; 1796 } 1797 1798 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 1799 } 1800 1801 return 0; 1802 1803 free_cq_irqs: 1804 for (k = 0; k < i; k++) { 1805 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 1806 1807 free_irq(pci_irq_vector(pdev, k+16), cq); 1808 } 1809 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 1810 free_chnl_interrupt: 1811 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 1812 free_phy_irq: 1813 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 1814 free_irq_vectors: 1815 pci_free_irq_vectors(pdev); 1816 return rc; 1817 } 1818 1819 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 1820 { 1821 int rc; 1822 1823 rc = hw_init_v3_hw(hisi_hba); 1824 if (rc) 1825 return rc; 1826 1827 rc = interrupt_init_v3_hw(hisi_hba); 1828 if (rc) 1829 return rc; 1830 1831 return 0; 1832 } 1833 1834 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 1835 struct sas_phy_linkrates *r) 1836 { 1837 u32 prog_phy_link_rate = 1838 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE); 1839 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1840 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1841 int i; 1842 enum sas_linkrate min, max; 1843 u32 rate_mask = 0; 1844 1845 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) { 1846 max = sas_phy->phy->maximum_linkrate; 1847 min = r->minimum_linkrate; 1848 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) { 1849 max = r->maximum_linkrate; 1850 min = sas_phy->phy->minimum_linkrate; 1851 } else 1852 return; 1853 1854 sas_phy->phy->maximum_linkrate = max; 1855 sas_phy->phy->minimum_linkrate = min; 1856 1857 max -= SAS_LINK_RATE_1_5_GBPS; 1858 1859 for (i = 0; i <= max; i++) 1860 rate_mask |= 1 << (i * 2); 1861 1862 prog_phy_link_rate &= ~0xff; 1863 prog_phy_link_rate |= rate_mask; 1864 1865 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1866 prog_phy_link_rate); 1867 1868 phy_hard_reset_v3_hw(hisi_hba, phy_no); 1869 } 1870 1871 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 1872 { 1873 struct pci_dev *pdev = hisi_hba->pci_dev; 1874 int i; 1875 1876 synchronize_irq(pci_irq_vector(pdev, 1)); 1877 synchronize_irq(pci_irq_vector(pdev, 2)); 1878 synchronize_irq(pci_irq_vector(pdev, 11)); 1879 for (i = 0; i < hisi_hba->queue_count; i++) { 1880 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 1881 synchronize_irq(pci_irq_vector(pdev, i + 16)); 1882 } 1883 1884 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 1885 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 1886 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 1887 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 1888 1889 for (i = 0; i < hisi_hba->n_phy; i++) { 1890 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 1891 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 1892 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 1893 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 1894 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 1895 } 1896 } 1897 1898 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 1899 { 1900 return hisi_sas_read32(hisi_hba, PHY_STATE); 1901 } 1902 1903 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1904 { 1905 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1906 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1907 struct sas_phy *sphy = sas_phy->phy; 1908 u32 reg_value; 1909 1910 /* loss dword sync */ 1911 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1912 sphy->loss_of_dword_sync_count += reg_value; 1913 1914 /* phy reset problem */ 1915 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1916 sphy->phy_reset_problem_count += reg_value; 1917 1918 /* invalid dword */ 1919 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1920 sphy->invalid_dword_count += reg_value; 1921 1922 /* disparity err */ 1923 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1924 sphy->running_disparity_error_count += reg_value; 1925 1926 } 1927 1928 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 1929 { 1930 struct device *dev = hisi_hba->dev; 1931 int rc; 1932 u32 status; 1933 1934 interrupt_disable_v3_hw(hisi_hba); 1935 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 1936 hisi_sas_kill_tasklets(hisi_hba); 1937 1938 hisi_sas_stop_phys(hisi_hba); 1939 1940 mdelay(10); 1941 1942 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); 1943 1944 /* wait until bus idle */ 1945 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE + 1946 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100); 1947 if (rc) { 1948 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 1949 return rc; 1950 } 1951 1952 hisi_sas_init_mem(hisi_hba); 1953 1954 return hw_init_v3_hw(hisi_hba); 1955 } 1956 1957 static const struct hisi_sas_hw hisi_sas_v3_hw = { 1958 .hw_init = hisi_sas_v3_init, 1959 .setup_itct = setup_itct_v3_hw, 1960 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 1961 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 1962 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 1963 .clear_itct = clear_itct_v3_hw, 1964 .sl_notify = sl_notify_v3_hw, 1965 .prep_ssp = prep_ssp_v3_hw, 1966 .prep_smp = prep_smp_v3_hw, 1967 .prep_stp = prep_ata_v3_hw, 1968 .prep_abort = prep_abort_v3_hw, 1969 .get_free_slot = get_free_slot_v3_hw, 1970 .start_delivery = start_delivery_v3_hw, 1971 .slot_complete = slot_complete_v3_hw, 1972 .phys_init = phys_init_v3_hw, 1973 .phy_start = start_phy_v3_hw, 1974 .phy_disable = disable_phy_v3_hw, 1975 .phy_hard_reset = phy_hard_reset_v3_hw, 1976 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 1977 .phy_set_linkrate = phy_set_linkrate_v3_hw, 1978 .dereg_device = dereg_device_v3_hw, 1979 .soft_reset = soft_reset_v3_hw, 1980 .get_phys_state = get_phys_state_v3_hw, 1981 .get_events = phy_get_events_v3_hw, 1982 }; 1983 1984 static struct Scsi_Host * 1985 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 1986 { 1987 struct Scsi_Host *shost; 1988 struct hisi_hba *hisi_hba; 1989 struct device *dev = &pdev->dev; 1990 1991 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba)); 1992 if (!shost) { 1993 dev_err(dev, "shost alloc failed\n"); 1994 return NULL; 1995 } 1996 hisi_hba = shost_priv(shost); 1997 1998 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 1999 hisi_hba->hw = &hisi_sas_v3_hw; 2000 hisi_hba->pci_dev = pdev; 2001 hisi_hba->dev = dev; 2002 hisi_hba->shost = shost; 2003 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2004 2005 timer_setup(&hisi_hba->timer, NULL, 0); 2006 2007 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2008 goto err_out; 2009 2010 if (hisi_sas_alloc(hisi_hba, shost)) { 2011 hisi_sas_free(hisi_hba); 2012 goto err_out; 2013 } 2014 2015 return shost; 2016 err_out: 2017 scsi_host_put(shost); 2018 dev_err(dev, "shost alloc failed\n"); 2019 return NULL; 2020 } 2021 2022 static int 2023 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2024 { 2025 struct Scsi_Host *shost; 2026 struct hisi_hba *hisi_hba; 2027 struct device *dev = &pdev->dev; 2028 struct asd_sas_phy **arr_phy; 2029 struct asd_sas_port **arr_port; 2030 struct sas_ha_struct *sha; 2031 int rc, phy_nr, port_nr, i; 2032 2033 rc = pci_enable_device(pdev); 2034 if (rc) 2035 goto err_out; 2036 2037 pci_set_master(pdev); 2038 2039 rc = pci_request_regions(pdev, DRV_NAME); 2040 if (rc) 2041 goto err_out_disable_device; 2042 2043 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 2044 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 2045 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 2046 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { 2047 dev_err(dev, "No usable DMA addressing method\n"); 2048 rc = -EIO; 2049 goto err_out_regions; 2050 } 2051 } 2052 2053 shost = hisi_sas_shost_alloc_pci(pdev); 2054 if (!shost) { 2055 rc = -ENOMEM; 2056 goto err_out_regions; 2057 } 2058 2059 sha = SHOST_TO_SAS_HA(shost); 2060 hisi_hba = shost_priv(shost); 2061 dev_set_drvdata(dev, sha); 2062 2063 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2064 if (!hisi_hba->regs) { 2065 dev_err(dev, "cannot map register.\n"); 2066 rc = -ENOMEM; 2067 goto err_out_ha; 2068 } 2069 2070 phy_nr = port_nr = hisi_hba->n_phy; 2071 2072 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2073 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2074 if (!arr_phy || !arr_port) { 2075 rc = -ENOMEM; 2076 goto err_out_ha; 2077 } 2078 2079 sha->sas_phy = arr_phy; 2080 sha->sas_port = arr_port; 2081 sha->core.shost = shost; 2082 sha->lldd_ha = hisi_hba; 2083 2084 shost->transportt = hisi_sas_stt; 2085 shost->max_id = HISI_SAS_MAX_DEVICES; 2086 shost->max_lun = ~0; 2087 shost->max_channel = 1; 2088 shost->max_cmd_len = 16; 2089 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); 2090 shost->can_queue = hisi_hba->hw->max_command_entries; 2091 shost->cmd_per_lun = hisi_hba->hw->max_command_entries; 2092 2093 sha->sas_ha_name = DRV_NAME; 2094 sha->dev = dev; 2095 sha->lldd_module = THIS_MODULE; 2096 sha->sas_addr = &hisi_hba->sas_addr[0]; 2097 sha->num_phys = hisi_hba->n_phy; 2098 sha->core.shost = hisi_hba->shost; 2099 2100 for (i = 0; i < hisi_hba->n_phy; i++) { 2101 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2102 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2103 } 2104 2105 hisi_sas_init_add(hisi_hba); 2106 2107 rc = scsi_add_host(shost, dev); 2108 if (rc) 2109 goto err_out_ha; 2110 2111 rc = sas_register_ha(sha); 2112 if (rc) 2113 goto err_out_register_ha; 2114 2115 rc = hisi_hba->hw->hw_init(hisi_hba); 2116 if (rc) 2117 goto err_out_register_ha; 2118 2119 scsi_scan_host(shost); 2120 2121 return 0; 2122 2123 err_out_register_ha: 2124 scsi_remove_host(shost); 2125 err_out_ha: 2126 scsi_host_put(shost); 2127 err_out_regions: 2128 pci_release_regions(pdev); 2129 err_out_disable_device: 2130 pci_disable_device(pdev); 2131 err_out: 2132 return rc; 2133 } 2134 2135 static void 2136 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2137 { 2138 int i; 2139 2140 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2141 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2142 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2143 for (i = 0; i < hisi_hba->queue_count; i++) { 2144 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2145 2146 free_irq(pci_irq_vector(pdev, i+16), cq); 2147 } 2148 pci_free_irq_vectors(pdev); 2149 } 2150 2151 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2152 { 2153 struct device *dev = &pdev->dev; 2154 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2155 struct hisi_hba *hisi_hba = sha->lldd_ha; 2156 struct Scsi_Host *shost = sha->core.shost; 2157 2158 sas_unregister_ha(sha); 2159 sas_remove_host(sha->core.shost); 2160 2161 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2162 hisi_sas_kill_tasklets(hisi_hba); 2163 pci_release_regions(pdev); 2164 pci_disable_device(pdev); 2165 hisi_sas_free(hisi_hba); 2166 scsi_host_put(shost); 2167 } 2168 2169 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2170 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2171 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2172 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2173 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2174 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2175 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2176 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2177 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2178 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2179 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2180 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2181 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2182 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2183 }; 2184 2185 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2186 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2187 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2188 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2189 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2190 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2191 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2192 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2193 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2194 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2195 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2196 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2197 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2198 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2199 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2200 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2201 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2202 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2203 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2204 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2205 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2206 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2207 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2208 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2209 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2210 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2211 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2212 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2213 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2214 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2215 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2216 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2217 }; 2218 2219 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2220 { 2221 struct device *dev = hisi_hba->dev; 2222 const struct hisi_sas_hw_error *ras_error; 2223 bool need_reset = false; 2224 u32 irq_value; 2225 int i; 2226 2227 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2228 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2229 ras_error = &sas_ras_intr0_nfe[i]; 2230 if (ras_error->irq_msk & irq_value) { 2231 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2232 ras_error->msg, irq_value); 2233 need_reset = true; 2234 } 2235 } 2236 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2237 2238 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2239 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2240 ras_error = &sas_ras_intr1_nfe[i]; 2241 if (ras_error->irq_msk & irq_value) { 2242 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2243 ras_error->msg, irq_value); 2244 need_reset = true; 2245 } 2246 } 2247 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2248 2249 return need_reset; 2250 } 2251 2252 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2253 pci_channel_state_t state) 2254 { 2255 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2256 struct hisi_hba *hisi_hba = sha->lldd_ha; 2257 struct device *dev = hisi_hba->dev; 2258 2259 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2260 if (state == pci_channel_io_perm_failure) 2261 return PCI_ERS_RESULT_DISCONNECT; 2262 2263 if (process_non_fatal_error_v3_hw(hisi_hba)) 2264 return PCI_ERS_RESULT_NEED_RESET; 2265 2266 return PCI_ERS_RESULT_CAN_RECOVER; 2267 } 2268 2269 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2270 { 2271 return PCI_ERS_RESULT_RECOVERED; 2272 } 2273 2274 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2275 { 2276 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2277 struct hisi_hba *hisi_hba = sha->lldd_ha; 2278 struct device *dev = hisi_hba->dev; 2279 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2280 2281 dev_info(dev, "PCI error: slot reset callback!!\n"); 2282 queue_work(hisi_hba->wq, &r.work); 2283 wait_for_completion(r.completion); 2284 if (r.done) 2285 return PCI_ERS_RESULT_RECOVERED; 2286 2287 return PCI_ERS_RESULT_DISCONNECT; 2288 } 2289 2290 enum { 2291 /* instances of the controller */ 2292 hip08, 2293 }; 2294 2295 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 2296 { 2297 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2298 struct hisi_hba *hisi_hba = sha->lldd_ha; 2299 struct device *dev = hisi_hba->dev; 2300 struct Scsi_Host *shost = hisi_hba->shost; 2301 u32 device_state, status; 2302 int rc; 2303 u32 reg_val; 2304 unsigned long flags; 2305 2306 if (!pdev->pm_cap) { 2307 dev_err(dev, "PCI PM not supported\n"); 2308 return -ENODEV; 2309 } 2310 2311 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2312 scsi_block_requests(shost); 2313 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2314 flush_workqueue(hisi_hba->wq); 2315 /* disable DQ/PHY/bus */ 2316 interrupt_disable_v3_hw(hisi_hba); 2317 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2318 hisi_sas_kill_tasklets(hisi_hba); 2319 2320 hisi_sas_stop_phys(hisi_hba); 2321 2322 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2323 AM_CTRL_GLOBAL); 2324 reg_val |= 0x1; 2325 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2326 AM_CTRL_GLOBAL, reg_val); 2327 2328 /* wait until bus idle */ 2329 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE + 2330 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100); 2331 if (rc) { 2332 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 2333 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2334 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2335 scsi_unblock_requests(shost); 2336 return rc; 2337 } 2338 2339 hisi_sas_init_mem(hisi_hba); 2340 2341 device_state = pci_choose_state(pdev, state); 2342 dev_warn(dev, "entering operating state [D%d]\n", 2343 device_state); 2344 pci_save_state(pdev); 2345 pci_disable_device(pdev); 2346 pci_set_power_state(pdev, device_state); 2347 2348 spin_lock_irqsave(&hisi_hba->lock, flags); 2349 hisi_sas_release_tasks(hisi_hba); 2350 spin_unlock_irqrestore(&hisi_hba->lock, flags); 2351 2352 sas_suspend_ha(sha); 2353 return 0; 2354 } 2355 2356 static int hisi_sas_v3_resume(struct pci_dev *pdev) 2357 { 2358 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2359 struct hisi_hba *hisi_hba = sha->lldd_ha; 2360 struct Scsi_Host *shost = hisi_hba->shost; 2361 struct device *dev = hisi_hba->dev; 2362 unsigned int rc; 2363 u32 device_state = pdev->current_state; 2364 2365 dev_warn(dev, "resuming from operating state [D%d]\n", 2366 device_state); 2367 pci_set_power_state(pdev, PCI_D0); 2368 pci_enable_wake(pdev, PCI_D0, 0); 2369 pci_restore_state(pdev); 2370 rc = pci_enable_device(pdev); 2371 if (rc) 2372 dev_err(dev, "enable device failed during resume (%d)\n", rc); 2373 2374 pci_set_master(pdev); 2375 scsi_unblock_requests(shost); 2376 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2377 2378 sas_prep_resume_ha(sha); 2379 init_reg_v3_hw(hisi_hba); 2380 hisi_hba->hw->phys_init(hisi_hba); 2381 sas_resume_ha(sha); 2382 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2383 2384 return 0; 2385 } 2386 2387 static const struct pci_device_id sas_v3_pci_table[] = { 2388 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 2389 {} 2390 }; 2391 2392 static const struct pci_error_handlers hisi_sas_err_handler = { 2393 .error_detected = hisi_sas_error_detected_v3_hw, 2394 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 2395 .slot_reset = hisi_sas_slot_reset_v3_hw, 2396 }; 2397 2398 static struct pci_driver sas_v3_pci_driver = { 2399 .name = DRV_NAME, 2400 .id_table = sas_v3_pci_table, 2401 .probe = hisi_sas_v3_probe, 2402 .remove = hisi_sas_v3_remove, 2403 .suspend = hisi_sas_v3_suspend, 2404 .resume = hisi_sas_v3_resume, 2405 .err_handler = &hisi_sas_err_handler, 2406 }; 2407 2408 module_pci_driver(sas_v3_pci_driver); 2409 2410 MODULE_LICENSE("GPL"); 2411 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2412 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 2413 MODULE_ALIAS("platform:" DRV_NAME); 2414