net: dsa: mv88e6xxx: prefix Port Control 1 macros

For implicit namespacing and clarity, prefix the common Port Control 1
Register macros with MV88E6XXX_PORT_CTL1.

Document the r

net: dsa: mv88e6xxx: prefix Port Control 1 macros

For implicit namespacing and clarity, prefix the common Port Control 1
Register macros with MV88E6XXX_PORT_CTL1.

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: prefix Port Control macros

For implicit namespacing and clarity, prefix the common Port Control
Register macros with MV88E6XXX_PORT_CTL0 and the ones which differ

net: dsa: mv88e6xxx: prefix Port Control macros

For implicit namespacing and clarity, prefix the common Port Control
Register macros with MV88E6XXX_PORT_CTL0 and the ones which differ
between implementations with a chosen reference model
(e.g. MV88E6185_PORT_CTL0_USE_TAG.)

The reason for CTL0 is to make it clear between the badly named
"Port Control", "Port Control 1" and "Port Control 2" registers.

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: prefix Port Switch ID macros

For implicit namespacing and clarity, prefix the common Switch ID
Register macros with MV88E6XXX_PORT_SWITCH_ID.

Document the r

net: dsa: mv88e6xxx: prefix Port Switch ID macros

For implicit namespacing and clarity, prefix the common Switch ID
Register macros with MV88E6XXX_PORT_SWITCH_ID.

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers, this means shifting their values by 4.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: prefix Port Jamming macros

For implicit namespacing and clarity, prefix the common Port Jamming
Control Register macros with MV88E6XXX_PORT_JAM_CTL and the ones whic

net: dsa: mv88e6xxx: prefix Port Jamming macros

For implicit namespacing and clarity, prefix the common Port Jamming
Control Register macros with MV88E6XXX_PORT_JAM_CTL and the ones which
differ between implementations with a chosen reference model
(e.g. MV88E6097_PORT_JAM_CTL.)

The 88E6390 family renamed the register to Flow Control and turned it
into an indirect table. Document that as well.

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: prefix Port MAC Control macros

For implicit namespacing and clarity, prefix the common MAC Control
Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which dif

net: dsa: mv88e6xxx: prefix Port MAC Control macros

For implicit namespacing and clarity, prefix the common MAC Control
Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which differ
between implementations with a chosen reference model
(e.g. MV88E6065_PORT_MAC_CTL_SPEED_200.)

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: prefix Port Status macros

For implicit namespacing and clarity, prefix the common Port Status
Register macros with MV88E6XXX_PORT_STS and the ones which differ
b

net: dsa: mv88e6xxx: prefix Port Status macros

For implicit namespacing and clarity, prefix the common Port Status
Register macros with MV88E6XXX_PORT_STS and the ones which differ
between implementations with a chosen reference model
(e.g. MV88E6352_PORT_STS_EEE.)

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: rework jumbo size operation

Marvell chips have a Jumbo Mode to set the maximum frame size (MTU).

The mv88e6xxx_ops structure is meant to contain generic functio

net: dsa: mv88e6xxx: rework jumbo size operation

Marvell chips have a Jumbo Mode to set the maximum frame size (MTU).

The mv88e6xxx_ops structure is meant to contain generic functionalities,
no driver logic. Change port_jumbo_config to port_set_jumbo_size setting
the mode from a given maximum size value.

There is no functional changes since we still use 10240 bytes.

At the same time, correctly clear all Jumbo Mode bits before writing.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: rework pause limit operation

All Marvell chips supporting Pause frames limiting use 1-byte value for
input and output.

Old chips have both bytes adjacent in

net: dsa: mv88e6xxx: rework pause limit operation

All Marvell chips supporting Pause frames limiting use 1-byte value for
input and output.

Old chips have both bytes adjacent in a 16-bit register. New ones have
an indirect table using 8-bit data.

The mv88e6xxx library functions (such as in port.c) must not contain
driver logic, but only generic helpers. This patch changes the
port_pause_config operation for port_pause_limit taking two u8 arguments
for input and output limits. There is no functional changes.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: add egress mode enumeration

As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead
of a 16-bit register mask.

Reviewed-by: Andrew Lunn <andr

net: dsa: mv88e6xxx: add egress mode enumeration

As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead
of a 16-bit register mask.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: move the Port macros

Move the PORT_* macros where they belong, in the related port.h header.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>

net: dsa: mv88e6xxx: move the Port macros

Move the PORT_* macros where they belong, in the related port.h header.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: rename chip header

The mv88e6xxx.h is meant to contains the chip structures and data.
Rename it to chip.h, as for other source/header pairs of the driver.

A

net: dsa: mv88e6xxx: rename chip header

The mv88e6xxx.h is meant to contains the chip structures and data.
Rename it to chip.h, as for other source/header pairs of the driver.

At the same time, ensure that relative header inclusions are separated
by a newline and sorted alphabetically.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: fix copyright holder

I do not hold the copyright of the DSA core and drivers source files,
since these changes have been written as an initiative of my day job.
Fix this.

net: dsa: fix copyright holder

I do not hold the copyright of the DSA core and drivers source files,
since these changes have been written as an initiative of my day job.
Fix this.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: add port priority override op

Add a new operation to disable the DA, SA and VTU priority override.

Setting such limit is not likely to be used soon, so provide

net: dsa: mv88e6xxx: add port priority override op

Add a new operation to disable the DA, SA and VTU priority override.

Setting such limit is not likely to be used soon, so provide a
port_disable_pri_override operation directly. This can be changed later
for port_set_pri_override when we'll need it.

Also remove the now obsolete mv88e6xxx_6320_family helper.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: add port ATU learn limit op

Add a new operation to disable the limiting of learnt MAC addresses.

Setting such limit is not likely to be used soon, so provide a

net: dsa: mv88e6xxx: add port ATU learn limit op

Add a new operation to disable the limiting of learnt MAC addresses.

Setting such limit is not likely to be used soon, so provide a
port_disable_learn_limit operation directly. This can be changed later
for port_set_learn_limit when we'll need it.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: fix port egress flooding mode

The Marvell switch ports can be configured to allow or prevent egress of
frames with an unknown unicast or multicast destination addres

net: dsa: mv88e6xxx: fix port egress flooding mode

The Marvell switch ports can be configured to allow or prevent egress of
frames with an unknown unicast or multicast destination address.

Some switch chips such as 88E6095 and 88E6185 have two disjoint bits in
Port Control Register (0x04) bit 2 "Forward Unknown" (for unicast) and
Port Control 2 Register (0x08) bit 6 "Default Forward" (for multicast).

Other chips such as 88E6085, 88E6123, 88E6352, and 88E6390 have a 2-bit
value in Port Control Register (0x04) bits 3:2 "EgressFloods".

The current code does not fully implement the disjoint bits variant and
assigns incorrect ones to some chip models. Fix that with two
implementation references (6185 and 6352 that I currently have) of a
port_set_egress_floods operation (as named in datasheets).

Old chips such as 88E6060 don't have egress flooding mode, so don't
error out if the operation is not provided.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: setup message ports

All interconnectable Marvell switch chips have an ATU Learn2All feature
which allows newly learnt addresses to be spanned on ports marked as

net: dsa: mv88e6xxx: setup message ports

All interconnectable Marvell switch chips have an ATU Learn2All feature
which allows newly learnt addresses to be spanned on ports marked as
"Message Port".

This commit configures the DSA ports as Message Port. Note that this has
no effect until the Learn2All feature is enabled.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Refactor remaining port setup

Move the remaining port configuration code which varies per device
into port.c, using ops were necessary. This makes
mv88e6xxx_6185

net: dsa: mv88e6xxx: Refactor remaining port setup

Move the remaining port configuration code which varies per device
into port.c, using ops were necessary. This makes
mv88e6xxx_6185_family() and mv88e6xxx_6095_family() unused, so remove
them.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Set the CMODE for mv88e6390 ports 9 & 10

Unlike most ports, ports 9 and 10 of the 6390X family have configurable
PHY modes. Set the mode as part of adjust_link().

net: dsa: mv88e6xxx: Set the CMODE for mv88e6390 ports 9 & 10

Unlike most ports, ports 9 and 10 of the 6390X family have configurable
PHY modes. Set the mode as part of adjust_link().

Ordering is important, because the SERDES interfaces connected to
ports 9 and 10 can be split and assigned to other ports. The CMODE has
to be correctly set before the SERDES interface on another port can be
configured. Such configuration is likely to be performed in
port_enable() and port_disabled(), called on slave_open() and
slave_close().

The simple case is port 9 and 10 are used for 'CPU' or 'DSA'. In this
case, the CMODE is set via a phy-mode in dsa_cpu_dsa_setup(), which is
called early in the switch setup.

When ports 9 or 10 are used as user ports, and have a fixed-phy, when
the fixed fixed-phy is attached, dsa_slave_adjust_link() is called,
which results in the adjust_link function being called, setting the
cmode. The port_enable() will for other ports will be called much
later.

When ports 9 or 10 are used as user ports and have a real phy attached
which does not use all the available SERDES interface, e.g. a 1Gbps
SGMII, there is currently no mechanism in place to set the CMODE of
the port from software. It must be hoped the stripping resistors are
correct.

At the same time, add a function to get the cmode. This will be needed
when configuring the SERDES interfaces.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Implement mv88e6390 pause control

The mv88e6390 has a number flow control registers accessed via the
Flow Control register. Use these to set the pause control.

net: dsa: mv88e6xxx: Implement mv88e6390 pause control

The mv88e6390 has a number flow control registers accessed via the
Flow Control register. Use these to set the pause control.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Refactor pause configuration

The mv88e6390 has a different mechanism for configuring pause.
Refactor the code into an ops function, and for the moment, don't add

net: dsa: mv88e6xxx: Refactor pause configuration

The mv88e6390 has a different mechanism for configuring pause.
Refactor the code into an ops function, and for the moment, don't add
any mv88e6390 code yet.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Refactor egress rate limiting

There are two different rate limiting configurations, depending on the
switch generation. Refactor this into ops.

Signed-off-b

net: dsa: mv88e6xxx: Refactor egress rate limiting

There are two different rate limiting configurations, depending on the
switch generation. Refactor this into ops.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Refactor setting of jumbo frames

Some switches support jumbo frames. Refactor this code into operations
in the ops structure.

Signed-off-by: Andrew Lunn <an

net: dsa: mv88e6xxx: Refactor setting of jumbo frames

Some switches support jumbo frames. Refactor this code into operations
in the ops structure.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Refactor CPU and DSA port setup

Older chips only support DSA tagging. Newer chips have both DSA and
EDSA tagging. Refactor the code by adding port functions for sett

net: dsa: mv88e6xxx: Refactor CPU and DSA port setup

Older chips only support DSA tagging. Newer chips have both DSA and
EDSA tagging. Refactor the code by adding port functions for setting the
frame mode, egress mode, and if to forward unknown frames.

This results in the helper mv88e6xxx_6065_family() becoming unused, so
remove it.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
v3:
Verify mandatory ops for port setup
Don't set ether type for DSA port.
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: Implement mv88e6390 tag remap

The mv88e6390 does not have the two registers to set the frame
priority map. Instead it has an indirection registers for setting a

net: dsa: mv88e6xxx: Implement mv88e6390 tag remap

The mv88e6390 does not have the two registers to set the frame
priority map. Instead it has an indirection registers for setting a
number of different priority maps. Refactor the old code into an
function, implement the mv88e6390 version, and use an op to call the
right one.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: dsa: mv88e6xxx: add port's MAC speed setter

While the two bits for link, duplex or RGMII delays are used the same
way on chips supporting the said feature, the two bits for speed ha

net: dsa: mv88e6xxx: add port's MAC speed setter

While the two bits for link, duplex or RGMII delays are used the same
way on chips supporting the said feature, the two bits for speed have
different meaning for most of the chips out there.

Speed value is stored in bits 1:0, 0x3 means unforce (normal detection).

Some chips reuse values for alternative speeds when bit 12 is set.

Newer chips with speed > 1Gbps reuse value 0x3 thus need a new bit 13.

Here are the values to write in register 0x1 to (un)force speed:

| Speed | 88E6065 | 88E6185 | 88E6352 | 88E6390 | 88E6390X |
| ------- | ------- | ------- | ------- | ------- | -------- |
| 10 | 0x0000 | 0x0000 | 0x0000 | 0x2000 | 0x2000 |
| 100 | 0x0001 | 0x0001 | 0x0001 | 0x2001 | 0x2001 |
| 200 | 0x0002 | NA | 0x1001 | 0x3001 | 0x3001 |
| 1000 | NA | 0x0002 | 0x0002 | 0x2002 | 0x2002 |
| 2500 | NA | NA | NA | 0x3003 | 0x3003 |
| 10000 | NA | NA | NA | NA | 0x2003 |
| unforce | 0x0003 | 0x0003 | 0x0003 | 0x0000 | 0x0000 |

This patch implements a generic mv88e6xxx_port_set_speed() function used
by chip-specific wrappers to filter supported ports and speeds.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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