1 /* 2 * Marvell 88E6xxx Switch Port Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_PORT_H 16 #define _MV88E6XXX_PORT_H 17 18 #include "chip.h" 19 20 /* Offset 0x00: Port Status Register */ 21 #define MV88E6XXX_PORT_STS 0x00 22 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 23 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 24 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 25 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 26 #define MV88E6XXX_PORT_STS_LINK 0x0800 27 #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 28 #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 29 #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 30 #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 31 #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 32 #define MV88E6352_PORT_STS_EEE 0x0040 33 #define MV88E6165_PORT_STS_AM_DIS 0x0040 34 #define MV88E6185_PORT_STS_MGMII 0x0040 35 #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 36 #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 37 #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 38 #define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008 39 #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009 40 #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 41 #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 42 #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 43 #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 44 45 /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 46 #define MV88E6XXX_PORT_MAC_CTL 0x01 47 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 48 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 49 #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 50 #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 51 #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 52 #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 53 #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 54 #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 55 #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 56 #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 57 #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 58 #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 59 #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 60 #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 61 #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 62 #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 63 #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 64 #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 65 66 /* Offset 0x02: Jamming Control Register */ 67 #define MV88E6097_PORT_JAM_CTL 0x02 68 #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 69 #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 70 71 /* Offset 0x02: Flow Control Register */ 72 #define MV88E6390_PORT_FLOW_CTL 0x02 73 #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 74 #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 75 #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 76 #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 77 #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 78 79 /* Offset 0x03: Switch Identifier Register */ 80 #define MV88E6XXX_PORT_SWITCH_ID 0x03 81 #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 82 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 83 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 84 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 85 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 86 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 87 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 88 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 89 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 90 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 91 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 92 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 93 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 94 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 95 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 96 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 97 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 98 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 99 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 100 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 101 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 102 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 103 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 104 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 105 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 106 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 107 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 108 #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 109 110 /* Offset 0x04: Port Control Register */ 111 #define MV88E6XXX_PORT_CTL0 0x04 112 #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 113 #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000 114 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 115 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 116 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 117 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 118 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 119 #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 120 #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 121 #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 122 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 123 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 124 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 125 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 126 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 127 #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 128 #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 129 #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 130 #define MV88E6185_PORT_CTL0_USE_IP 0x0020 131 #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 132 #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 133 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c 134 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000 135 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004 136 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008 137 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c 138 #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 139 #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 140 #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 141 #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 142 #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 143 144 #define PORT_CONTROL_1 0x05 145 #define PORT_CONTROL_1_MESSAGE_PORT BIT(15) 146 #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) 147 #define PORT_BASE_VLAN 0x06 148 #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) 149 #define PORT_DEFAULT_VLAN 0x07 150 #define PORT_DEFAULT_VLAN_MASK 0xfff 151 #define PORT_CONTROL_2 0x08 152 #define PORT_CONTROL_2_IGNORE_FCS BIT(15) 153 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) 154 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) 155 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) 156 #define PORT_CONTROL_2_JUMBO_MASK (0x03 << 12) 157 #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) 158 #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) 159 #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) 160 #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) 161 #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) 162 #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) 163 #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) 164 #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) 165 #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) 166 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) 167 #define PORT_CONTROL_2_MAP_DA BIT(7) 168 #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) 169 #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) 170 #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) 171 #define PORT_CONTROL_2_UPSTREAM_MASK 0x0f 172 #define PORT_RATE_CONTROL 0x09 173 #define PORT_RATE_CONTROL_2 0x0a 174 #define PORT_ASSOC_VECTOR 0x0b 175 #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) 176 #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) 177 #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) 178 #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) 179 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) 180 #define PORT_ATU_CONTROL 0x0c 181 #define PORT_PRI_OVERRIDE 0x0d 182 #define PORT_ETH_TYPE 0x0f 183 #define PORT_ETH_TYPE_DEFAULT 0x9100 184 #define PORT_IN_DISCARD_LO 0x10 185 #define PORT_IN_DISCARD_HI 0x11 186 #define PORT_IN_FILTERED 0x12 187 #define PORT_OUT_FILTERED 0x13 188 #define PORT_TAG_REGMAP_0123 0x18 189 #define PORT_TAG_REGMAP_4567 0x19 190 #define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */ 191 #define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15) 192 #define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12) 193 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12) 194 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12) 195 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12) 196 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12) 197 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12) 198 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12) 199 #define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9 200 201 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 202 u16 *val); 203 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 204 u16 val); 205 206 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 207 phy_interface_t mode); 208 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 209 phy_interface_t mode); 210 211 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 212 213 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 214 215 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 216 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 217 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 218 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 219 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 220 221 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 222 223 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 224 225 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 226 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 227 228 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 229 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 230 231 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 232 u16 mode); 233 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 234 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 235 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 236 enum mv88e6xxx_egress_mode mode); 237 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 238 enum mv88e6xxx_frame_mode mode); 239 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 240 enum mv88e6xxx_frame_mode mode); 241 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 242 bool unicast, bool multicast); 243 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 244 bool unicast, bool multicast); 245 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 246 u16 etype); 247 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 248 bool message_port); 249 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 250 size_t size); 251 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 252 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 253 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 254 u8 out); 255 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 256 u8 out); 257 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 258 phy_interface_t mode); 259 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 260 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 261 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 262 int upstream_port); 263 264 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 265 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 266 267 #endif /* _MV88E6XXX_PORT_H */ 268