1 /* 2 * Marvell 88E6xxx Switch Port Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_PORT_H 16 #define _MV88E6XXX_PORT_H 17 18 #include "chip.h" 19 20 #define PORT_STATUS 0x00 21 #define PORT_STATUS_PAUSE_EN BIT(15) 22 #define PORT_STATUS_MY_PAUSE BIT(14) 23 #define PORT_STATUS_HD_FLOW BIT(13) 24 #define PORT_STATUS_PHY_DETECT BIT(12) 25 #define PORT_STATUS_LINK BIT(11) 26 #define PORT_STATUS_DUPLEX BIT(10) 27 #define PORT_STATUS_SPEED_MASK 0x0300 28 #define PORT_STATUS_SPEED_10 0x0000 29 #define PORT_STATUS_SPEED_100 0x0100 30 #define PORT_STATUS_SPEED_1000 0x0200 31 #define PORT_STATUS_EEE BIT(6) /* 6352 */ 32 #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ 33 #define PORT_STATUS_MGMII BIT(6) /* 6185 */ 34 #define PORT_STATUS_TX_PAUSED BIT(5) 35 #define PORT_STATUS_FLOW_CTRL BIT(4) 36 #define PORT_STATUS_CMODE_MASK 0x0f 37 #define PORT_STATUS_CMODE_100BASE_X 0x8 38 #define PORT_STATUS_CMODE_1000BASE_X 0x9 39 #define PORT_STATUS_CMODE_SGMII 0xa 40 #define PORT_STATUS_CMODE_2500BASEX 0xb 41 #define PORT_STATUS_CMODE_XAUI 0xc 42 #define PORT_STATUS_CMODE_RXAUI 0xd 43 #define PORT_PCS_CTRL 0x01 44 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) 45 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) 46 #define PORT_PCS_CTRL_FORCE_SPEED BIT(13) /* 6390 */ 47 #define PORT_PCS_CTRL_ALTSPEED BIT(12) /* 6390 */ 48 #define PORT_PCS_CTRL_200BASE BIT(12) /* 6352 */ 49 #define PORT_PCS_CTRL_FC BIT(7) 50 #define PORT_PCS_CTRL_FORCE_FC BIT(6) 51 #define PORT_PCS_CTRL_LINK_UP BIT(5) 52 #define PORT_PCS_CTRL_FORCE_LINK BIT(4) 53 #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) 54 #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) 55 #define PORT_PCS_CTRL_SPEED_MASK (0x03) 56 #define PORT_PCS_CTRL_SPEED_10 (0x00) 57 #define PORT_PCS_CTRL_SPEED_100 (0x01) 58 #define PORT_PCS_CTRL_SPEED_200 (0x02) /* 6065 and non Gb chips */ 59 #define PORT_PCS_CTRL_SPEED_1000 (0x02) 60 #define PORT_PCS_CTRL_SPEED_10000 (0x03) /* 6390X */ 61 #define PORT_PCS_CTRL_SPEED_UNFORCED (0x03) 62 #define PORT_PAUSE_CTRL 0x02 63 #define PORT_FLOW_CTRL_LIMIT_IN ((0x00 << 8) | BIT(15)) 64 #define PORT_FLOW_CTRL_LIMIT_OUT ((0x01 << 8) | BIT(15)) 65 #define PORT_SWITCH_ID 0x03 66 #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a 67 #define PORT_SWITCH_ID_PROD_NUM_6095 0x095 68 #define PORT_SWITCH_ID_PROD_NUM_6097 0x099 69 #define PORT_SWITCH_ID_PROD_NUM_6131 0x106 70 #define PORT_SWITCH_ID_PROD_NUM_6320 0x115 71 #define PORT_SWITCH_ID_PROD_NUM_6123 0x121 72 #define PORT_SWITCH_ID_PROD_NUM_6141 0x340 73 #define PORT_SWITCH_ID_PROD_NUM_6161 0x161 74 #define PORT_SWITCH_ID_PROD_NUM_6165 0x165 75 #define PORT_SWITCH_ID_PROD_NUM_6171 0x171 76 #define PORT_SWITCH_ID_PROD_NUM_6172 0x172 77 #define PORT_SWITCH_ID_PROD_NUM_6175 0x175 78 #define PORT_SWITCH_ID_PROD_NUM_6176 0x176 79 #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 80 #define PORT_SWITCH_ID_PROD_NUM_6190 0x190 81 #define PORT_SWITCH_ID_PROD_NUM_6190X 0x0a0 82 #define PORT_SWITCH_ID_PROD_NUM_6191 0x191 83 #define PORT_SWITCH_ID_PROD_NUM_6240 0x240 84 #define PORT_SWITCH_ID_PROD_NUM_6290 0x290 85 #define PORT_SWITCH_ID_PROD_NUM_6321 0x310 86 #define PORT_SWITCH_ID_PROD_NUM_6341 0x341 87 #define PORT_SWITCH_ID_PROD_NUM_6352 0x352 88 #define PORT_SWITCH_ID_PROD_NUM_6350 0x371 89 #define PORT_SWITCH_ID_PROD_NUM_6351 0x375 90 #define PORT_SWITCH_ID_PROD_NUM_6390 0x390 91 #define PORT_SWITCH_ID_PROD_NUM_6390X 0x0a1 92 #define PORT_CONTROL 0x04 93 #define PORT_CONTROL_USE_CORE_TAG BIT(15) 94 #define PORT_CONTROL_DROP_ON_LOCK BIT(14) 95 #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) 96 #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) 97 #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) 98 #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) 99 #define PORT_CONTROL_EGRESS_MASK (0x3 << 12) 100 #define PORT_CONTROL_HEADER BIT(11) 101 #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) 102 #define PORT_CONTROL_DOUBLE_TAG BIT(9) 103 #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) 104 #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) 105 #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) 106 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) 107 #define PORT_CONTROL_FRAME_MASK (0x3 << 8) 108 #define PORT_CONTROL_DSA_TAG BIT(8) 109 #define PORT_CONTROL_VLAN_TUNNEL BIT(7) 110 #define PORT_CONTROL_TAG_IF_BOTH BIT(6) 111 #define PORT_CONTROL_USE_IP BIT(5) 112 #define PORT_CONTROL_USE_TAG BIT(4) 113 #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) 114 #define PORT_CONTROL_EGRESS_FLOODS_MASK (0x3 << 2) 115 #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA (0x0 << 2) 116 #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA (0x1 << 2) 117 #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA (0x2 << 2) 118 #define PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA (0x3 << 2) 119 #define PORT_CONTROL_STATE_MASK 0x03 120 #define PORT_CONTROL_STATE_DISABLED 0x00 121 #define PORT_CONTROL_STATE_BLOCKING 0x01 122 #define PORT_CONTROL_STATE_LEARNING 0x02 123 #define PORT_CONTROL_STATE_FORWARDING 0x03 124 #define PORT_CONTROL_1 0x05 125 #define PORT_CONTROL_1_MESSAGE_PORT BIT(15) 126 #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) 127 #define PORT_BASE_VLAN 0x06 128 #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) 129 #define PORT_DEFAULT_VLAN 0x07 130 #define PORT_DEFAULT_VLAN_MASK 0xfff 131 #define PORT_CONTROL_2 0x08 132 #define PORT_CONTROL_2_IGNORE_FCS BIT(15) 133 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) 134 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) 135 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) 136 #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) 137 #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) 138 #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) 139 #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) 140 #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) 141 #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) 142 #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) 143 #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) 144 #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) 145 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) 146 #define PORT_CONTROL_2_MAP_DA BIT(7) 147 #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) 148 #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) 149 #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) 150 #define PORT_CONTROL_2_UPSTREAM_MASK 0x0f 151 #define PORT_RATE_CONTROL 0x09 152 #define PORT_RATE_CONTROL_2 0x0a 153 #define PORT_ASSOC_VECTOR 0x0b 154 #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) 155 #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) 156 #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) 157 #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) 158 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) 159 #define PORT_ATU_CONTROL 0x0c 160 #define PORT_PRI_OVERRIDE 0x0d 161 #define PORT_ETH_TYPE 0x0f 162 #define PORT_ETH_TYPE_DEFAULT 0x9100 163 #define PORT_IN_DISCARD_LO 0x10 164 #define PORT_IN_DISCARD_HI 0x11 165 #define PORT_IN_FILTERED 0x12 166 #define PORT_OUT_FILTERED 0x13 167 #define PORT_TAG_REGMAP_0123 0x18 168 #define PORT_TAG_REGMAP_4567 0x19 169 #define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */ 170 #define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15) 171 #define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12) 172 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12) 173 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12) 174 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12) 175 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12) 176 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12) 177 #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12) 178 #define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9 179 180 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 181 u16 *val); 182 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 183 u16 val); 184 185 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 186 phy_interface_t mode); 187 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 188 phy_interface_t mode); 189 190 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 191 192 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 193 194 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 195 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 196 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 197 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 198 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 199 200 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 201 202 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 203 204 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 205 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 206 207 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 208 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 209 210 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 211 u16 mode); 212 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 213 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 214 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 215 enum mv88e6xxx_egress_mode mode); 216 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 217 enum mv88e6xxx_frame_mode mode); 218 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 219 enum mv88e6xxx_frame_mode mode); 220 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 221 bool unicast, bool multicast); 222 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 223 bool unicast, bool multicast); 224 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 225 u16 etype); 226 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 227 bool message_port); 228 int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port); 229 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 230 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 231 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 232 u8 out); 233 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 234 u8 out); 235 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 236 phy_interface_t mode); 237 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 238 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 239 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 240 int upstream_port); 241 242 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 243 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 244 245 #endif /* _MV88E6XXX_PORT_H */ 246