1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include "sdhci.h" 17 #include "sdhci-pci.h" 18 #include "cqhci.h" 19 20 /* Genesys Logic extra registers */ 21 #define SDHCI_GLI_9750_WT 0x800 22 #define SDHCI_GLI_9750_WT_EN BIT(0) 23 #define GLI_9750_WT_EN_ON 0x1 24 #define GLI_9750_WT_EN_OFF 0x0 25 26 #define SDHCI_GLI_9750_CFG2 0x848 27 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 28 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 29 30 #define SDHCI_GLI_9750_DRIVING 0x860 31 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 32 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 33 #define GLI_9750_DRIVING_1_VALUE 0xFFF 34 #define GLI_9750_DRIVING_2_VALUE 0x3 35 #define SDHCI_GLI_9750_SEL_1 BIT(29) 36 #define SDHCI_GLI_9750_SEL_2 BIT(31) 37 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 38 39 #define SDHCI_GLI_9750_PLL 0x864 40 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 41 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 42 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 43 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 44 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 45 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 46 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 47 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 48 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 49 50 #define SDHCI_GLI_9750_PLLSSC 0x86C 51 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 52 53 #define SDHCI_GLI_9750_SW_CTRL 0x874 54 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 55 #define GLI_9750_SW_CTRL_4_VALUE 0x3 56 57 #define SDHCI_GLI_9750_MISC 0x878 58 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 59 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 60 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 61 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 62 #define GLI_9750_MISC_RX_INV_ON 0x1 63 #define GLI_9750_MISC_RX_INV_OFF 0x0 64 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 65 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 66 67 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 68 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 69 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 70 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 71 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 72 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 73 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 74 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 75 76 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 77 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 78 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 79 80 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 81 82 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 83 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 84 85 #define PCIE_GLI_9763E_VHS 0x884 86 #define GLI_9763E_VHS_REV GENMASK(19, 16) 87 #define GLI_9763E_VHS_REV_R 0x0 88 #define GLI_9763E_VHS_REV_M 0x1 89 #define GLI_9763E_VHS_REV_W 0x2 90 #define PCIE_GLI_9763E_MB 0x888 91 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 92 #define GLI_9763E_MB_ERP_ON BIT(7) 93 #define PCIE_GLI_9763E_SCR 0x8E0 94 #define GLI_9763E_SCR_AXI_REQ BIT(9) 95 96 #define PCIE_GLI_9763E_CFG2 0x8A4 97 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 98 #define GLI_9763E_CFG2_L1DLY_MID 0x54 99 100 #define PCIE_GLI_9763E_MMC_CTRL 0x960 101 #define GLI_9763E_HS400_SLOW BIT(3) 102 103 #define PCIE_GLI_9763E_CLKRXDLY 0x934 104 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 105 #define GLI_9763E_HS400_RXDLY_5 0x5 106 107 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 108 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 109 SDHCI_TRNS_BLK_CNT_EN | \ 110 SDHCI_TRNS_DMA) 111 112 #define PCI_GLI_9755_WT 0x800 113 #define PCI_GLI_9755_WT_EN BIT(0) 114 #define GLI_9755_WT_EN_ON 0x1 115 #define GLI_9755_WT_EN_OFF 0x0 116 117 #define PCI_GLI_9755_PECONF 0x44 118 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 119 #define PCI_GLI_9755_DMACLK BIT(29) 120 #define PCI_GLI_9755_INVERT_CD BIT(30) 121 #define PCI_GLI_9755_INVERT_WP BIT(31) 122 123 #define PCI_GLI_9755_CFG2 0x48 124 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 125 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 126 127 #define PCI_GLI_9755_PLL 0x64 128 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 129 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 130 #define PCI_GLI_9755_PLL_DIR BIT(15) 131 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 132 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 133 134 #define PCI_GLI_9755_PLLSSC 0x68 135 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 136 137 #define PCI_GLI_9755_SerDes 0x70 138 #define PCI_GLI_9755_SCP_DIS BIT(19) 139 140 #define GLI_MAX_TUNING_LOOP 40 141 142 /* Genesys Logic chipset */ 143 static inline void gl9750_wt_on(struct sdhci_host *host) 144 { 145 u32 wt_value; 146 u32 wt_enable; 147 148 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 149 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 150 151 if (wt_enable == GLI_9750_WT_EN_ON) 152 return; 153 154 wt_value &= ~SDHCI_GLI_9750_WT_EN; 155 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 156 157 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 158 } 159 160 static inline void gl9750_wt_off(struct sdhci_host *host) 161 { 162 u32 wt_value; 163 u32 wt_enable; 164 165 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 166 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 167 168 if (wt_enable == GLI_9750_WT_EN_OFF) 169 return; 170 171 wt_value &= ~SDHCI_GLI_9750_WT_EN; 172 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 173 174 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 175 } 176 177 static void gli_set_9750(struct sdhci_host *host) 178 { 179 u32 driving_value; 180 u32 pll_value; 181 u32 sw_ctrl_value; 182 u32 misc_value; 183 u32 parameter_value; 184 u32 control_value; 185 u16 ctrl2; 186 187 gl9750_wt_on(host); 188 189 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 190 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 191 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 192 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 193 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 194 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 195 196 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 197 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 198 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 199 GLI_9750_DRIVING_1_VALUE); 200 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 201 GLI_9750_DRIVING_2_VALUE); 202 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 203 driving_value |= SDHCI_GLI_9750_SEL_2; 204 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 205 206 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 207 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 208 GLI_9750_SW_CTRL_4_VALUE); 209 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 210 211 /* reset the tuning flow after reinit and before starting tuning */ 212 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 213 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 214 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 215 GLI_9750_PLL_TX2_INV_VALUE); 216 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 217 GLI_9750_PLL_TX2_DLY_VALUE); 218 219 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 220 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 221 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 222 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 223 GLI_9750_MISC_TX1_INV_VALUE); 224 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 225 GLI_9750_MISC_RX_INV_VALUE); 226 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 227 GLI_9750_MISC_TX1_DLY_VALUE); 228 229 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 230 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 231 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 232 233 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 234 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 235 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 236 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 237 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 238 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 239 240 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 241 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 242 243 /* disable tuned clk */ 244 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 245 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 246 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 247 248 /* enable tuning parameters control */ 249 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 250 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 251 GLI_9750_TUNING_CONTROL_EN_ON); 252 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 253 254 /* write tuning parameters */ 255 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 256 257 /* disable tuning parameters control */ 258 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 259 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 260 GLI_9750_TUNING_CONTROL_EN_OFF); 261 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 262 263 /* clear tuned clk */ 264 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 265 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 266 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 267 268 gl9750_wt_off(host); 269 } 270 271 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 272 { 273 u32 misc_value; 274 275 gl9750_wt_on(host); 276 277 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 278 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 279 if (b) { 280 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 281 GLI_9750_MISC_RX_INV_ON); 282 } else { 283 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 284 GLI_9750_MISC_RX_INV_OFF); 285 } 286 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 287 288 gl9750_wt_off(host); 289 } 290 291 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 292 { 293 int i; 294 int rx_inv; 295 296 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 297 gli_set_9750_rx_inv(host, !!rx_inv); 298 sdhci_start_tuning(host); 299 300 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 301 u16 ctrl; 302 303 sdhci_send_tuning(host, opcode); 304 305 if (!host->tuning_done) { 306 sdhci_abort_tuning(host, opcode); 307 break; 308 } 309 310 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 311 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 312 if (ctrl & SDHCI_CTRL_TUNED_CLK) 313 return 0; /* Success! */ 314 break; 315 } 316 } 317 } 318 if (!host->tuning_done) { 319 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 320 mmc_hostname(host->mmc)); 321 return -ETIMEDOUT; 322 } 323 324 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 325 mmc_hostname(host->mmc)); 326 sdhci_reset_tuning(host); 327 328 return -EAGAIN; 329 } 330 331 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 332 { 333 host->mmc->retune_period = 0; 334 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 335 host->mmc->retune_period = host->tuning_count; 336 337 gli_set_9750(host); 338 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 339 sdhci_end_tuning(host); 340 341 return 0; 342 } 343 344 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 345 { 346 u32 pll; 347 348 gl9750_wt_on(host); 349 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 350 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 351 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 352 gl9750_wt_off(host); 353 } 354 355 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 356 { 357 u32 pll; 358 359 gl9750_wt_on(host); 360 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 361 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 362 SDHCI_GLI_9750_PLL_PDIV | 363 SDHCI_GLI_9750_PLL_DIR); 364 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 365 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 366 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 367 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 368 gl9750_wt_off(host); 369 370 /* wait for pll stable */ 371 mdelay(1); 372 } 373 374 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 375 { 376 u32 pll; 377 u32 ssc; 378 379 gl9750_wt_on(host); 380 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 381 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 382 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 383 SDHCI_GLI_9750_PLLSSC_EN); 384 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 385 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 386 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 387 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 388 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 389 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 390 gl9750_wt_off(host); 391 } 392 393 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 394 { 395 /* set pll to 205MHz and enable ssc */ 396 gl9750_set_ssc(host, 0x1, 0xF, 0x5A1D); 397 gl9750_set_pll(host, 0x1, 0x246, 0x0); 398 } 399 400 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 401 { 402 /* set pll to 100MHz and enable ssc */ 403 gl9750_set_ssc(host, 0x1, 0xE, 0x51EC); 404 gl9750_set_pll(host, 0x1, 0x244, 0x1); 405 } 406 407 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 408 { 409 /* set pll to 50MHz and enable ssc */ 410 gl9750_set_ssc(host, 0x1, 0xE, 0x51EC); 411 gl9750_set_pll(host, 0x1, 0x244, 0x3); 412 } 413 414 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 415 { 416 struct mmc_ios *ios = &host->mmc->ios; 417 u16 clk; 418 419 host->mmc->actual_clock = 0; 420 421 gl9750_disable_ssc_pll(host); 422 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 423 424 if (clock == 0) 425 return; 426 427 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 428 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 429 host->mmc->actual_clock = 205000000; 430 gl9750_set_ssc_pll_205mhz(host); 431 } else if (clock == 100000000) { 432 gl9750_set_ssc_pll_100mhz(host); 433 } else if (clock == 50000000) { 434 gl9750_set_ssc_pll_50mhz(host); 435 } 436 437 sdhci_enable_clk(host, clk); 438 } 439 440 static void gl9750_hw_setting(struct sdhci_host *host) 441 { 442 u32 value; 443 444 gl9750_wt_on(host); 445 446 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 447 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 448 /* set ASPM L1 entry delay to 7.9us */ 449 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 450 GLI_9750_CFG2_L1DLY_VALUE); 451 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 452 453 gl9750_wt_off(host); 454 } 455 456 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 457 { 458 int ret; 459 460 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 461 PCI_IRQ_MSI | PCI_IRQ_MSIX); 462 if (ret < 0) { 463 pr_warn("%s: enable PCI MSI failed, error=%d\n", 464 mmc_hostname(slot->host->mmc), ret); 465 return; 466 } 467 468 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 469 } 470 471 static inline void gl9755_wt_on(struct pci_dev *pdev) 472 { 473 u32 wt_value; 474 u32 wt_enable; 475 476 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 477 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 478 479 if (wt_enable == GLI_9755_WT_EN_ON) 480 return; 481 482 wt_value &= ~PCI_GLI_9755_WT_EN; 483 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 484 485 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 486 } 487 488 static inline void gl9755_wt_off(struct pci_dev *pdev) 489 { 490 u32 wt_value; 491 u32 wt_enable; 492 493 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 494 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 495 496 if (wt_enable == GLI_9755_WT_EN_OFF) 497 return; 498 499 wt_value &= ~PCI_GLI_9755_WT_EN; 500 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 501 502 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 503 } 504 505 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 506 { 507 u32 pll; 508 509 gl9755_wt_on(pdev); 510 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 511 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 512 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 513 gl9755_wt_off(pdev); 514 } 515 516 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 517 { 518 u32 pll; 519 520 gl9755_wt_on(pdev); 521 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 522 pll &= ~(PCI_GLI_9755_PLL_LDIV | 523 PCI_GLI_9755_PLL_PDIV | 524 PCI_GLI_9755_PLL_DIR); 525 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 526 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 527 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 528 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 529 gl9755_wt_off(pdev); 530 531 /* wait for pll stable */ 532 mdelay(1); 533 } 534 535 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 536 { 537 u32 pll; 538 u32 ssc; 539 540 gl9755_wt_on(pdev); 541 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 542 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 543 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 544 PCI_GLI_9755_PLLSSC_EN); 545 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 546 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 547 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 548 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 549 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 550 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 551 gl9755_wt_off(pdev); 552 } 553 554 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 555 { 556 /* set pll to 205MHz and enable ssc */ 557 gl9755_set_ssc(pdev, 0x1, 0xF, 0x5A1D); 558 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 559 } 560 561 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 562 { 563 /* set pll to 100MHz and enable ssc */ 564 gl9755_set_ssc(pdev, 0x1, 0xE, 0x51EC); 565 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 566 } 567 568 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 569 { 570 /* set pll to 50MHz and enable ssc */ 571 gl9755_set_ssc(pdev, 0x1, 0xE, 0x51EC); 572 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 573 } 574 575 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 576 { 577 struct sdhci_pci_slot *slot = sdhci_priv(host); 578 struct mmc_ios *ios = &host->mmc->ios; 579 struct pci_dev *pdev; 580 u16 clk; 581 582 pdev = slot->chip->pdev; 583 host->mmc->actual_clock = 0; 584 585 gl9755_disable_ssc_pll(pdev); 586 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 587 588 if (clock == 0) 589 return; 590 591 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 592 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 593 host->mmc->actual_clock = 205000000; 594 gl9755_set_ssc_pll_205mhz(pdev); 595 } else if (clock == 100000000) { 596 gl9755_set_ssc_pll_100mhz(pdev); 597 } else if (clock == 50000000) { 598 gl9755_set_ssc_pll_50mhz(pdev); 599 } 600 601 sdhci_enable_clk(host, clk); 602 } 603 604 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 605 { 606 struct pci_dev *pdev = slot->chip->pdev; 607 u32 value; 608 609 gl9755_wt_on(pdev); 610 611 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 612 /* 613 * Apple ARM64 platforms using these chips may have 614 * inverted CD/WP detection. 615 */ 616 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 617 value |= PCI_GLI_9755_INVERT_CD; 618 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 619 value |= PCI_GLI_9755_INVERT_WP; 620 value &= ~PCI_GLI_9755_LFCLK; 621 value &= ~PCI_GLI_9755_DMACLK; 622 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 623 624 /* enable short circuit protection */ 625 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 626 value &= ~PCI_GLI_9755_SCP_DIS; 627 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 628 629 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 630 value &= ~PCI_GLI_9755_CFG2_L1DLY; 631 /* set ASPM L1 entry delay to 7.9us */ 632 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 633 GLI_9755_CFG2_L1DLY_VALUE); 634 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 635 636 gl9755_wt_off(pdev); 637 } 638 639 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 640 { 641 struct sdhci_host *host = slot->host; 642 643 gl9750_hw_setting(host); 644 gli_pcie_enable_msi(slot); 645 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 646 sdhci_enable_v4_mode(host); 647 648 return 0; 649 } 650 651 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 652 { 653 struct sdhci_host *host = slot->host; 654 655 gl9755_hw_setting(slot); 656 gli_pcie_enable_msi(slot); 657 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 658 sdhci_enable_v4_mode(host); 659 660 return 0; 661 } 662 663 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 664 { 665 /* 666 * According to Section 3.6.1 signal voltage switch procedure in 667 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 668 * follows: 669 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 670 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 671 * period. 672 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 673 * step (12). 674 * 675 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 676 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 677 * 678 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 679 * slightly longer than 5ms before the control register reports that 680 * 1.8V is ready, and far longer still before the card will actually 681 * work reliably. 682 */ 683 usleep_range(100000, 110000); 684 } 685 686 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 687 { 688 sdhci_reset(host, mask); 689 gli_set_9750(host); 690 } 691 692 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 693 { 694 u32 value; 695 696 value = readl(host->ioaddr + reg); 697 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 698 value |= 0xc8; 699 700 return value; 701 } 702 703 #ifdef CONFIG_PM_SLEEP 704 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 705 { 706 struct sdhci_pci_slot *slot = chip->slots[0]; 707 708 pci_free_irq_vectors(slot->chip->pdev); 709 gli_pcie_enable_msi(slot); 710 711 return sdhci_pci_resume_host(chip); 712 } 713 714 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip) 715 { 716 struct sdhci_pci_slot *slot = chip->slots[0]; 717 int ret; 718 719 ret = sdhci_pci_gli_resume(chip); 720 if (ret) 721 return ret; 722 723 return cqhci_resume(slot->host->mmc); 724 } 725 726 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip) 727 { 728 struct sdhci_pci_slot *slot = chip->slots[0]; 729 int ret; 730 731 ret = cqhci_suspend(slot->host->mmc); 732 if (ret) 733 return ret; 734 735 return sdhci_suspend_host(slot->host); 736 } 737 #endif 738 739 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 740 struct mmc_ios *ios) 741 { 742 struct sdhci_host *host = mmc_priv(mmc); 743 u32 val; 744 745 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 746 if (ios->enhanced_strobe) 747 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 748 else 749 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 750 751 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 752 } 753 754 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 755 unsigned int timing) 756 { 757 u16 ctrl_2; 758 759 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 760 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 761 if (timing == MMC_TIMING_MMC_HS200) 762 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 763 else if (timing == MMC_TIMING_MMC_HS) 764 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 765 else if (timing == MMC_TIMING_MMC_DDR52) 766 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 767 else if (timing == MMC_TIMING_MMC_HS400) 768 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 769 770 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 771 } 772 773 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 774 { 775 sdhci_dumpregs(mmc_priv(mmc)); 776 } 777 778 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 779 { 780 struct cqhci_host *cq_host = mmc->cqe_private; 781 u32 value; 782 783 value = cqhci_readl(cq_host, CQHCI_CFG); 784 value |= CQHCI_ENABLE; 785 cqhci_writel(cq_host, value, CQHCI_CFG); 786 } 787 788 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 789 { 790 struct sdhci_host *host = mmc_priv(mmc); 791 792 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 793 sdhci_cqe_enable(mmc); 794 } 795 796 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 797 { 798 int cmd_error = 0; 799 int data_error = 0; 800 801 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 802 return intmask; 803 804 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 805 806 return 0; 807 } 808 809 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 810 { 811 struct sdhci_host *host = mmc_priv(mmc); 812 struct cqhci_host *cq_host = mmc->cqe_private; 813 u32 value; 814 815 value = cqhci_readl(cq_host, CQHCI_CFG); 816 value &= ~CQHCI_ENABLE; 817 cqhci_writel(cq_host, value, CQHCI_CFG); 818 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 819 } 820 821 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 822 .enable = sdhci_gl9763e_cqe_enable, 823 .disable = sdhci_cqe_disable, 824 .dumpregs = sdhci_gl9763e_dumpregs, 825 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 826 .post_disable = sdhci_gl9763e_cqe_post_disable, 827 }; 828 829 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 830 { 831 struct device *dev = &slot->chip->pdev->dev; 832 struct sdhci_host *host = slot->host; 833 struct cqhci_host *cq_host; 834 bool dma64; 835 int ret; 836 837 ret = sdhci_setup_host(host); 838 if (ret) 839 return ret; 840 841 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 842 if (!cq_host) { 843 ret = -ENOMEM; 844 goto cleanup; 845 } 846 847 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 848 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 849 850 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 851 if (dma64) 852 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 853 854 ret = cqhci_init(cq_host, host->mmc, dma64); 855 if (ret) 856 goto cleanup; 857 858 ret = __sdhci_add_host(host); 859 if (ret) 860 goto cleanup; 861 862 return 0; 863 864 cleanup: 865 sdhci_cleanup_host(host); 866 return ret; 867 } 868 869 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask) 870 { 871 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 872 host->mmc->cqe_private) 873 cqhci_deactivate(host->mmc); 874 sdhci_reset(host, mask); 875 } 876 877 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 878 { 879 struct pci_dev *pdev = slot->chip->pdev; 880 u32 value; 881 882 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 883 value &= ~GLI_9763E_VHS_REV; 884 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 885 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 886 887 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 888 value |= GLI_9763E_SCR_AXI_REQ; 889 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 890 891 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 892 value &= ~GLI_9763E_HS400_SLOW; 893 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 894 895 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 896 value &= ~GLI_9763E_CFG2_L1DLY; 897 /* set ASPM L1 entry delay to 21us */ 898 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 899 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 900 901 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 902 value &= ~GLI_9763E_HS400_RXDLY; 903 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 904 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 905 906 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 907 value &= ~GLI_9763E_VHS_REV; 908 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 909 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 910 } 911 912 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 913 { 914 struct pci_dev *pdev = slot->chip->pdev; 915 struct sdhci_host *host = slot->host; 916 u32 value; 917 918 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 919 MMC_CAP_1_8V_DDR | 920 MMC_CAP_NONREMOVABLE; 921 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 922 MMC_CAP2_HS400_1_8V | 923 MMC_CAP2_HS400_ES | 924 MMC_CAP2_NO_SDIO | 925 MMC_CAP2_NO_SD; 926 927 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 928 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 929 if (value & GLI_9763E_MB_ERP_ON) 930 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 931 932 gli_pcie_enable_msi(slot); 933 host->mmc_host_ops.hs400_enhanced_strobe = 934 gl9763e_hs400_enhanced_strobe; 935 gli_set_gl9763e(slot); 936 sdhci_enable_v4_mode(host); 937 938 return 0; 939 } 940 941 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 942 943 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 944 { 945 u32 val = readl(host->ioaddr + (reg & ~3)); 946 u16 word; 947 948 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 949 return word; 950 } 951 952 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 953 { 954 u32 val = readl(host->ioaddr + (reg & ~3)); 955 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 956 957 return byte; 958 } 959 960 static const struct sdhci_ops sdhci_gl9755_ops = { 961 .read_w = sdhci_gli_readw, 962 .read_b = sdhci_gli_readb, 963 .set_clock = sdhci_gl9755_set_clock, 964 .enable_dma = sdhci_pci_enable_dma, 965 .set_bus_width = sdhci_set_bus_width, 966 .reset = sdhci_reset, 967 .set_uhs_signaling = sdhci_set_uhs_signaling, 968 .voltage_switch = sdhci_gli_voltage_switch, 969 }; 970 971 const struct sdhci_pci_fixes sdhci_gl9755 = { 972 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 973 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 974 .probe_slot = gli_probe_slot_gl9755, 975 .ops = &sdhci_gl9755_ops, 976 #ifdef CONFIG_PM_SLEEP 977 .resume = sdhci_pci_gli_resume, 978 #endif 979 }; 980 981 static const struct sdhci_ops sdhci_gl9750_ops = { 982 .read_w = sdhci_gli_readw, 983 .read_b = sdhci_gli_readb, 984 .read_l = sdhci_gl9750_readl, 985 .set_clock = sdhci_gl9750_set_clock, 986 .enable_dma = sdhci_pci_enable_dma, 987 .set_bus_width = sdhci_set_bus_width, 988 .reset = sdhci_gl9750_reset, 989 .set_uhs_signaling = sdhci_set_uhs_signaling, 990 .voltage_switch = sdhci_gli_voltage_switch, 991 .platform_execute_tuning = gl9750_execute_tuning, 992 }; 993 994 const struct sdhci_pci_fixes sdhci_gl9750 = { 995 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 996 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 997 .probe_slot = gli_probe_slot_gl9750, 998 .ops = &sdhci_gl9750_ops, 999 #ifdef CONFIG_PM_SLEEP 1000 .resume = sdhci_pci_gli_resume, 1001 #endif 1002 }; 1003 1004 static const struct sdhci_ops sdhci_gl9763e_ops = { 1005 .set_clock = sdhci_set_clock, 1006 .enable_dma = sdhci_pci_enable_dma, 1007 .set_bus_width = sdhci_set_bus_width, 1008 .reset = sdhci_gl9763e_reset, 1009 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 1010 .voltage_switch = sdhci_gli_voltage_switch, 1011 .irq = sdhci_gl9763e_cqhci_irq, 1012 }; 1013 1014 const struct sdhci_pci_fixes sdhci_gl9763e = { 1015 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1016 .probe_slot = gli_probe_slot_gl9763e, 1017 .ops = &sdhci_gl9763e_ops, 1018 #ifdef CONFIG_PM_SLEEP 1019 .resume = sdhci_cqhci_gli_resume, 1020 .suspend = sdhci_cqhci_gli_suspend, 1021 #endif 1022 .add_host = gl9763e_add_host, 1023 }; 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