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Revision tags: v4.18.9 |
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32aa27e1 |
| 14-Sep-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
msm/gpu/a6xx: Force of_dma_configure to setup DMA for GMU
The point of the 'force_dma' parameter for of_dma_configure
is to force the device to be set up even if DMA capability is
no
msm/gpu/a6xx: Force of_dma_configure to setup DMA for GMU
The point of the 'force_dma' parameter for of_dma_configure
is to force the device to be set up even if DMA capability is
not described by the firmware which is exactly the use case
we have for GMU - we need SMMU to get set up but we have no
other dma capabilities since memory is managed by the GPU
driver. Currently we pass false so of_dma_configure() fails
and subsequently GMU and GPU probe does as well.
Fixes: 4b565ca5a2c ("drm/msm: Add A6XX device support")
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Revision tags: v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14 |
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| #
f8fc924e |
| 08-Aug-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/a6xx: Fix PDC register overlap
The current design greedily takes a big chunk of the PDC
register space instead of just the GPU specific sections
which conflicts with other dr
drm/msm/a6xx: Fix PDC register overlap
The current design greedily takes a big chunk of the PDC
register space instead of just the GPU specific sections
which conflicts with other drivers and generally makes
a mess of things.
Furthermore we only need to map the GPU PDC sections
just once during init so map the memory inside the function
that uses it and adjust the pointers and register offsets
accordingly.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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9fb4bfd0 |
| 27-Sep-2018 |
Sharat Masetty <smasetty@codeaurora.org> |
drm/msm/a6xx: Send the right perf index value to GMU
The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running
drm/msm/a6xx: Send the right perf index value to GMU
The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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546907de |
| 08-Aug-2018 |
Colin Ian King <colin.king@canonical.com> |
drm/msm: a6xx: fix spelling mistake: "initalization" -> "initialization"
Trivial fix to spelling mistake in dev_err message and comment
Signed-off-by: Colin Ian King <colin.king@can
drm/msm: a6xx: fix spelling mistake: "initalization" -> "initialization"
Trivial fix to spelling mistake in dev_err message and comment
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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4b565ca5 |
| 06-Aug-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Add A6XX device support
Add support for the A6XX family of Adreno GPUs. The biggest addition
is the GMU (Graphics Management Unit) which takes over most of the
power managem
drm/msm: Add A6XX device support
Add support for the A6XX family of Adreno GPUs. The biggest addition
is the GMU (Graphics Management Unit) which takes over most of the
power management of the GPU itself but in a ironic twist of fate
needs a goodly amount of management itself. Add support for the
A6XX core code, the GMU and the HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
show more ...
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