1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_ddi.h" 8 #include "intel_ddi_buf_trans.h" 9 #include "intel_de.h" 10 #include "intel_display_types.h" 11 12 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 13 * them for both DP and FDI transports, allowing those ports to 14 * automatically adapt to HDMI connections as well 15 */ 16 static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = { 17 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, 18 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, 19 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } }, 20 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } }, 21 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, 22 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, 23 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } }, 24 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, 25 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } }, 26 }; 27 28 static const struct intel_ddi_buf_trans hsw_ddi_translations_dp = { 29 .entries = _hsw_ddi_translations_dp, 30 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_dp), 31 }; 32 33 static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = { 34 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, 35 { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } }, 36 { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } }, 37 { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } }, 38 { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } }, 39 { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } }, 40 { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } }, 41 { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } }, 42 { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } }, 43 }; 44 45 static const struct intel_ddi_buf_trans hsw_ddi_translations_fdi = { 46 .entries = _hsw_ddi_translations_fdi, 47 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_fdi), 48 }; 49 50 static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { 51 /* Idx NT mV d T mV d db */ 52 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */ 53 { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */ 54 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, /* 2: 400 600 3.5 */ 55 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, /* 3: 600 600 0 */ 56 { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } }, /* 4: 600 750 2 */ 57 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5: 600 900 3.5 */ 58 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, /* 6: 800 800 0 */ 59 { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } }, /* 7: 800 1000 2 */ 60 { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } }, /* 8: 850 850 0 */ 61 { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } }, /* 9: 900 900 0 */ 62 { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } }, /* 10: 950 950 0 */ 63 { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */ 64 }; 65 66 static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = { 67 .entries = _hsw_ddi_translations_hdmi, 68 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi), 69 .hdmi_default_entry = 6, 70 }; 71 72 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { 73 { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } }, 74 { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } }, 75 { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } }, 76 { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } }, 77 { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } }, 78 { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } }, 79 { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } }, 80 { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } }, 81 { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } }, 82 }; 83 84 static const struct intel_ddi_buf_trans bdw_ddi_translations_edp = { 85 .entries = _bdw_ddi_translations_edp, 86 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_edp), 87 }; 88 89 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = { 90 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, 91 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, 92 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, 93 { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } }, 94 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, 95 { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } }, 96 { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } }, 97 { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } }, 98 { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } }, 99 }; 100 101 static const struct intel_ddi_buf_trans bdw_ddi_translations_dp = { 102 .entries = _bdw_ddi_translations_dp, 103 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_dp), 104 }; 105 106 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = { 107 { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } }, 108 { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } }, 109 { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } }, 110 { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } }, 111 { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } }, 112 { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } }, 113 { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } }, 114 { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } }, 115 { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } }, 116 }; 117 118 static const struct intel_ddi_buf_trans bdw_ddi_translations_fdi = { 119 .entries = _bdw_ddi_translations_fdi, 120 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_fdi), 121 }; 122 123 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { 124 /* Idx NT mV d T mV df db */ 125 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */ 126 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */ 127 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, /* 2: 400 800 6 */ 128 { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } }, /* 3: 450 450 0 */ 129 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, /* 4: 600 600 0 */ 130 { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5: 600 800 2.5 */ 131 { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } }, /* 6: 600 1000 4.5 */ 132 { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } }, /* 7: 800 800 0 */ 133 { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } }, /* 8: 800 1000 2 */ 134 { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */ 135 }; 136 137 static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = { 138 .entries = _bdw_ddi_translations_hdmi, 139 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi), 140 .hdmi_default_entry = 7, 141 }; 142 143 /* Skylake H and S */ 144 static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = { 145 { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, 146 { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, 147 { .hsw = { 0x00007011, 0x00000088, 0x0 } }, 148 { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, 149 { .hsw = { 0x00002016, 0x0000009B, 0x0 } }, 150 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 151 { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, 152 { .hsw = { 0x00002016, 0x000000DF, 0x0 } }, 153 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 154 }; 155 156 static const struct intel_ddi_buf_trans skl_ddi_translations_dp = { 157 .entries = _skl_ddi_translations_dp, 158 .num_entries = ARRAY_SIZE(_skl_ddi_translations_dp), 159 }; 160 161 /* Skylake U */ 162 static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = { 163 { .hsw = { 0x0000201B, 0x000000A2, 0x0 } }, 164 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 165 { .hsw = { 0x80007011, 0x000000CD, 0x1 } }, 166 { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, 167 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } }, 168 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 169 { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, 170 { .hsw = { 0x00002016, 0x00000088, 0x0 } }, 171 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 172 }; 173 174 static const struct intel_ddi_buf_trans skl_u_ddi_translations_dp = { 175 .entries = _skl_u_ddi_translations_dp, 176 .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_dp), 177 }; 178 179 /* Skylake Y */ 180 static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = { 181 { .hsw = { 0x00000018, 0x000000A2, 0x0 } }, 182 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 183 { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, 184 { .hsw = { 0x80009010, 0x000000C0, 0x3 } }, 185 { .hsw = { 0x00000018, 0x0000009D, 0x0 } }, 186 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 187 { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, 188 { .hsw = { 0x00000018, 0x00000088, 0x0 } }, 189 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 190 }; 191 192 static const struct intel_ddi_buf_trans skl_y_ddi_translations_dp = { 193 .entries = _skl_y_ddi_translations_dp, 194 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_dp), 195 }; 196 197 /* Kabylake H and S */ 198 static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = { 199 { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, 200 { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, 201 { .hsw = { 0x00007011, 0x00000088, 0x0 } }, 202 { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, 203 { .hsw = { 0x00002016, 0x0000009B, 0x0 } }, 204 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 205 { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, 206 { .hsw = { 0x00002016, 0x00000097, 0x0 } }, 207 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 208 }; 209 210 static const struct intel_ddi_buf_trans kbl_ddi_translations_dp = { 211 .entries = _kbl_ddi_translations_dp, 212 .num_entries = ARRAY_SIZE(_kbl_ddi_translations_dp), 213 }; 214 215 /* Kabylake U */ 216 static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = { 217 { .hsw = { 0x0000201B, 0x000000A1, 0x0 } }, 218 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 219 { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, 220 { .hsw = { 0x80009010, 0x000000C0, 0x3 } }, 221 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } }, 222 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 223 { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, 224 { .hsw = { 0x00002016, 0x0000004F, 0x0 } }, 225 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 226 }; 227 228 static const struct intel_ddi_buf_trans kbl_u_ddi_translations_dp = { 229 .entries = _kbl_u_ddi_translations_dp, 230 .num_entries = ARRAY_SIZE(_kbl_u_ddi_translations_dp), 231 }; 232 233 /* Kabylake Y */ 234 static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = { 235 { .hsw = { 0x00001017, 0x000000A1, 0x0 } }, 236 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 237 { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, 238 { .hsw = { 0x8000800F, 0x000000C0, 0x3 } }, 239 { .hsw = { 0x00001017, 0x0000009D, 0x0 } }, 240 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 241 { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, 242 { .hsw = { 0x00001017, 0x0000004C, 0x0 } }, 243 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 244 }; 245 246 static const struct intel_ddi_buf_trans kbl_y_ddi_translations_dp = { 247 .entries = _kbl_y_ddi_translations_dp, 248 .num_entries = ARRAY_SIZE(_kbl_y_ddi_translations_dp), 249 }; 250 251 /* 252 * Skylake/Kabylake H and S 253 * eDP 1.4 low vswing translation parameters 254 */ 255 static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = { 256 { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, 257 { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, 258 { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, 259 { .hsw = { 0x00009010, 0x0000009C, 0x0 } }, 260 { .hsw = { 0x00000018, 0x000000A9, 0x0 } }, 261 { .hsw = { 0x00006013, 0x000000A2, 0x0 } }, 262 { .hsw = { 0x00007011, 0x000000A6, 0x0 } }, 263 { .hsw = { 0x00000018, 0x000000AB, 0x0 } }, 264 { .hsw = { 0x00007013, 0x0000009F, 0x0 } }, 265 { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, 266 }; 267 268 static const struct intel_ddi_buf_trans skl_ddi_translations_edp = { 269 .entries = _skl_ddi_translations_edp, 270 .num_entries = ARRAY_SIZE(_skl_ddi_translations_edp), 271 }; 272 273 /* 274 * Skylake/Kabylake U 275 * eDP 1.4 low vswing translation parameters 276 */ 277 static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = { 278 { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, 279 { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, 280 { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, 281 { .hsw = { 0x00009010, 0x0000009C, 0x0 } }, 282 { .hsw = { 0x00000018, 0x000000A9, 0x0 } }, 283 { .hsw = { 0x00006013, 0x000000A2, 0x0 } }, 284 { .hsw = { 0x00007011, 0x000000A6, 0x0 } }, 285 { .hsw = { 0x00002016, 0x000000AB, 0x0 } }, 286 { .hsw = { 0x00005013, 0x0000009F, 0x0 } }, 287 { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, 288 }; 289 290 static const struct intel_ddi_buf_trans skl_u_ddi_translations_edp = { 291 .entries = _skl_u_ddi_translations_edp, 292 .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_edp), 293 }; 294 295 /* 296 * Skylake/Kabylake Y 297 * eDP 1.4 low vswing translation parameters 298 */ 299 static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = { 300 { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, 301 { .hsw = { 0x00004013, 0x000000AB, 0x0 } }, 302 { .hsw = { 0x00007011, 0x000000A4, 0x0 } }, 303 { .hsw = { 0x00009010, 0x000000DF, 0x0 } }, 304 { .hsw = { 0x00000018, 0x000000AA, 0x0 } }, 305 { .hsw = { 0x00006013, 0x000000A4, 0x0 } }, 306 { .hsw = { 0x00007011, 0x0000009D, 0x0 } }, 307 { .hsw = { 0x00000018, 0x000000A0, 0x0 } }, 308 { .hsw = { 0x00006012, 0x000000DF, 0x0 } }, 309 { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, 310 }; 311 312 static const struct intel_ddi_buf_trans skl_y_ddi_translations_edp = { 313 .entries = _skl_y_ddi_translations_edp, 314 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_edp), 315 }; 316 317 /* Skylake/Kabylake U, H and S */ 318 static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { 319 { .hsw = { 0x00000018, 0x000000AC, 0x0 } }, 320 { .hsw = { 0x00005012, 0x0000009D, 0x0 } }, 321 { .hsw = { 0x00007011, 0x00000088, 0x0 } }, 322 { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, 323 { .hsw = { 0x00000018, 0x00000098, 0x0 } }, 324 { .hsw = { 0x00004013, 0x00000088, 0x0 } }, 325 { .hsw = { 0x80006012, 0x000000CD, 0x1 } }, 326 { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, 327 { .hsw = { 0x80003015, 0x000000CD, 0x1 } }, /* Default */ 328 { .hsw = { 0x80003015, 0x000000C0, 0x1 } }, 329 { .hsw = { 0x80000018, 0x000000C0, 0x1 } }, 330 }; 331 332 static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = { 333 .entries = _skl_ddi_translations_hdmi, 334 .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi), 335 .hdmi_default_entry = 8, 336 }; 337 338 /* Skylake/Kabylake Y */ 339 static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { 340 { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, 341 { .hsw = { 0x00005012, 0x000000DF, 0x0 } }, 342 { .hsw = { 0x80007011, 0x000000CB, 0x3 } }, 343 { .hsw = { 0x00000018, 0x000000A4, 0x0 } }, 344 { .hsw = { 0x00000018, 0x0000009D, 0x0 } }, 345 { .hsw = { 0x00004013, 0x00000080, 0x0 } }, 346 { .hsw = { 0x80006013, 0x000000C0, 0x3 } }, 347 { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, 348 { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, /* Default */ 349 { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, 350 { .hsw = { 0x80000018, 0x000000C0, 0x3 } }, 351 }; 352 353 static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = { 354 .entries = _skl_y_ddi_translations_hdmi, 355 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi), 356 .hdmi_default_entry = 8, 357 }; 358 359 static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { 360 /* Idx NT mV diff db */ 361 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ 362 { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ 363 { .bxt = { 104, 0x9A, 0, 64, } }, /* 2: 400 6 */ 364 { .bxt = { 154, 0x9A, 0, 43, } }, /* 3: 400 9.5 */ 365 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */ 366 { .bxt = { 116, 0x9A, 0, 85, } }, /* 5: 600 3.5 */ 367 { .bxt = { 154, 0x9A, 0, 64, } }, /* 6: 600 6 */ 368 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */ 369 { .bxt = { 154, 0x9A, 0, 85, } }, /* 8: 800 3.5 */ 370 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ 371 }; 372 373 static const struct intel_ddi_buf_trans bxt_ddi_translations_dp = { 374 .entries = _bxt_ddi_translations_dp, 375 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_dp), 376 }; 377 378 static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = { 379 /* Idx NT mV diff db */ 380 { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */ 381 { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */ 382 { .bxt = { 48, 0, 0, 96, } }, /* 2: 200 4 */ 383 { .bxt = { 54, 0, 0, 69, } }, /* 3: 200 6 */ 384 { .bxt = { 32, 0, 0, 128, } }, /* 4: 250 0 */ 385 { .bxt = { 48, 0, 0, 104, } }, /* 5: 250 1.5 */ 386 { .bxt = { 54, 0, 0, 85, } }, /* 6: 250 4 */ 387 { .bxt = { 43, 0, 0, 128, } }, /* 7: 300 0 */ 388 { .bxt = { 54, 0, 0, 101, } }, /* 8: 300 1.5 */ 389 { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */ 390 }; 391 392 static const struct intel_ddi_buf_trans bxt_ddi_translations_edp = { 393 .entries = _bxt_ddi_translations_edp, 394 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_edp), 395 }; 396 397 /* BSpec has 2 recommended values - entries 0 and 8. 398 * Using the entry with higher vswing. 399 */ 400 static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { 401 /* Idx NT mV diff db */ 402 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ 403 { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ 404 { .bxt = { 52, 0x9A, 0, 64, } }, /* 2: 400 6 */ 405 { .bxt = { 42, 0x9A, 0, 43, } }, /* 3: 400 9.5 */ 406 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */ 407 { .bxt = { 77, 0x9A, 0, 85, } }, /* 5: 600 3.5 */ 408 { .bxt = { 77, 0x9A, 0, 64, } }, /* 6: 600 6 */ 409 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */ 410 { .bxt = { 102, 0x9A, 0, 85, } }, /* 8: 800 3.5 */ 411 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ 412 }; 413 414 static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = { 415 .entries = _bxt_ddi_translations_hdmi, 416 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi), 417 .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1, 418 }; 419 420 /* icl_combo_phy_ddi_translations */ 421 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = { 422 /* NT mV Trans mV db */ 423 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 424 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 425 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 426 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 427 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 428 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 429 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 430 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 431 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 432 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 433 }; 434 435 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = { 436 .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 437 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), 438 }; 439 440 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = { 441 /* NT mV Trans mV db */ 442 { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 443 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ 444 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */ 445 { .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200 350 4.9 */ 446 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 447 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ 448 { .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */ 449 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 450 { .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 451 { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 452 }; 453 454 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = { 455 .entries = _icl_combo_phy_ddi_translations_edp_hbr2, 456 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), 457 }; 458 459 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = { 460 /* NT mV Trans mV db */ 461 { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ 462 { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ 463 { .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */ 464 { .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */ 465 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */ 466 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */ 467 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ 468 }; 469 470 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = { 471 .entries = _icl_combo_phy_ddi_translations_hdmi, 472 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi), 473 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1, 474 }; 475 476 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = { 477 /* NT mV Trans mV db */ 478 { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 479 { .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ 480 { .icl = { 0xC, 0x64, 0x34, 0x00, 0x0B } }, /* 350 700 6.0 */ 481 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 350 900 8.2 */ 482 { .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 483 { .icl = { 0xC, 0x64, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */ 484 { .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ 485 { .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 486 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */ 487 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 488 }; 489 490 static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = { 491 .entries = _ehl_combo_phy_ddi_translations_dp, 492 .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_dp), 493 }; 494 495 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = { 496 /* NT mV Trans mV db */ 497 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 498 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ 499 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */ 500 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200 350 4.9 */ 501 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 502 { .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250 300 1.6 */ 503 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250 350 2.9 */ 504 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 505 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 506 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 507 }; 508 509 static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = { 510 .entries = _ehl_combo_phy_ddi_translations_edp_hbr2, 511 .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_edp_hbr2), 512 }; 513 514 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = { 515 /* NT mV Trans mV db */ 516 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 517 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ 518 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */ 519 { .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200 350 4.9 */ 520 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 521 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ 522 { .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */ 523 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 524 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 525 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 526 }; 527 528 static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = { 529 .entries = _jsl_combo_phy_ddi_translations_edp_hbr, 530 .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr), 531 }; 532 533 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = { 534 /* NT mV Trans mV db */ 535 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 536 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ 537 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */ 538 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200 350 4.9 */ 539 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 540 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 300 1.6 */ 541 { .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250 350 2.9 */ 542 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 543 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 544 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 545 }; 546 547 static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = { 548 .entries = _jsl_combo_phy_ddi_translations_edp_hbr2, 549 .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr2), 550 }; 551 552 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { 553 /* NT mV Trans mV db */ 554 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 555 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ 556 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 557 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ 558 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 559 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 560 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ 561 { .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 562 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */ 563 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 564 }; 565 566 static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = { 567 .entries = _dg1_combo_phy_ddi_translations_dp_rbr_hbr, 568 .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_rbr_hbr), 569 }; 570 571 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 572 /* NT mV Trans mV db */ 573 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 574 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ 575 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 576 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ 577 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 578 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 579 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ 580 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 581 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 582 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 583 }; 584 585 static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = { 586 .entries = _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, 587 .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_hbr2_hbr3), 588 }; 589 590 static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hbr[] = { 591 /* Voltage swing pre-emphasis */ 592 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ 593 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ 594 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */ 595 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */ 596 { .mg = { 0x21, 0x00, 0x00 } }, /* 1 0 */ 597 { .mg = { 0x2B, 0x00, 0x08 } }, /* 1 1 */ 598 { .mg = { 0x30, 0x00, 0x0F } }, /* 1 2 */ 599 { .mg = { 0x31, 0x00, 0x03 } }, /* 2 0 */ 600 { .mg = { 0x34, 0x00, 0x0B } }, /* 2 1 */ 601 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ 602 }; 603 604 static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr = { 605 .entries = _icl_mg_phy_ddi_translations_rbr_hbr, 606 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_rbr_hbr), 607 }; 608 609 static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 610 /* Voltage swing pre-emphasis */ 611 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ 612 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ 613 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */ 614 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */ 615 { .mg = { 0x26, 0x00, 0x00 } }, /* 1 0 */ 616 { .mg = { 0x2C, 0x00, 0x07 } }, /* 1 1 */ 617 { .mg = { 0x33, 0x00, 0x0C } }, /* 1 2 */ 618 { .mg = { 0x2E, 0x00, 0x00 } }, /* 2 0 */ 619 { .mg = { 0x36, 0x00, 0x09 } }, /* 2 1 */ 620 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ 621 }; 622 623 static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3 = { 624 .entries = _icl_mg_phy_ddi_translations_hbr2_hbr3, 625 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hbr2_hbr3), 626 }; 627 628 static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] = { 629 /* HDMI Preset VS Pre-emph */ 630 { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */ 631 { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */ 632 { .mg = { 0x29, 0x0, 0x0 } }, /* 3 650mV 0dB */ 633 { .mg = { 0x32, 0x0, 0x0 } }, /* 4 800mV 0dB */ 634 { .mg = { 0x3F, 0x0, 0x0 } }, /* 5 1000mV 0dB */ 635 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */ 636 { .mg = { 0x39, 0x0, 0x6 } }, /* 7 Full -1.8 dB */ 637 { .mg = { 0x38, 0x0, 0x7 } }, /* 8 Full -2 dB */ 638 { .mg = { 0x37, 0x0, 0x8 } }, /* 9 Full -2.5 dB */ 639 { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ 640 }; 641 642 static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = { 643 .entries = _icl_mg_phy_ddi_translations_hdmi, 644 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi), 645 .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1, 646 }; 647 648 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = { 649 /* VS pre-emp Non-trans mV Pre-emph dB */ 650 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ 651 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ 652 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ 653 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */ 654 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 655 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ 656 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 657 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 658 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ 659 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ 660 }; 661 662 static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr = { 663 .entries = _tgl_dkl_phy_ddi_translations_dp_hbr, 664 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr), 665 }; 666 667 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr2[] = { 668 /* VS pre-emp Non-trans mV Pre-emph dB */ 669 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ 670 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ 671 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ 672 { .dkl = { 0x0, 0x0, 0x19 } }, /* 0 3 400mV 9.5 dB */ 673 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 674 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ 675 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 676 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 677 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ 678 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ 679 }; 680 681 static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr2 = { 682 .entries = _tgl_dkl_phy_ddi_translations_dp_hbr2, 683 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr2), 684 }; 685 686 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[] = { 687 /* HDMI Preset VS Pre-emph */ 688 { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ 689 { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ 690 { .dkl = { 0x4, 0x0, 0x0 } }, /* 3 650mV 0dB */ 691 { .dkl = { 0x2, 0x0, 0x0 } }, /* 4 800mV 0dB */ 692 { .dkl = { 0x0, 0x0, 0x0 } }, /* 5 1000mV 0dB */ 693 { .dkl = { 0x0, 0x0, 0x5 } }, /* 6 Full -1.5 dB */ 694 { .dkl = { 0x0, 0x0, 0x6 } }, /* 7 Full -1.8 dB */ 695 { .dkl = { 0x0, 0x0, 0x7 } }, /* 8 Full -2 dB */ 696 { .dkl = { 0x0, 0x0, 0x8 } }, /* 9 Full -2.5 dB */ 697 { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */ 698 }; 699 700 static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = { 701 .entries = _tgl_dkl_phy_ddi_translations_hdmi, 702 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi), 703 .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1, 704 }; 705 706 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = { 707 /* NT mV Trans mV db */ 708 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 709 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 710 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 711 { .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 712 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 713 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 714 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 715 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 716 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 717 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 718 }; 719 720 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = { 721 .entries = _tgl_combo_phy_ddi_translations_dp_hbr, 722 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr), 723 }; 724 725 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = { 726 /* NT mV Trans mV db */ 727 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 728 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 729 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 730 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 731 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 732 { .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 733 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 734 { .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 735 { .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 736 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 737 }; 738 739 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = { 740 .entries = _tgl_combo_phy_ddi_translations_dp_hbr2, 741 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr2), 742 }; 743 744 static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { 745 /* NT mV Trans mV db */ 746 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 747 { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ 748 { .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */ 749 { .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */ 750 { .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 751 { .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 752 { .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ 753 { .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 754 { .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */ 755 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 756 }; 757 758 static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = { 759 .entries = _tgl_uy_combo_phy_ddi_translations_dp_hbr2, 760 .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_ddi_translations_dp_hbr2), 761 }; 762 763 /* 764 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries 765 * that DisplayPort specification requires 766 */ 767 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { 768 /* VS pre-emp */ 769 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */ 770 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */ 771 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 2 */ 772 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 3 */ 773 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 0 */ 774 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 1 */ 775 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 2 */ 776 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 0 */ 777 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */ 778 }; 779 780 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = { 781 .entries = _tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 782 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_edp_hbr2_hobl), 783 }; 784 785 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = { 786 /* NT mV Trans mV db */ 787 { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 788 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 789 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 790 { .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350 900 8.2 */ 791 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 792 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 793 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 794 { .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */ 795 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 796 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 797 }; 798 799 static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = { 800 .entries = _rkl_combo_phy_ddi_translations_dp_hbr, 801 .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr), 802 }; 803 804 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 805 /* NT mV Trans mV db */ 806 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 807 { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ 808 { .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */ 809 { .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */ 810 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 811 { .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */ 812 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 813 { .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 814 { .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600 900 3.5 */ 815 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 816 }; 817 818 static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = { 819 .entries = _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, 820 .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), 821 }; 822 823 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 824 /* NT mV Trans mV db */ 825 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 826 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 827 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */ 828 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ 829 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 830 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */ 831 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ 832 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 833 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 834 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 835 }; 836 837 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = { 838 .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3, 839 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3), 840 }; 841 842 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = { 843 /* NT mV Trans mV db */ 844 { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200 200 0.0 */ 845 { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200 250 1.9 */ 846 { .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } }, /* 200 300 3.5 */ 847 { .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } }, /* 200 350 4.9 */ 848 { .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */ 849 { .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ 850 { .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */ 851 { .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } }, /* 300 300 0.0 */ 852 { .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 853 { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */ 854 }; 855 856 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = { 857 .entries = _adls_combo_phy_ddi_translations_edp_hbr2, 858 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2), 859 }; 860 861 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = { 862 /* NT mV Trans mV db */ 863 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 864 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 865 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */ 866 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ 867 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 868 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */ 869 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ 870 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 871 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 872 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 873 }; 874 875 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = { 876 .entries = _adls_combo_phy_ddi_translations_edp_hbr3, 877 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3), 878 }; 879 880 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_hdmi[] = { 881 /* NT mV Trans mV db */ 882 { .icl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ 883 { .icl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 884 { .icl = { 0xA, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */ 885 { .icl = { 0xA, 0x78, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */ 886 { .icl = { 0xB, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1000 1000 0.0 Re-timer */ 887 { .icl = { 0xB, 0x7F, 0x3B, 0x00, 0x04 } }, /* Full Red -1.5 */ 888 { .icl = { 0xB, 0x7F, 0x39, 0x00, 0x06 } }, /* Full Red -1.8 */ 889 { .icl = { 0xB, 0x7F, 0x37, 0x00, 0x08 } }, /* Full Red -2.0 CRLS */ 890 { .icl = { 0xB, 0x7F, 0x35, 0x00, 0x0A } }, /* Full Red -2.5 */ 891 { .icl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } }, /* Full Red -3.0 */ 892 }; 893 894 static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_hdmi = { 895 .entries = _adlp_combo_phy_ddi_translations_hdmi, 896 .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi), 897 .hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi) - 1, 898 }; 899 900 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr[] = { 901 /* NT mV Trans mV db */ 902 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 903 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 904 { .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */ 905 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ 906 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 907 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 908 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 909 { .icl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */ 910 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 911 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 912 }; 913 914 static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr = { 915 .entries = _adlp_combo_phy_ddi_translations_dp_hbr, 916 .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr), 917 }; 918 919 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 920 /* NT mV Trans mV db */ 921 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 922 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 923 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 924 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 925 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 926 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 927 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ 928 { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 929 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */ 930 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 931 }; 932 933 static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr2_hbr3 = { 934 .entries = _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, 935 .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr2_hbr3), 936 }; 937 938 static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_hbr3 = { 939 .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 940 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), 941 }; 942 943 static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_up_to_hbr2 = { 944 .entries = _icl_combo_phy_ddi_translations_edp_hbr2, 945 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), 946 }; 947 948 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr[] = { 949 /* VS pre-emp Non-trans mV Pre-emph dB */ 950 { .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */ 951 { .dkl = { 0x5, 0x0, 0x06 } }, /* 0 1 400mV 3.5 dB */ 952 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ 953 { .dkl = { 0x0, 0x0, 0x17 } }, /* 0 3 400mV 9.5 dB */ 954 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 955 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ 956 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 957 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 958 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ 959 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ 960 }; 961 962 static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr = { 963 .entries = _adlp_dkl_phy_ddi_translations_dp_hbr, 964 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr), 965 }; 966 967 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3[] = { 968 /* VS pre-emp Non-trans mV Pre-emph dB */ 969 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ 970 { .dkl = { 0x5, 0x0, 0x04 } }, /* 0 1 400mV 3.5 dB */ 971 { .dkl = { 0x2, 0x0, 0x0A } }, /* 0 2 400mV 6 dB */ 972 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */ 973 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 974 { .dkl = { 0x2, 0x0, 0x06 } }, /* 1 1 600mV 3.5 dB */ 975 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 976 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 977 { .dkl = { 0x0, 0x0, 0x09 } }, /* 2 1 800mV 3.5 dB */ 978 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ 979 }; 980 981 static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3 = { 982 .entries = _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, 983 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), 984 }; 985 986 static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { 987 { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ 988 { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ 989 { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ 990 { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ 991 { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ 992 { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ 993 { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ 994 { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ 995 { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ 996 { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ 997 }; 998 999 static const struct intel_ddi_buf_trans dg2_snps_translations = { 1000 .entries = _dg2_snps_translations, 1001 .num_entries = ARRAY_SIZE(_dg2_snps_translations), 1002 .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, 1003 }; 1004 1005 static const union intel_ddi_buf_trans_entry _dg2_snps_translations_uhbr[] = { 1006 { .snps = { 62, 0, 0 } }, /* preset 0 */ 1007 { .snps = { 56, 0, 6 } }, /* preset 1 */ 1008 { .snps = { 51, 0, 11 } }, /* preset 2 */ 1009 { .snps = { 48, 0, 14 } }, /* preset 3 */ 1010 { .snps = { 43, 0, 19 } }, /* preset 4 */ 1011 { .snps = { 59, 3, 0 } }, /* preset 5 */ 1012 { .snps = { 53, 3, 6 } }, /* preset 6 */ 1013 { .snps = { 49, 3, 10 } }, /* preset 7 */ 1014 { .snps = { 45, 3, 14 } }, /* preset 8 */ 1015 { .snps = { 42, 3, 17 } }, /* preset 9 */ 1016 { .snps = { 56, 6, 0 } }, /* preset 10 */ 1017 { .snps = { 50, 6, 6 } }, /* preset 11 */ 1018 { .snps = { 47, 6, 9 } }, /* preset 12 */ 1019 { .snps = { 42, 6, 14 } }, /* preset 13 */ 1020 { .snps = { 46, 8, 8 } }, /* preset 14 */ 1021 { .snps = { 56, 3, 3 } }, /* preset 15 */ 1022 }; 1023 1024 static const struct intel_ddi_buf_trans dg2_snps_translations_uhbr = { 1025 .entries = _dg2_snps_translations_uhbr, 1026 .num_entries = ARRAY_SIZE(_dg2_snps_translations_uhbr), 1027 }; 1028 1029 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) 1030 { 1031 return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 1032 } 1033 1034 static const struct intel_ddi_buf_trans * 1035 intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) 1036 { 1037 *num_entries = ddi_translations->num_entries; 1038 return ddi_translations; 1039 } 1040 1041 static const struct intel_ddi_buf_trans * 1042 hsw_get_buf_trans(struct intel_encoder *encoder, 1043 const struct intel_crtc_state *crtc_state, 1044 int *n_entries) 1045 { 1046 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1047 return intel_get_buf_trans(&hsw_ddi_translations_fdi, n_entries); 1048 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1049 return intel_get_buf_trans(&hsw_ddi_translations_hdmi, n_entries); 1050 else 1051 return intel_get_buf_trans(&hsw_ddi_translations_dp, n_entries); 1052 } 1053 1054 static const struct intel_ddi_buf_trans * 1055 bdw_get_buf_trans(struct intel_encoder *encoder, 1056 const struct intel_crtc_state *crtc_state, 1057 int *n_entries) 1058 { 1059 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1060 1061 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1062 return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries); 1063 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1064 return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries); 1065 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1066 i915->vbt.edp.low_vswing) 1067 return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries); 1068 else 1069 return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries); 1070 } 1071 1072 static int skl_buf_trans_num_entries(enum port port, int n_entries) 1073 { 1074 /* Only DDIA and DDIE can select the 10th register with DP */ 1075 if (port == PORT_A || port == PORT_E) 1076 return min(n_entries, 10); 1077 else 1078 return min(n_entries, 9); 1079 } 1080 1081 static const struct intel_ddi_buf_trans * 1082 _skl_get_buf_trans_dp(struct intel_encoder *encoder, 1083 const struct intel_ddi_buf_trans *ddi_translations, 1084 int *n_entries) 1085 { 1086 ddi_translations = intel_get_buf_trans(ddi_translations, n_entries); 1087 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 1088 return ddi_translations; 1089 } 1090 1091 static const struct intel_ddi_buf_trans * 1092 skl_y_get_buf_trans(struct intel_encoder *encoder, 1093 const struct intel_crtc_state *crtc_state, 1094 int *n_entries) 1095 { 1096 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1097 1098 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1099 return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); 1100 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1101 i915->vbt.edp.low_vswing) 1102 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); 1103 else 1104 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries); 1105 } 1106 1107 static const struct intel_ddi_buf_trans * 1108 skl_u_get_buf_trans(struct intel_encoder *encoder, 1109 const struct intel_crtc_state *crtc_state, 1110 int *n_entries) 1111 { 1112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1113 1114 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1115 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1116 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1117 i915->vbt.edp.low_vswing) 1118 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); 1119 else 1120 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries); 1121 } 1122 1123 static const struct intel_ddi_buf_trans * 1124 skl_get_buf_trans(struct intel_encoder *encoder, 1125 const struct intel_crtc_state *crtc_state, 1126 int *n_entries) 1127 { 1128 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1129 1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1131 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1132 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1133 i915->vbt.edp.low_vswing) 1134 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); 1135 else 1136 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries); 1137 } 1138 1139 static const struct intel_ddi_buf_trans * 1140 kbl_y_get_buf_trans(struct intel_encoder *encoder, 1141 const struct intel_crtc_state *crtc_state, 1142 int *n_entries) 1143 { 1144 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1145 1146 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1147 return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); 1148 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1149 i915->vbt.edp.low_vswing) 1150 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); 1151 else 1152 return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries); 1153 } 1154 1155 static const struct intel_ddi_buf_trans * 1156 kbl_u_get_buf_trans(struct intel_encoder *encoder, 1157 const struct intel_crtc_state *crtc_state, 1158 int *n_entries) 1159 { 1160 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1161 1162 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1163 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1164 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1165 i915->vbt.edp.low_vswing) 1166 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); 1167 else 1168 return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries); 1169 } 1170 1171 static const struct intel_ddi_buf_trans * 1172 kbl_get_buf_trans(struct intel_encoder *encoder, 1173 const struct intel_crtc_state *crtc_state, 1174 int *n_entries) 1175 { 1176 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1177 1178 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1179 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1180 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1181 i915->vbt.edp.low_vswing) 1182 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); 1183 else 1184 return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries); 1185 } 1186 1187 static const struct intel_ddi_buf_trans * 1188 bxt_get_buf_trans(struct intel_encoder *encoder, 1189 const struct intel_crtc_state *crtc_state, 1190 int *n_entries) 1191 { 1192 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1193 1194 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1195 return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); 1196 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1197 i915->vbt.edp.low_vswing) 1198 return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries); 1199 else 1200 return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); 1201 } 1202 1203 static const struct intel_ddi_buf_trans * 1204 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1205 const struct intel_crtc_state *crtc_state, 1206 int *n_entries) 1207 { 1208 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1209 n_entries); 1210 } 1211 1212 static const struct intel_ddi_buf_trans * 1213 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1214 const struct intel_crtc_state *crtc_state, 1215 int *n_entries) 1216 { 1217 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1218 1219 if (crtc_state->port_clock > 540000) { 1220 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1221 n_entries); 1222 } else if (dev_priv->vbt.edp.low_vswing) { 1223 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1224 n_entries); 1225 } 1226 1227 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1228 } 1229 1230 static const struct intel_ddi_buf_trans * 1231 icl_get_combo_buf_trans(struct intel_encoder *encoder, 1232 const struct intel_crtc_state *crtc_state, 1233 int *n_entries) 1234 { 1235 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1236 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1237 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1238 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1239 else 1240 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1241 } 1242 1243 static const struct intel_ddi_buf_trans * 1244 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, 1245 const struct intel_crtc_state *crtc_state, 1246 int *n_entries) 1247 { 1248 if (crtc_state->port_clock > 270000) { 1249 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hbr2_hbr3, 1250 n_entries); 1251 } else { 1252 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_rbr_hbr, 1253 n_entries); 1254 } 1255 } 1256 1257 static const struct intel_ddi_buf_trans * 1258 icl_get_mg_buf_trans(struct intel_encoder *encoder, 1259 const struct intel_crtc_state *crtc_state, 1260 int *n_entries) 1261 { 1262 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1263 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, n_entries); 1264 else 1265 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); 1266 } 1267 1268 static const struct intel_ddi_buf_trans * 1269 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1270 const struct intel_crtc_state *crtc_state, 1271 int *n_entries) 1272 { 1273 if (crtc_state->port_clock > 270000) 1274 return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, n_entries); 1275 else 1276 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); 1277 } 1278 1279 static const struct intel_ddi_buf_trans * 1280 ehl_get_combo_buf_trans(struct intel_encoder *encoder, 1281 const struct intel_crtc_state *crtc_state, 1282 int *n_entries) 1283 { 1284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1285 1286 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1287 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1288 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1289 dev_priv->vbt.edp.low_vswing) 1290 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1291 else 1292 return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, n_entries); 1293 } 1294 1295 static const struct intel_ddi_buf_trans * 1296 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1297 const struct intel_crtc_state *crtc_state, 1298 int *n_entries) 1299 { 1300 if (crtc_state->port_clock > 270000) 1301 return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, n_entries); 1302 else 1303 return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, n_entries); 1304 } 1305 1306 static const struct intel_ddi_buf_trans * 1307 jsl_get_combo_buf_trans(struct intel_encoder *encoder, 1308 const struct intel_crtc_state *crtc_state, 1309 int *n_entries) 1310 { 1311 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1312 1313 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1314 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1315 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1316 dev_priv->vbt.edp.low_vswing) 1317 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1318 else 1319 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); 1320 } 1321 1322 static const struct intel_ddi_buf_trans * 1323 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1324 const struct intel_crtc_state *crtc_state, 1325 int *n_entries) 1326 { 1327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1328 1329 if (crtc_state->port_clock > 270000) { 1330 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1331 return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, 1332 n_entries); 1333 } else { 1334 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr2, 1335 n_entries); 1336 } 1337 } else { 1338 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, 1339 n_entries); 1340 } 1341 } 1342 1343 static const struct intel_ddi_buf_trans * 1344 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1345 const struct intel_crtc_state *crtc_state, 1346 int *n_entries) 1347 { 1348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1349 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1350 1351 if (crtc_state->port_clock > 540000) { 1352 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1353 n_entries); 1354 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1355 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 1356 n_entries); 1357 } else if (dev_priv->vbt.edp.low_vswing) { 1358 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1359 n_entries); 1360 } 1361 1362 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1363 } 1364 1365 static const struct intel_ddi_buf_trans * 1366 tgl_get_combo_buf_trans(struct intel_encoder *encoder, 1367 const struct intel_crtc_state *crtc_state, 1368 int *n_entries) 1369 { 1370 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1371 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1372 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1373 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1374 else 1375 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1376 } 1377 1378 static const struct intel_ddi_buf_trans * 1379 dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1380 const struct intel_crtc_state *crtc_state, 1381 int *n_entries) 1382 { 1383 if (crtc_state->port_clock > 270000) 1384 return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, 1385 n_entries); 1386 else 1387 return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, 1388 n_entries); 1389 } 1390 1391 static const struct intel_ddi_buf_trans * 1392 dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1393 const struct intel_crtc_state *crtc_state, 1394 int *n_entries) 1395 { 1396 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1397 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1398 1399 if (crtc_state->port_clock > 540000) 1400 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1401 n_entries); 1402 else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) 1403 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 1404 n_entries); 1405 else if (dev_priv->vbt.edp.low_vswing) 1406 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1407 n_entries); 1408 else 1409 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1410 } 1411 1412 static const struct intel_ddi_buf_trans * 1413 dg1_get_combo_buf_trans(struct intel_encoder *encoder, 1414 const struct intel_crtc_state *crtc_state, 1415 int *n_entries) 1416 { 1417 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1418 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1419 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1420 return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1421 else 1422 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1423 } 1424 1425 static const struct intel_ddi_buf_trans * 1426 rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1427 const struct intel_crtc_state *crtc_state, 1428 int *n_entries) 1429 { 1430 if (crtc_state->port_clock > 270000) 1431 return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); 1432 else 1433 return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); 1434 } 1435 1436 static const struct intel_ddi_buf_trans * 1437 rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1438 const struct intel_crtc_state *crtc_state, 1439 int *n_entries) 1440 { 1441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1442 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1443 1444 if (crtc_state->port_clock > 540000) { 1445 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1446 n_entries); 1447 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1448 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 1449 n_entries); 1450 } else if (dev_priv->vbt.edp.low_vswing) { 1451 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1452 n_entries); 1453 } 1454 1455 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1456 } 1457 1458 static const struct intel_ddi_buf_trans * 1459 rkl_get_combo_buf_trans(struct intel_encoder *encoder, 1460 const struct intel_crtc_state *crtc_state, 1461 int *n_entries) 1462 { 1463 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1464 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1465 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1466 return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1467 else 1468 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1469 } 1470 1471 static const struct intel_ddi_buf_trans * 1472 adls_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1473 const struct intel_crtc_state *crtc_state, 1474 int *n_entries) 1475 { 1476 if (crtc_state->port_clock > 270000) 1477 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); 1478 else 1479 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries); 1480 } 1481 1482 static const struct intel_ddi_buf_trans * 1483 adls_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1484 const struct intel_crtc_state *crtc_state, 1485 int *n_entries) 1486 { 1487 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1488 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1489 1490 if (crtc_state->port_clock > 540000) 1491 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries); 1492 else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed) 1493 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); 1494 else if (i915->vbt.edp.low_vswing) 1495 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries); 1496 else 1497 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1498 } 1499 1500 static const struct intel_ddi_buf_trans * 1501 adls_get_combo_buf_trans(struct intel_encoder *encoder, 1502 const struct intel_crtc_state *crtc_state, 1503 int *n_entries) 1504 { 1505 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1506 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1507 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1508 return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1509 else 1510 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1511 } 1512 1513 static const struct intel_ddi_buf_trans * 1514 adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1515 const struct intel_crtc_state *crtc_state, 1516 int *n_entries) 1517 { 1518 if (crtc_state->port_clock > 270000) 1519 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); 1520 else 1521 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr, n_entries); 1522 } 1523 1524 static const struct intel_ddi_buf_trans * 1525 adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1526 const struct intel_crtc_state *crtc_state, 1527 int *n_entries) 1528 { 1529 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1530 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1531 1532 if (crtc_state->port_clock > 540000) { 1533 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_hbr3, 1534 n_entries); 1535 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1536 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 1537 n_entries); 1538 } else if (dev_priv->vbt.edp.low_vswing) { 1539 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_up_to_hbr2, 1540 n_entries); 1541 } 1542 1543 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1544 } 1545 1546 static const struct intel_ddi_buf_trans * 1547 adlp_get_combo_buf_trans(struct intel_encoder *encoder, 1548 const struct intel_crtc_state *crtc_state, 1549 int *n_entries) 1550 { 1551 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1552 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_hdmi, n_entries); 1553 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1554 return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1555 else 1556 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1557 } 1558 1559 static const struct intel_ddi_buf_trans * 1560 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1561 const struct intel_crtc_state *crtc_state, 1562 int *n_entries) 1563 { 1564 if (crtc_state->port_clock > 270000) { 1565 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr2, 1566 n_entries); 1567 } else { 1568 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr, 1569 n_entries); 1570 } 1571 } 1572 1573 static const struct intel_ddi_buf_trans * 1574 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, 1575 const struct intel_crtc_state *crtc_state, 1576 int *n_entries) 1577 { 1578 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1579 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); 1580 else 1581 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1582 } 1583 1584 static const struct intel_ddi_buf_trans * 1585 adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1586 const struct intel_crtc_state *crtc_state, 1587 int *n_entries) 1588 { 1589 if (crtc_state->port_clock > 270000) { 1590 return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, 1591 n_entries); 1592 } else { 1593 return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr, 1594 n_entries); 1595 } 1596 } 1597 1598 static const struct intel_ddi_buf_trans * 1599 adlp_get_dkl_buf_trans(struct intel_encoder *encoder, 1600 const struct intel_crtc_state *crtc_state, 1601 int *n_entries) 1602 { 1603 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1604 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); 1605 else 1606 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1607 } 1608 1609 static const struct intel_ddi_buf_trans * 1610 dg2_get_snps_buf_trans(struct intel_encoder *encoder, 1611 const struct intel_crtc_state *crtc_state, 1612 int *n_entries) 1613 { 1614 if (crtc_state->port_clock > 1000000) 1615 return intel_get_buf_trans(&dg2_snps_translations_uhbr, n_entries); 1616 else 1617 return intel_get_buf_trans(&dg2_snps_translations, n_entries); 1618 } 1619 1620 int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, 1621 const struct intel_crtc_state *crtc_state, 1622 int *default_entry) 1623 { 1624 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1625 const struct intel_ddi_buf_trans *ddi_translations; 1626 int n_entries; 1627 1628 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1629 1630 if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { 1631 *default_entry = 0; 1632 return 0; 1633 } 1634 1635 *default_entry = ddi_translations->hdmi_default_entry; 1636 1637 return n_entries; 1638 } 1639 1640 void intel_ddi_buf_trans_init(struct intel_encoder *encoder) 1641 { 1642 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1643 enum phy phy = intel_port_to_phy(i915, encoder->port); 1644 1645 if (IS_DG2(i915)) { 1646 encoder->get_buf_trans = dg2_get_snps_buf_trans; 1647 } else if (IS_ALDERLAKE_P(i915)) { 1648 if (intel_phy_is_combo(i915, phy)) 1649 encoder->get_buf_trans = adlp_get_combo_buf_trans; 1650 else 1651 encoder->get_buf_trans = adlp_get_dkl_buf_trans; 1652 } else if (IS_ALDERLAKE_S(i915)) { 1653 encoder->get_buf_trans = adls_get_combo_buf_trans; 1654 } else if (IS_ROCKETLAKE(i915)) { 1655 encoder->get_buf_trans = rkl_get_combo_buf_trans; 1656 } else if (IS_DG1(i915)) { 1657 encoder->get_buf_trans = dg1_get_combo_buf_trans; 1658 } else if (DISPLAY_VER(i915) >= 12) { 1659 if (intel_phy_is_combo(i915, phy)) 1660 encoder->get_buf_trans = tgl_get_combo_buf_trans; 1661 else 1662 encoder->get_buf_trans = tgl_get_dkl_buf_trans; 1663 } else if (DISPLAY_VER(i915) == 11) { 1664 if (IS_PLATFORM(i915, INTEL_JASPERLAKE)) 1665 encoder->get_buf_trans = jsl_get_combo_buf_trans; 1666 else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) 1667 encoder->get_buf_trans = ehl_get_combo_buf_trans; 1668 else if (intel_phy_is_combo(i915, phy)) 1669 encoder->get_buf_trans = icl_get_combo_buf_trans; 1670 else 1671 encoder->get_buf_trans = icl_get_mg_buf_trans; 1672 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 1673 encoder->get_buf_trans = bxt_get_buf_trans; 1674 } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) { 1675 encoder->get_buf_trans = kbl_y_get_buf_trans; 1676 } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) { 1677 encoder->get_buf_trans = kbl_u_get_buf_trans; 1678 } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { 1679 encoder->get_buf_trans = kbl_get_buf_trans; 1680 } else if (IS_SKL_ULX(i915)) { 1681 encoder->get_buf_trans = skl_y_get_buf_trans; 1682 } else if (IS_SKL_ULT(i915)) { 1683 encoder->get_buf_trans = skl_u_get_buf_trans; 1684 } else if (IS_SKYLAKE(i915)) { 1685 encoder->get_buf_trans = skl_get_buf_trans; 1686 } else if (IS_BROADWELL(i915)) { 1687 encoder->get_buf_trans = bdw_get_buf_trans; 1688 } else { 1689 encoder->get_buf_trans = hsw_get_buf_trans; 1690 } 1691 } 1692