1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v13_0.h" 29 #include "smu13_driver_if_v13_0_5.h" 30 #include "smu_v13_0_5_ppt.h" 31 #include "smu_v13_0_5_ppsmc.h" 32 #include "smu_v13_0_5_pmfw.h" 33 #include "smu_cmn.h" 34 35 /* 36 * DO NOT use these for err/warn/info/debug messages. 37 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 38 * They are more MGPU friendly. 39 */ 40 #undef pr_err 41 #undef pr_warn 42 #undef pr_info 43 #undef pr_debug 44 45 #define FEATURE_MASK(feature) (1ULL << feature) 46 #define SMC_DPM_FEATURE ( \ 47 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 48 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 49 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 50 FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ 51 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \ 54 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \ 55 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)) 56 57 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = { 58 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 59 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 60 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1), 61 MSG_MAP(DisableGfxOff, PPSMC_MSG_DisableGfxOff, 1), 62 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 63 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 64 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 65 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1), 66 MSG_MAP(Spare0, PPSMC_MSG_Spare0, 1), 67 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 70 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 71 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu , 1), 72 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 73 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), 74 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 75 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 76 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 77 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 78 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 79 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), 80 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), 81 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 82 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 83 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 84 }; 85 86 static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = { 87 FEA_MAP(DATA_CALCULATION), 88 FEA_MAP(PPT), 89 FEA_MAP(TDC), 90 FEA_MAP(THERMAL), 91 FEA_MAP(PROCHOT), 92 FEA_MAP(CCLK_DPM), 93 FEA_MAP_REVERSE(FCLK), 94 FEA_MAP(LCLK_DPM), 95 FEA_MAP(DF_CSTATES), 96 FEA_MAP(FAN_CONTROLLER), 97 FEA_MAP(CPPC), 98 FEA_MAP_HALF_REVERSE(GFX), 99 FEA_MAP(DS_GFXCLK), 100 FEA_MAP(S0I3), 101 FEA_MAP(VCN_DPM), 102 FEA_MAP(DS_VCN), 103 FEA_MAP(DCFCLK_DPM), 104 FEA_MAP(ATHUB_PG), 105 FEA_MAP_REVERSE(SOCCLK), 106 FEA_MAP(SHUBCLK_DPM), 107 FEA_MAP(GFXOFF), 108 }; 109 110 static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = { 111 TAB_MAP_VALID(WATERMARKS), 112 TAB_MAP_VALID(SMU_METRICS), 113 TAB_MAP_VALID(CUSTOM_DPM), 114 TAB_MAP_VALID(DPMCLOCKS), 115 }; 116 117 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu) 118 { 119 struct smu_table_context *smu_table = &smu->smu_table; 120 struct smu_table *tables = smu_table->tables; 121 122 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 123 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 124 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 125 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 126 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 127 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 128 129 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 130 if (!smu_table->clocks_table) 131 goto err0_out; 132 133 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 134 if (!smu_table->metrics_table) 135 goto err1_out; 136 smu_table->metrics_time = 0; 137 138 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 139 if (!smu_table->watermarks_table) 140 goto err2_out; 141 142 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 143 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 144 if (!smu_table->gpu_metrics_table) 145 goto err3_out; 146 147 return 0; 148 149 err3_out: 150 kfree(smu_table->watermarks_table); 151 err2_out: 152 kfree(smu_table->metrics_table); 153 err1_out: 154 kfree(smu_table->clocks_table); 155 err0_out: 156 return -ENOMEM; 157 } 158 159 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu) 160 { 161 struct smu_table_context *smu_table = &smu->smu_table; 162 163 kfree(smu_table->clocks_table); 164 smu_table->clocks_table = NULL; 165 166 kfree(smu_table->metrics_table); 167 smu_table->metrics_table = NULL; 168 169 kfree(smu_table->watermarks_table); 170 smu_table->watermarks_table = NULL; 171 172 return 0; 173 } 174 175 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en) 176 { 177 struct amdgpu_device *adev = smu->adev; 178 int ret = 0; 179 180 if (!en && !adev->in_s0ix) 181 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); 182 183 return ret; 184 } 185 186 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 187 { 188 int ret = 0; 189 190 /* vcn dpm on is a prerequisite for vcn power gate messages */ 191 if (enable) 192 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 193 0, NULL); 194 else 195 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 196 0, NULL); 197 198 return ret; 199 } 200 201 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 202 { 203 int ret = 0; 204 205 if (enable) 206 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 207 0, NULL); 208 else 209 ret = smu_cmn_send_smc_msg_with_param(smu, 210 SMU_MSG_PowerDownJpeg, 0, 211 NULL); 212 213 return ret; 214 } 215 216 217 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu) 218 { 219 int ret = 0; 220 uint64_t feature_enabled; 221 222 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 223 224 if (ret) 225 return false; 226 227 return !!(feature_enabled & SMC_DPM_FEATURE); 228 } 229 230 static int smu_v13_0_5_post_smu_init(struct smu_context *smu) 231 { 232 /* 233 struct amdgpu_device *adev = smu->adev; 234 */ 235 int ret = 0; 236 237 /* allow message will be sent after enable gfxoff on smu 13.0.5 */ 238 /* 239 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 240 if (ret) 241 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 242 */ 243 return ret; 244 } 245 246 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type) 247 { 248 int ret = 0; 249 250 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL); 251 if (ret) 252 dev_err(smu->adev->dev, "Failed to mode reset!\n"); 253 254 return ret; 255 } 256 257 static int smu_v13_0_5_mode2_reset(struct smu_context *smu) 258 { 259 return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2); 260 } 261 262 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu, 263 MetricsMember_t member, 264 uint32_t *value) 265 { 266 struct smu_table_context *smu_table = &smu->smu_table; 267 268 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 269 int ret = 0; 270 271 ret = smu_cmn_get_metrics_table(smu, NULL, false); 272 if (ret) 273 return ret; 274 275 switch (member) { 276 case METRICS_AVERAGE_GFXCLK: 277 *value = metrics->GfxclkFrequency; 278 break; 279 case METRICS_AVERAGE_SOCCLK: 280 *value = metrics->SocclkFrequency; 281 break; 282 case METRICS_AVERAGE_VCLK: 283 *value = metrics->VclkFrequency; 284 break; 285 case METRICS_AVERAGE_DCLK: 286 *value = metrics->DclkFrequency; 287 break; 288 case METRICS_AVERAGE_UCLK: 289 *value = metrics->MemclkFrequency; 290 break; 291 case METRICS_AVERAGE_GFXACTIVITY: 292 *value = metrics->GfxActivity / 100; 293 break; 294 case METRICS_AVERAGE_VCNACTIVITY: 295 *value = metrics->UvdActivity; 296 break; 297 case METRICS_AVERAGE_SOCKETPOWER: 298 *value = (metrics->CurrentSocketPower << 8) / 1000; 299 break; 300 case METRICS_TEMPERATURE_EDGE: 301 *value = metrics->GfxTemperature / 100 * 302 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 303 break; 304 case METRICS_TEMPERATURE_HOTSPOT: 305 *value = metrics->SocTemperature / 100 * 306 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 307 break; 308 case METRICS_THROTTLER_STATUS: 309 *value = metrics->ThrottlerStatus; 310 break; 311 case METRICS_VOLTAGE_VDDGFX: 312 *value = metrics->Voltage[0]; 313 break; 314 case METRICS_VOLTAGE_VDDSOC: 315 *value = metrics->Voltage[1]; 316 break; 317 #if 0 318 case METRICS_SS_APU_SHARE: 319 /* return the percentage of APU power with respect to APU's power limit. 320 * percentage is reported, this isn't boost value. Smartshift power 321 * boost/shift is only when the percentage is more than 100. 322 */ 323 if (metrics->StapmOpnLimit > 0) 324 *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit; 325 else 326 *value = 0; 327 break; 328 case METRICS_SS_DGPU_SHARE: 329 /* return the percentage of dGPU power with respect to dGPU's power limit. 330 * percentage is reported, this isn't boost value. Smartshift power 331 * boost/shift is only when the percentage is more than 100. 332 */ 333 if ((metrics->dGpuPower > 0) && 334 (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)) 335 *value = (metrics->dGpuPower * 100) / 336 (metrics->StapmCurrentLimit - metrics->StapmOpnLimit); 337 else 338 *value = 0; 339 break; 340 #endif 341 default: 342 *value = UINT_MAX; 343 break; 344 } 345 346 return ret; 347 } 348 349 static int smu_v13_0_5_read_sensor(struct smu_context *smu, 350 enum amd_pp_sensors sensor, 351 void *data, uint32_t *size) 352 { 353 int ret = 0; 354 355 if (!data || !size) 356 return -EINVAL; 357 358 switch (sensor) { 359 case AMDGPU_PP_SENSOR_GPU_LOAD: 360 ret = smu_v13_0_5_get_smu_metrics_data(smu, 361 METRICS_AVERAGE_GFXACTIVITY, 362 (uint32_t *)data); 363 *size = 4; 364 break; 365 case AMDGPU_PP_SENSOR_GPU_POWER: 366 ret = smu_v13_0_5_get_smu_metrics_data(smu, 367 METRICS_AVERAGE_SOCKETPOWER, 368 (uint32_t *)data); 369 *size = 4; 370 break; 371 case AMDGPU_PP_SENSOR_EDGE_TEMP: 372 ret = smu_v13_0_5_get_smu_metrics_data(smu, 373 METRICS_TEMPERATURE_EDGE, 374 (uint32_t *)data); 375 *size = 4; 376 break; 377 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 378 ret = smu_v13_0_5_get_smu_metrics_data(smu, 379 METRICS_TEMPERATURE_HOTSPOT, 380 (uint32_t *)data); 381 *size = 4; 382 break; 383 case AMDGPU_PP_SENSOR_GFX_MCLK: 384 ret = smu_v13_0_5_get_smu_metrics_data(smu, 385 METRICS_AVERAGE_UCLK, 386 (uint32_t *)data); 387 *(uint32_t *)data *= 100; 388 *size = 4; 389 break; 390 case AMDGPU_PP_SENSOR_GFX_SCLK: 391 ret = smu_v13_0_5_get_smu_metrics_data(smu, 392 METRICS_AVERAGE_GFXCLK, 393 (uint32_t *)data); 394 *(uint32_t *)data *= 100; 395 *size = 4; 396 break; 397 case AMDGPU_PP_SENSOR_VDDGFX: 398 ret = smu_v13_0_5_get_smu_metrics_data(smu, 399 METRICS_VOLTAGE_VDDGFX, 400 (uint32_t *)data); 401 *size = 4; 402 break; 403 case AMDGPU_PP_SENSOR_VDDNB: 404 ret = smu_v13_0_5_get_smu_metrics_data(smu, 405 METRICS_VOLTAGE_VDDSOC, 406 (uint32_t *)data); 407 *size = 4; 408 break; 409 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 410 ret = smu_v13_0_5_get_smu_metrics_data(smu, 411 METRICS_SS_APU_SHARE, 412 (uint32_t *)data); 413 *size = 4; 414 break; 415 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 416 ret = smu_v13_0_5_get_smu_metrics_data(smu, 417 METRICS_SS_DGPU_SHARE, 418 (uint32_t *)data); 419 *size = 4; 420 break; 421 default: 422 ret = -EOPNOTSUPP; 423 break; 424 } 425 426 return ret; 427 } 428 429 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu, 430 struct pp_smu_wm_range_sets *clock_ranges) 431 { 432 int i; 433 int ret = 0; 434 Watermarks_t *table = smu->smu_table.watermarks_table; 435 436 if (!table || !clock_ranges) 437 return -EINVAL; 438 439 if (clock_ranges) { 440 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 441 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 442 return -EINVAL; 443 444 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 445 table->WatermarkRow[WM_DCFCLK][i].MinClock = 446 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 447 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 448 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 449 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 450 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 451 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 452 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 453 454 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 455 clock_ranges->reader_wm_sets[i].wm_inst; 456 } 457 458 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 459 table->WatermarkRow[WM_SOCCLK][i].MinClock = 460 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 461 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 462 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 463 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 464 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 465 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 466 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 467 468 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 469 clock_ranges->writer_wm_sets[i].wm_inst; 470 } 471 472 smu->watermarks_bitmap |= WATERMARKS_EXIST; 473 } 474 475 /* pass data to smu controller */ 476 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 477 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 478 ret = smu_cmn_write_watermarks_table(smu); 479 if (ret) { 480 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 481 return ret; 482 } 483 smu->watermarks_bitmap |= WATERMARKS_LOADED; 484 } 485 486 return 0; 487 } 488 489 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu, 490 void **table) 491 { 492 struct smu_table_context *smu_table = &smu->smu_table; 493 struct gpu_metrics_v2_1 *gpu_metrics = 494 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 495 SmuMetrics_t metrics; 496 int ret = 0; 497 498 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 499 if (ret) 500 return ret; 501 502 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 503 504 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 505 gpu_metrics->temperature_soc = metrics.SocTemperature; 506 /* 507 memcpy(&gpu_metrics->temperature_core[0], 508 &metrics.CoreTemperature[0], 509 sizeof(uint16_t) * 8); 510 gpu_metrics->temperature_l3[0] = metrics.L3Temperature; 511 */ 512 513 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 514 gpu_metrics->average_mm_activity = metrics.UvdActivity; 515 516 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 517 gpu_metrics->average_gfx_power = metrics.Power[0]; 518 gpu_metrics->average_soc_power = metrics.Power[1]; 519 /* 520 memcpy(&gpu_metrics->average_core_power[0], 521 &metrics.CorePower[0], 522 sizeof(uint16_t) * 8); 523 */ 524 525 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 526 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 527 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 528 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 529 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 530 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 531 532 /* 533 memcpy(&gpu_metrics->current_coreclk[0], 534 &metrics.CoreFrequency[0], 535 sizeof(uint16_t) * 8); 536 gpu_metrics->current_l3clk[0] = metrics.L3Frequency; 537 */ 538 539 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 540 541 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 542 543 *table = (void *)gpu_metrics; 544 545 return sizeof(struct gpu_metrics_v2_1); 546 } 547 548 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu) 549 { 550 struct smu_table_context *smu_table = &smu->smu_table; 551 552 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 553 } 554 555 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 556 long input[], uint32_t size) 557 { 558 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 559 int ret = 0; 560 561 /* Only allowed in manual mode */ 562 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 563 return -EINVAL; 564 565 switch (type) { 566 case PP_OD_EDIT_SCLK_VDDC_TABLE: 567 if (size != 2) { 568 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 569 return -EINVAL; 570 } 571 572 if (input[0] == 0) { 573 if (input[1] < smu->gfx_default_hard_min_freq) { 574 dev_warn(smu->adev->dev, 575 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 576 input[1], smu->gfx_default_hard_min_freq); 577 return -EINVAL; 578 } 579 smu->gfx_actual_hard_min_freq = input[1]; 580 } else if (input[0] == 1) { 581 if (input[1] > smu->gfx_default_soft_max_freq) { 582 dev_warn(smu->adev->dev, 583 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 584 input[1], smu->gfx_default_soft_max_freq); 585 return -EINVAL; 586 } 587 smu->gfx_actual_soft_max_freq = input[1]; 588 } else { 589 return -EINVAL; 590 } 591 break; 592 case PP_OD_RESTORE_DEFAULT_TABLE: 593 if (size != 0) { 594 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 595 return -EINVAL; 596 } else { 597 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 598 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 599 } 600 break; 601 case PP_OD_COMMIT_DPM_TABLE: 602 if (size != 0) { 603 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 604 return -EINVAL; 605 } else { 606 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 607 dev_err(smu->adev->dev, 608 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 609 smu->gfx_actual_hard_min_freq, 610 smu->gfx_actual_soft_max_freq); 611 return -EINVAL; 612 } 613 614 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 615 smu->gfx_actual_hard_min_freq, NULL); 616 if (ret) { 617 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 618 return ret; 619 } 620 621 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 622 smu->gfx_actual_soft_max_freq, NULL); 623 if (ret) { 624 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 625 return ret; 626 } 627 } 628 break; 629 default: 630 return -ENOSYS; 631 } 632 633 return ret; 634 } 635 636 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu, 637 enum smu_clk_type clk_type, 638 uint32_t *value) 639 { 640 MetricsMember_t member_type; 641 642 switch (clk_type) { 643 case SMU_SOCCLK: 644 member_type = METRICS_AVERAGE_SOCCLK; 645 break; 646 case SMU_VCLK: 647 member_type = METRICS_AVERAGE_VCLK; 648 break; 649 case SMU_DCLK: 650 member_type = METRICS_AVERAGE_DCLK; 651 break; 652 case SMU_MCLK: 653 member_type = METRICS_AVERAGE_UCLK; 654 break; 655 case SMU_FCLK: 656 return smu_cmn_send_smc_msg_with_param(smu, 657 SMU_MSG_GetFclkFrequency, 0, value); 658 default: 659 return -EINVAL; 660 } 661 662 return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value); 663 } 664 665 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu, 666 enum smu_clk_type clk_type, 667 uint32_t *count) 668 { 669 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 670 671 switch (clk_type) { 672 case SMU_SOCCLK: 673 *count = clk_table->NumSocClkLevelsEnabled; 674 break; 675 case SMU_VCLK: 676 *count = clk_table->VcnClkLevelsEnabled; 677 break; 678 case SMU_DCLK: 679 *count = clk_table->VcnClkLevelsEnabled; 680 break; 681 case SMU_MCLK: 682 *count = clk_table->NumDfPstatesEnabled; 683 break; 684 case SMU_FCLK: 685 *count = clk_table->NumDfPstatesEnabled; 686 break; 687 default: 688 break; 689 } 690 691 return 0; 692 } 693 694 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu, 695 enum smu_clk_type clk_type, 696 uint32_t dpm_level, 697 uint32_t *freq) 698 { 699 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 700 701 if (!clk_table || clk_type >= SMU_CLK_COUNT) 702 return -EINVAL; 703 704 switch (clk_type) { 705 case SMU_SOCCLK: 706 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 707 return -EINVAL; 708 *freq = clk_table->SocClocks[dpm_level]; 709 break; 710 case SMU_VCLK: 711 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 712 return -EINVAL; 713 *freq = clk_table->VClocks[dpm_level]; 714 break; 715 case SMU_DCLK: 716 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 717 return -EINVAL; 718 *freq = clk_table->DClocks[dpm_level]; 719 break; 720 case SMU_UCLK: 721 case SMU_MCLK: 722 if (dpm_level >= clk_table->NumDfPstatesEnabled) 723 return -EINVAL; 724 *freq = clk_table->DfPstateTable[dpm_level].MemClk; 725 break; 726 case SMU_FCLK: 727 if (dpm_level >= clk_table->NumDfPstatesEnabled) 728 return -EINVAL; 729 *freq = clk_table->DfPstateTable[dpm_level].FClk; 730 break; 731 default: 732 return -EINVAL; 733 } 734 735 return 0; 736 } 737 738 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu, 739 enum smu_clk_type clk_type) 740 { 741 enum smu_feature_mask feature_id = 0; 742 743 switch (clk_type) { 744 case SMU_MCLK: 745 case SMU_UCLK: 746 case SMU_FCLK: 747 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 748 break; 749 case SMU_GFXCLK: 750 case SMU_SCLK: 751 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 752 break; 753 case SMU_SOCCLK: 754 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 755 break; 756 case SMU_VCLK: 757 case SMU_DCLK: 758 feature_id = SMU_FEATURE_VCN_DPM_BIT; 759 break; 760 default: 761 return true; 762 } 763 764 return smu_cmn_feature_is_enabled(smu, feature_id); 765 } 766 767 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu, 768 enum smu_clk_type clk_type, 769 uint32_t *min, 770 uint32_t *max) 771 { 772 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 773 uint32_t clock_limit; 774 uint32_t max_dpm_level, min_dpm_level; 775 int ret = 0; 776 777 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) { 778 switch (clk_type) { 779 case SMU_MCLK: 780 case SMU_UCLK: 781 clock_limit = smu->smu_table.boot_values.uclk; 782 break; 783 case SMU_FCLK: 784 clock_limit = smu->smu_table.boot_values.fclk; 785 break; 786 case SMU_GFXCLK: 787 case SMU_SCLK: 788 clock_limit = smu->smu_table.boot_values.gfxclk; 789 break; 790 case SMU_SOCCLK: 791 clock_limit = smu->smu_table.boot_values.socclk; 792 break; 793 case SMU_VCLK: 794 clock_limit = smu->smu_table.boot_values.vclk; 795 break; 796 case SMU_DCLK: 797 clock_limit = smu->smu_table.boot_values.dclk; 798 break; 799 default: 800 clock_limit = 0; 801 break; 802 } 803 804 /* clock in Mhz unit */ 805 if (min) 806 *min = clock_limit / 100; 807 if (max) 808 *max = clock_limit / 100; 809 810 return 0; 811 } 812 813 if (max) { 814 switch (clk_type) { 815 case SMU_GFXCLK: 816 case SMU_SCLK: 817 *max = clk_table->MaxGfxClk; 818 break; 819 case SMU_MCLK: 820 case SMU_UCLK: 821 case SMU_FCLK: 822 max_dpm_level = 0; 823 break; 824 case SMU_SOCCLK: 825 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; 826 break; 827 case SMU_VCLK: 828 case SMU_DCLK: 829 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1; 830 break; 831 default: 832 ret = -EINVAL; 833 goto failed; 834 } 835 836 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 837 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max); 838 if (ret) 839 goto failed; 840 } 841 } 842 843 if (min) { 844 switch (clk_type) { 845 case SMU_GFXCLK: 846 case SMU_SCLK: 847 *min = clk_table->MinGfxClk; 848 break; 849 case SMU_MCLK: 850 case SMU_UCLK: 851 case SMU_FCLK: 852 min_dpm_level = clk_table->NumDfPstatesEnabled - 1; 853 break; 854 case SMU_SOCCLK: 855 min_dpm_level = 0; 856 break; 857 case SMU_VCLK: 858 case SMU_DCLK: 859 min_dpm_level = 0; 860 break; 861 default: 862 ret = -EINVAL; 863 goto failed; 864 } 865 866 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 867 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min); 868 if (ret) 869 goto failed; 870 } 871 } 872 873 failed: 874 return ret; 875 } 876 877 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, 878 enum smu_clk_type clk_type, 879 uint32_t min, 880 uint32_t max) 881 { 882 enum smu_message_type msg_set_min, msg_set_max; 883 int ret = 0; 884 885 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) 886 return -EINVAL; 887 888 switch (clk_type) { 889 case SMU_GFXCLK: 890 case SMU_SCLK: 891 msg_set_min = SMU_MSG_SetHardMinGfxClk; 892 msg_set_max = SMU_MSG_SetSoftMaxGfxClk; 893 break; 894 case SMU_FCLK: 895 msg_set_min = SMU_MSG_SetHardMinFclkByFreq; 896 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq; 897 break; 898 case SMU_SOCCLK: 899 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq; 900 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq; 901 break; 902 case SMU_VCLK: 903 case SMU_DCLK: 904 msg_set_min = SMU_MSG_SetHardMinVcn; 905 msg_set_max = SMU_MSG_SetSoftMaxVcn; 906 break; 907 default: 908 return -EINVAL; 909 } 910 911 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL); 912 if (ret) 913 goto out; 914 915 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL); 916 if (ret) 917 goto out; 918 919 out: 920 return ret; 921 } 922 923 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, 924 enum smu_clk_type clk_type, char *buf) 925 { 926 int i, size = 0, ret = 0; 927 uint32_t cur_value = 0, value = 0, count = 0; 928 929 smu_cmn_get_sysfs_buf(&buf, &size); 930 931 switch (clk_type) { 932 case SMU_OD_SCLK: 933 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 934 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 935 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 936 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 937 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 938 break; 939 case SMU_OD_RANGE: 940 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 941 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 942 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 943 break; 944 case SMU_SOCCLK: 945 case SMU_VCLK: 946 case SMU_DCLK: 947 case SMU_MCLK: 948 case SMU_FCLK: 949 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value); 950 if (ret) 951 goto print_clk_out; 952 953 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count); 954 if (ret) 955 goto print_clk_out; 956 957 for (i = 0; i < count; i++) { 958 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, i, &value); 959 if (ret) 960 goto print_clk_out; 961 962 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 963 cur_value == value ? "*" : ""); 964 } 965 break; 966 default: 967 break; 968 } 969 970 print_clk_out: 971 return size; 972 } 973 974 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu, 975 enum smu_clk_type clk_type, uint32_t mask) 976 { 977 uint32_t soft_min_level = 0, soft_max_level = 0; 978 uint32_t min_freq = 0, max_freq = 0; 979 int ret = 0; 980 981 soft_min_level = mask ? (ffs(mask) - 1) : 0; 982 soft_max_level = mask ? (fls(mask) - 1) : 0; 983 984 switch (clk_type) { 985 case SMU_SOCCLK: 986 case SMU_FCLK: 987 case SMU_VCLK: 988 case SMU_DCLK: 989 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 990 if (ret) 991 goto force_level_out; 992 993 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 994 if (ret) 995 goto force_level_out; 996 997 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 998 if (ret) 999 goto force_level_out; 1000 break; 1001 default: 1002 ret = -EINVAL; 1003 break; 1004 } 1005 1006 force_level_out: 1007 return ret; 1008 } 1009 1010 static int smu_v13_0_5_set_performance_level(struct smu_context *smu, 1011 enum amd_dpm_forced_level level) 1012 { 1013 struct amdgpu_device *adev = smu->adev; 1014 uint32_t sclk_min = 0, sclk_max = 0; 1015 uint32_t fclk_min = 0, fclk_max = 0; 1016 uint32_t socclk_min = 0, socclk_max = 0; 1017 int ret = 0; 1018 1019 switch (level) { 1020 case AMD_DPM_FORCED_LEVEL_HIGH: 1021 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max); 1022 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max); 1023 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max); 1024 sclk_min = sclk_max; 1025 fclk_min = fclk_max; 1026 socclk_min = socclk_max; 1027 break; 1028 case AMD_DPM_FORCED_LEVEL_LOW: 1029 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL); 1030 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL); 1031 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL); 1032 sclk_max = sclk_min; 1033 fclk_max = fclk_min; 1034 socclk_max = socclk_min; 1035 break; 1036 case AMD_DPM_FORCED_LEVEL_AUTO: 1037 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max); 1038 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max); 1039 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max); 1040 break; 1041 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1042 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1043 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1044 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1045 /* Temporarily do nothing since the optimal clocks haven't been provided yet */ 1046 break; 1047 case AMD_DPM_FORCED_LEVEL_MANUAL: 1048 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1049 return 0; 1050 default: 1051 dev_err(adev->dev, "Invalid performance level %d\n", level); 1052 return -EINVAL; 1053 } 1054 1055 if (sclk_min && sclk_max) { 1056 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, 1057 SMU_SCLK, 1058 sclk_min, 1059 sclk_max); 1060 if (ret) 1061 return ret; 1062 1063 smu->gfx_actual_hard_min_freq = sclk_min; 1064 smu->gfx_actual_soft_max_freq = sclk_max; 1065 } 1066 1067 if (fclk_min && fclk_max) { 1068 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, 1069 SMU_FCLK, 1070 fclk_min, 1071 fclk_max); 1072 if (ret) 1073 return ret; 1074 } 1075 1076 if (socclk_min && socclk_max) { 1077 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, 1078 SMU_SOCCLK, 1079 socclk_min, 1080 socclk_max); 1081 if (ret) 1082 return ret; 1083 } 1084 1085 return ret; 1086 } 1087 1088 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1089 { 1090 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1091 1092 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1093 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1094 smu->gfx_actual_hard_min_freq = 0; 1095 smu->gfx_actual_soft_max_freq = 0; 1096 1097 return 0; 1098 } 1099 1100 static const struct pptable_funcs smu_v13_0_5_ppt_funcs = { 1101 .check_fw_status = smu_v13_0_check_fw_status, 1102 .check_fw_version = smu_v13_0_check_fw_version, 1103 .init_smc_tables = smu_v13_0_5_init_smc_tables, 1104 .fini_smc_tables = smu_v13_0_5_fini_smc_tables, 1105 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1106 .system_features_control = smu_v13_0_5_system_features_control, 1107 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1108 .send_smc_msg = smu_cmn_send_smc_msg, 1109 .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable, 1110 .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable, 1111 .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables, 1112 .read_sensor = smu_v13_0_5_read_sensor, 1113 .is_dpm_running = smu_v13_0_5_is_dpm_running, 1114 .set_watermarks_table = smu_v13_0_5_set_watermarks_table, 1115 .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics, 1116 .get_enabled_mask = smu_cmn_get_enabled_mask, 1117 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1118 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1119 .gfx_off_control = smu_v13_0_gfx_off_control, 1120 .post_init = smu_v13_0_5_post_smu_init, 1121 .mode2_reset = smu_v13_0_5_mode2_reset, 1122 .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq, 1123 .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table, 1124 .print_clk_levels = smu_v13_0_5_print_clk_levels, 1125 .force_clk_levels = smu_v13_0_5_force_clk_levels, 1126 .set_performance_level = smu_v13_0_5_set_performance_level, 1127 .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters, 1128 }; 1129 1130 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu) 1131 { 1132 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs; 1133 smu->message_map = smu_v13_0_5_message_map; 1134 smu->feature_map = smu_v13_0_5_feature_mask_map; 1135 smu->table_map = smu_v13_0_5_table_map; 1136 smu->is_apu = true; 1137 } 1138