#
bbd069a8 |
| 19-May-2023 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: Reduce sdp bw after urgent to 90%
[Description] Reduce expected SDP bandwidth due to poor QoS and arbitration issues on high bandwidth configs
Cc: Mario Limonciello <mario.limoncie
drm/amd/display: Reduce sdp bw after urgent to 90%
[Description] Reduce expected SDP bandwidth due to poor QoS and arbitration issues on high bandwidth configs
Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0be5ccd5 |
| 27-May-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/display: Fix up kdoc formats in dcn32_fpu.c
Fixes the following gcc with W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2806: warning: Cannot understand * ************
drm/amd/display: Fix up kdoc formats in dcn32_fpu.c
Fixes the following gcc with W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2806: warning: Cannot understand * ************************************************************************* drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2855: warning: Cannot understand * ************************************************************************* drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2900: warning: Function parameter or member 'dc' not described in 'dcn32_assign_fpo_vactive_candidate' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2900: warning: Function parameter or member 'context' not described in 'dcn32_assign_fpo_vactive_candidate' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2900: warning: Function parameter or member 'fpo_candidate_stream' not described in 'dcn32_assign_fpo_vactive_candidate' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2929: warning: Function parameter or member 'dc' not described in 'dcn32_find_vactive_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2929: warning: Function parameter or member 'context' not described in 'dcn32_find_vactive_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2929: warning: Function parameter or member 'vactive_margin_req_us' not described in 'dcn32_find_vactive_pipe'
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20 |
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#
25879d7b |
| 16-Mar-2023 |
Qingqing Zhuo <qingqing.zhuo@amd.com> |
drm/amd/display: Clean FPGA code in dc
[Why] Drop dead code for Linux.
[How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung
drm/amd/display: Clean FPGA code in dc
[Why] Drop dead code for Linux.
[How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d205a800 |
| 12-Apr-2023 |
Leo (Hanghong) Ma <hanghong.ma@amd.com> |
drm/amd/display: Add visual confirm color support for MCLK switch
[Why && How] We would like to have visual confirm color support for MCLK switch. 1. Set visual confirm color to yellow: Vblank MCLK
drm/amd/display: Add visual confirm color support for MCLK switch
[Why && How] We would like to have visual confirm color support for MCLK switch. 1. Set visual confirm color to yellow: Vblank MCLK switch. 2. Set visual confirm color to cyan: FPO + Vblank MCLK switch. 3. Set visual confirm color to pink: Vactive MCLK switch.
Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6ba5a269 |
| 02-May-2023 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: Update vactive margin and max vblank for fpo + vactive
[Description] - Some 1920x1080@60hz displays have VBLANK time > 600us which we still want to accept for FPO + Vactive config
drm/amd/display: Update vactive margin and max vblank for fpo + vactive
[Description] - Some 1920x1080@60hz displays have VBLANK time > 600us which we still want to accept for FPO + Vactive configs based on testing - Increase max VBLANK time to 1000us to allow these configs for FPO + Vactive - Increase minimum vactive switch margin for FPO + Vactive to 200us - Based on testing, 1920x1080@120hz can have a switch margin of ~160us which requires significantly longer FPO stretch margin (5ms) which we don't want to accept for now - Also move margins into debug option
Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
807a1c14 |
| 28-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Block SubVP on displays that have pixclk > 1800Mhz
[Description] - Enabling SubVP on high refresh rate displays had a side effect of also enabling on high bandwidth displays such
drm/amd/display: Block SubVP on displays that have pixclk > 1800Mhz
[Description] - Enabling SubVP on high refresh rate displays had a side effect of also enabling on high bandwidth displays such as 8K60 - However, these are not validated and should be blocked for the time being - Block SubVP on displays that have pix rate > 1800Mhz (includes 8K60 displays)
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a00e5952 |
| 27-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Block SubVP high refresh when VRR active fixed
[Description] - SubVP high refresh is blocked when VRR is active variable, but we should also block it for when VRR is active fixed
drm/amd/display: Block SubVP high refresh when VRR active fixed
[Description] - SubVP high refresh is blocked when VRR is active variable, but we should also block it for when VRR is active fixed (video use case)
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
62cc6216 |
| 26-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Check Vactive for VRR active for FPO + Vactive
[Description] - For FPO + Vactive cases, we rely on the Vactive display to be at it's nominal refresh rate because the Vactive pipe
drm/amd/display: Check Vactive for VRR active for FPO + Vactive
[Description] - For FPO + Vactive cases, we rely on the Vactive display to be at it's nominal refresh rate because the Vactive pipe may not necessarily assert P-State allow while it's in VBLANK - For cases where the Vactive display has a stretched VBLANK due to VRR, we could underflow when trying to complete an FPO + Vactive MCLK switch because the FPO display has limited VBLANK time in waiting for the Vactive display to assert P-State allow naturally - Block FPO + Vactive if the Vactive display has VRR active (variable or fixed)
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e1a60020 |
| 19-May-2023 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: Reduce sdp bw after urgent to 90%
[Description] Reduce expected SDP bandwidth due to poor QoS and arbitration issues on high bandwidth configs
Cc: Mario Limonciello <mario.limoncie
drm/amd/display: Reduce sdp bw after urgent to 90%
[Description] Reduce expected SDP bandwidth due to poor QoS and arbitration issues on high bandwidth configs
Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15 |
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#
3caab67d |
| 28-Feb-2023 |
Jasdeep Dhillon <jasdeep.dhillon@amd.com> |
drm/amd/display: Isolate remaining FPU code in DCN32
[Why] DCN32 resource contains code that uses FPU.
[How] Moved code into DCN32 FPU
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Sign
drm/amd/display: Isolate remaining FPU code in DCN32
[Why] DCN32 resource contains code that uses FPU.
[How] Moved code into DCN32 FPU
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f38129bb |
| 21-Mar-2023 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"
This reverts commit 80c6d6804f31451848a3956a70c2bcb1f07cfcb0. The orignal commit was intended as a workaround to prevent underflow
Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"
This reverts commit 80c6d6804f31451848a3956a70c2bcb1f07cfcb0. The orignal commit was intended as a workaround to prevent underflow and flickering when using one normal monitor and the other high refresh rate monitor (> 120Hz).
This patch is being reverted in favour of a software solution to enable SubVP+DRR
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1938bcdc |
| 12-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Query GECC enable for SubVP disable
- We want to disable SubVP if Graphics Error Correction/Correcting Code (GECC) is enabled. - After reading feature caps from DMCUB during init,
drm/amd/display: Query GECC enable for SubVP disable
- We want to disable SubVP if Graphics Error Correction/Correcting Code (GECC) is enabled. - After reading feature caps from DMCUB during init, use the GECC enable/disable info to determine if SubVP can be enabled or not.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
87f0c16e |
| 17-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Enable SubVP for high refresh rate displays
[Description] - Add debug option to enable SubVP for high refresh rate displays - For now limit the enabled modes based on a table in deb
drm/amd/display: Enable SubVP for high refresh rate displays
[Description] - Add debug option to enable SubVP for high refresh rate displays - For now limit the enabled modes based on a table in debug options - Currently disabled by default
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c8cefb99 |
| 12-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: For no plane case set pstate support in validation
- Previously update_clocks was overriding pstate support if it checked that there were no planes - However, P-State support shou
drm/amd/display: For no plane case set pstate support in validation
- Previously update_clocks was overriding pstate support if it checked that there were no planes - However, P-State support should be determined in validation phase instead - This fixes an issue where a transition from FPO -> no planes expects UCLK MAX, but update_clocks was overriding to set UCLK to min
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b058e399 |
| 10-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Enable SubVP on PSR panels if single stream
Enable SubVP on PSR panels now that we have FW support
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@
drm/amd/display: Enable SubVP on PSR panels if single stream
Enable SubVP on PSR panels now that we have FW support
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ee7be8f3 |
| 10-Apr-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPO
- Due to hardware related QoS issues, we need to limit certain SKUs with less memory channels to DPM1 and above. - At DPM0 + wo
drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPO
- Due to hardware related QoS issues, we need to limit certain SKUs with less memory channels to DPM1 and above. - At DPM0 + workload running, the urgent return latency can exceed 15us (the expected maximum is 4us) which results in underflow
Cc: stable@vger.kernel.org Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2c30f855 |
| 28-Feb-2023 |
Jasdeep Dhillon <jasdeep.dhillon@amd.com> |
drm/amd/display: Isolate remaining FPU code in DCN32
[Why] DCN32 resource contains code that uses FPU.
[How] Moved code into DCN32 FPU
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Sign
drm/amd/display: Isolate remaining FPU code in DCN32
[Why] DCN32 resource contains code that uses FPU.
[How] Moved code into DCN32 FPU
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9fc6e4b3 |
| 31-Mar-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Set watermarks set D equal to A
[Description] - Since we do not use optimized watermark settings for MALL, set D = A - PMFW uses Set D for d0i3.1, so driver should make D = A for
drm/amd/display: Set watermarks set D equal to A
[Description] - Since we do not use optimized watermark settings for MALL, set D = A - PMFW uses Set D for d0i3.1, so driver should make D = A for the time being - If we choose to optimize in the future we can set watermarks D correctly
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ef3d74aa |
| 03-Apr-2023 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Add missing mclk update
When using FPO, there is some misconfiguration that happens for the lack of configuration of the MCLK switch in some circumstances. This commit adds the requ
drm/amd/display: Add missing mclk update
When using FPO, there is some misconfiguration that happens for the lack of configuration of the MCLK switch in some circumstances. This commit adds the required field update when using the MCLK switch.
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
764ba43d |
| 03-Apr-2023 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Update bouding box values for DCN32
All clock values came from firmware, but bounding box values can be helpful in some debug situations. This commit updates some of the values asso
drm/amd/display: Update bouding box values for DCN32
All clock values came from firmware, but bounding box values can be helpful in some debug situations. This commit updates some of the values associated with clock speed and memory channels.
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0289e0ed |
| 23-Mar-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Add FPO + VActive support
[Description] - When determining FPO support, include FPO + VActive support - Support FPO + VActive if one display meets regular requirements for FPO and
drm/amd/display: Add FPO + VActive support
[Description] - When determining FPO support, include FPO + VActive support - Support FPO + VActive if one display meets regular requirements for FPO and the second display is able to switch in VACTIVE with a given amount of margin
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
abaeafb1 |
| 21-Mar-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Clear FAMS flag if FAMS doesn't reduce vlevel
[Description] - If we find that applying FAMS doesn't reduce the voltage level, we will not use it - Ensure to clear the stream flags
drm/amd/display: Clear FAMS flag if FAMS doesn't reduce vlevel
[Description] - If we find that applying FAMS doesn't reduce the voltage level, we will not use it - Ensure to clear the stream flags indicating FAMS if we hit this case
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4ed79308 |
| 15-Mar-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Use per pipe P-State force for FPO
[Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This chan
drm/amd/display: Use per pipe P-State force for FPO
[Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This change is in preparation to enable FPO + VActive
* Use per pipe P-State force for FPO - For FPO, instead of using max watermarks value for P-State disallow, use per pipe p-state force instead - This is in preparation to enable FPO + VActive
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19914818 |
| 13-Mar-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Update FCLK change latency
[Descrtipion] - Driver hardcoded FCLK P-State latency was incorrect - Use the value provided by PMFW header instead
Reviewed-by: Nevenko Stupar <Nevenko.
drm/amd/display: Update FCLK change latency
[Descrtipion] - Driver hardcoded FCLK P-State latency was incorrect - Use the value provided by PMFW header instead
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ac18b610 |
| 13-Mar-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Enable FPO for configs that could reduce vlevel
[Description] - On high refresh rate DRR displays that support VBLANK naturally, UCLK could be idling at DPM1 instead of DPM0 since
drm/amd/display: Enable FPO for configs that could reduce vlevel
[Description] - On high refresh rate DRR displays that support VBLANK naturally, UCLK could be idling at DPM1 instead of DPM0 since it doesn't use FPO - To achieve DPM0, enable FPO on these configs even though it can support P-State without FPO - Default disable for now, have debug option to enable
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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