1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include "dcn32_fpu.h" 27 #include "dcn32/dcn32_resource.h" 28 #include "dcn20/dcn20_resource.h" 29 #include "display_mode_vba_util_32.h" 30 #include "dml/dcn32/display_mode_vba_32.h" 31 // We need this includes for WATERMARKS_* defines 32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h" 33 #include "dcn30/dcn30_resource.h" 34 #include "link.h" 35 36 #define DC_LOGGER_INIT(logger) 37 38 static const struct subvp_high_refresh_list subvp_high_refresh_list = { 39 .min_refresh = 120, 40 .max_refresh = 165, 41 .res = { 42 {.width = 3840, .height = 2160, }, 43 {.width = 3440, .height = 1440, }, 44 {.width = 2560, .height = 1440, }}, 45 }; 46 47 struct _vcs_dpi_ip_params_st dcn3_2_ip = { 48 .gpuvm_enable = 0, 49 .gpuvm_max_page_table_levels = 4, 50 .hostvm_enable = 0, 51 .rob_buffer_size_kbytes = 128, 52 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 53 .config_return_buffer_size_in_kbytes = 1280, 54 .compressed_buffer_segment_size_in_kbytes = 64, 55 .meta_fifo_size_in_kentries = 22, 56 .zero_size_buffer_entries = 512, 57 .compbuf_reserved_space_64b = 256, 58 .compbuf_reserved_space_zs = 64, 59 .dpp_output_buffer_pixels = 2560, 60 .opp_output_buffer_lines = 1, 61 .pixel_chunk_size_kbytes = 8, 62 .alpha_pixel_chunk_size_kbytes = 4, 63 .min_pixel_chunk_size_bytes = 1024, 64 .dcc_meta_buffer_size_bytes = 6272, 65 .meta_chunk_size_kbytes = 2, 66 .min_meta_chunk_size_bytes = 256, 67 .writeback_chunk_size_kbytes = 8, 68 .ptoi_supported = false, 69 .num_dsc = 4, 70 .maximum_dsc_bits_per_component = 12, 71 .maximum_pixels_per_line_per_dsc_unit = 6016, 72 .dsc422_native_support = true, 73 .is_line_buffer_bpp_fixed = true, 74 .line_buffer_fixed_bpp = 57, 75 .line_buffer_size_bits = 1171920, 76 .max_line_buffer_lines = 32, 77 .writeback_interface_buffer_size_kbytes = 90, 78 .max_num_dpp = 4, 79 .max_num_otg = 4, 80 .max_num_hdmi_frl_outputs = 1, 81 .max_num_wb = 1, 82 .max_dchub_pscl_bw_pix_per_clk = 4, 83 .max_pscl_lb_bw_pix_per_clk = 2, 84 .max_lb_vscl_bw_pix_per_clk = 4, 85 .max_vscl_hscl_bw_pix_per_clk = 4, 86 .max_hscl_ratio = 6, 87 .max_vscl_ratio = 6, 88 .max_hscl_taps = 8, 89 .max_vscl_taps = 8, 90 .dpte_buffer_size_in_pte_reqs_luma = 64, 91 .dpte_buffer_size_in_pte_reqs_chroma = 34, 92 .dispclk_ramp_margin_percent = 1, 93 .max_inter_dcn_tile_repeaters = 8, 94 .cursor_buffer_size = 16, 95 .cursor_chunk_size = 2, 96 .writeback_line_buffer_buffer_size = 0, 97 .writeback_min_hscl_ratio = 1, 98 .writeback_min_vscl_ratio = 1, 99 .writeback_max_hscl_ratio = 1, 100 .writeback_max_vscl_ratio = 1, 101 .writeback_max_hscl_taps = 1, 102 .writeback_max_vscl_taps = 1, 103 .dppclk_delay_subtotal = 47, 104 .dppclk_delay_scl = 50, 105 .dppclk_delay_scl_lb_only = 16, 106 .dppclk_delay_cnvc_formatter = 28, 107 .dppclk_delay_cnvc_cursor = 6, 108 .dispclk_delay_subtotal = 125, 109 .dynamic_metadata_vm_enabled = false, 110 .odm_combine_4to1_supported = false, 111 .dcc_supported = true, 112 .max_num_dp2p0_outputs = 2, 113 .max_num_dp2p0_streams = 4, 114 }; 115 116 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { 117 .clock_limits = { 118 { 119 .state = 0, 120 .dcfclk_mhz = 1564.0, 121 .fabricclk_mhz = 2500.0, 122 .dispclk_mhz = 2150.0, 123 .dppclk_mhz = 2150.0, 124 .phyclk_mhz = 810.0, 125 .phyclk_d18_mhz = 667.0, 126 .phyclk_d32_mhz = 625.0, 127 .socclk_mhz = 1200.0, 128 .dscclk_mhz = 716.667, 129 .dram_speed_mts = 18000.0, 130 .dtbclk_mhz = 1564.0, 131 }, 132 }, 133 .num_states = 1, 134 .sr_exit_time_us = 42.97, 135 .sr_enter_plus_exit_time_us = 49.94, 136 .sr_exit_z8_time_us = 285.0, 137 .sr_enter_plus_exit_z8_time_us = 320, 138 .writeback_latency_us = 12.0, 139 .round_trip_ping_latency_dcfclk_cycles = 263, 140 .urgent_latency_pixel_data_only_us = 4.0, 141 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 142 .urgent_latency_vm_data_only_us = 4.0, 143 .fclk_change_latency_us = 25, 144 .usr_retraining_latency_us = 2, 145 .smn_latency_us = 2, 146 .mall_allocated_for_dcn_mbytes = 64, 147 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 148 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 149 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 150 .pct_ideal_sdp_bw_after_urgent = 100.0, 151 .pct_ideal_fabric_bw_after_urgent = 67.0, 152 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 153 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 154 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 155 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 156 .max_avg_sdp_bw_use_normal_percent = 80.0, 157 .max_avg_fabric_bw_use_normal_percent = 60.0, 158 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 159 .max_avg_dram_bw_use_normal_percent = 15.0, 160 .num_chans = 24, 161 .dram_channel_width_bytes = 2, 162 .fabric_datapath_to_dcn_data_return_bytes = 64, 163 .return_bus_width_bytes = 64, 164 .downspread_percent = 0.38, 165 .dcn_downspread_percent = 0.5, 166 .dram_clock_change_latency_us = 400, 167 .dispclk_dppclk_vco_speed_mhz = 4300.0, 168 .do_urgent_latency_adjustment = true, 169 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 170 .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000, 171 }; 172 173 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) 174 { 175 /* defaults */ 176 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; 177 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; 178 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; 179 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; 180 /* For min clocks use as reported by PM FW and report those as min */ 181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; 182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 183 uint16_t setb_min_uclk_mhz = min_uclk_mhz; 184 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; 185 186 dc_assert_fp_enabled(); 187 188 /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ 189 if (dcfclk_mhz_for_the_second_state) 190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; 191 else 192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 193 194 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) 195 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; 196 197 /* Set A - Normal - default values */ 198 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; 199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 200 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us; 201 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; 202 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 203 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 204 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 205 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; 206 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; 207 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; 208 209 /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */ 210 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; 211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; 212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us; 213 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; 214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 215 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 216 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; 217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz; 218 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; 219 220 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ 221 /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */ 222 if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { 223 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; 224 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50; 225 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us; 226 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; 227 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 228 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; 229 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 230 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; 231 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; 232 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; 233 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; 234 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; 235 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; 236 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; 237 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; 238 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; 239 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; 240 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; 241 } 242 /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */ 243 /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */ 244 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; 245 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; 246 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us; 247 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD 248 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD 249 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; 250 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 251 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; 252 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; 253 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; 254 } 255 256 /* 257 * Finds dummy_latency_index when MCLK switching using firmware based 258 * vblank stretch is enabled. This function will iterate through the 259 * table of dummy pstate latencies until the lowest value that allows 260 * dm_allow_self_refresh_and_mclk_switch to happen is found 261 */ 262 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, 263 struct dc_state *context, 264 display_e2e_pipe_params_st *pipes, 265 int pipe_cnt, 266 int vlevel) 267 { 268 const int max_latency_table_entries = 4; 269 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 270 int dummy_latency_index = 0; 271 enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 272 273 dc_assert_fp_enabled(); 274 275 while (dummy_latency_index < max_latency_table_entries) { 276 if (temp_clock_change_support != dm_dram_clock_change_unsupported) 277 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; 278 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 279 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 280 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 281 282 /* for subvp + DRR case, if subvp pipes are still present we support pstate */ 283 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && 284 dcn32_subvp_in_use(dc, context)) 285 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; 286 287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && 288 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) 289 break; 290 291 dummy_latency_index++; 292 } 293 294 if (dummy_latency_index == max_latency_table_entries) { 295 ASSERT(dummy_latency_index != max_latency_table_entries); 296 /* If the execution gets here, it means dummy p_states are 297 * not possible. This should never happen and would mean 298 * something is severely wrong. 299 * Here we reset dummy_latency_index to 3, because it is 300 * better to have underflows than system crashes. 301 */ 302 dummy_latency_index = max_latency_table_entries - 1; 303 } 304 305 return dummy_latency_index; 306 } 307 308 /** 309 * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes 310 * and populate pipe_ctx with those params. 311 * @dc: [in] current dc state 312 * @context: [in] new dc state 313 * @pipes: [in] DML pipe params array 314 * @pipe_cnt: [in] DML pipe count 315 * 316 * This function must be called AFTER the phantom pipes are added to context 317 * and run through DML (so that the DLG params for the phantom pipes can be 318 * populated), and BEFORE we program the timing for the phantom pipes. 319 */ 320 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 321 struct dc_state *context, 322 display_e2e_pipe_params_st *pipes, 323 int pipe_cnt) 324 { 325 uint32_t i, pipe_idx; 326 327 dc_assert_fp_enabled(); 328 329 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 330 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 331 332 if (!pipe->stream) 333 continue; 334 335 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 336 pipes[pipe_idx].pipe.dest.vstartup_start = 337 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 338 pipes[pipe_idx].pipe.dest.vupdate_offset = 339 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 340 pipes[pipe_idx].pipe.dest.vupdate_width = 341 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 342 pipes[pipe_idx].pipe.dest.vready_offset = 343 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 344 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; 345 } 346 pipe_idx++; 347 } 348 } 349 350 /** 351 * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe 352 * @context: [in] New DC state to be programmed 353 * @pipe_e2e: [in] DML pipe end to end context 354 * 355 * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both 356 * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is 357 * determined by DPPClk requirements 358 * 359 * This function follows the same policy as DML: 360 * - Check for ODM combine requirements / policy first 361 * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and 362 * MPC is required 363 * 364 * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits). 365 */ 366 uint8_t dcn32_predict_pipe_split(struct dc_state *context, 367 display_e2e_pipe_params_st *pipe_e2e) 368 { 369 double pscl_throughput; 370 double pscl_throughput_chroma; 371 double dpp_clk_single_dpp, clock; 372 double clk_frequency = 0.0; 373 double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz; 374 bool total_available_pipes_support = false; 375 uint32_t number_of_dpp = 0; 376 enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled; 377 double req_dispclk_per_surface = 0; 378 uint8_t num_splits = 0; 379 380 dc_assert_fp_enabled(); 381 382 dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit, 383 pipe_e2e->pipe.dest.hactive, 384 pipe_e2e->dout.output_format, 385 pipe_e2e->dout.output_type, 386 pipe_e2e->pipe.dest.odm_combine_policy, 387 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 388 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 389 pipe_e2e->dout.dsc_enable != 0, 390 0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */ 391 context->bw_ctx.dml.ip.max_num_dpp, 392 pipe_e2e->pipe.dest.pixel_rate_mhz, 393 context->bw_ctx.dml.soc.dcn_downspread_percent, 394 context->bw_ctx.dml.ip.dispclk_ramp_margin_percent, 395 context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz, 396 pipe_e2e->dout.dsc_slices, 397 /* Output */ 398 &total_available_pipes_support, 399 &number_of_dpp, 400 &odm_mode, 401 &req_dispclk_per_surface); 402 403 dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio, 404 pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c, 405 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio, 406 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c, 407 context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk, 408 context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk, 409 pipe_e2e->pipe.dest.pixel_rate_mhz, 410 pipe_e2e->pipe.src.source_format, 411 pipe_e2e->pipe.scale_taps.htaps, 412 pipe_e2e->pipe.scale_taps.htaps_c, 413 pipe_e2e->pipe.scale_taps.vtaps, 414 pipe_e2e->pipe.scale_taps.vtaps_c, 415 /* Output */ 416 &pscl_throughput, &pscl_throughput_chroma, 417 &dpp_clk_single_dpp); 418 419 clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100); 420 421 if (clock > 0) 422 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock); 423 424 if (odm_mode == dm_odm_combine_mode_2to1) 425 num_splits = 1; 426 else if (odm_mode == dm_odm_combine_mode_4to1) 427 num_splits = 3; 428 else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz) 429 num_splits = 1; 430 431 return num_splits; 432 } 433 434 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 435 { 436 float memory_bw_kbytes_sec; 437 float fabric_bw_kbytes_sec; 438 float sdp_bw_kbytes_sec; 439 float limiting_bw_kbytes_sec; 440 441 memory_bw_kbytes_sec = entry->dram_speed_mts * 442 dcn3_2_soc.num_chans * 443 dcn3_2_soc.dram_channel_width_bytes * 444 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 445 446 fabric_bw_kbytes_sec = entry->fabricclk_mhz * 447 dcn3_2_soc.return_bus_width_bytes * 448 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 449 450 sdp_bw_kbytes_sec = entry->dcfclk_mhz * 451 dcn3_2_soc.return_bus_width_bytes * 452 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 453 454 limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 455 456 if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 457 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 458 459 if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 460 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 461 462 return limiting_bw_kbytes_sec; 463 } 464 465 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 466 { 467 if (entry->dcfclk_mhz > 0) { 468 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 469 470 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 471 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * 472 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 473 } else if (entry->fabricclk_mhz > 0) { 474 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 475 476 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 477 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * 478 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 479 } else if (entry->dram_speed_mts > 0) { 480 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * 481 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 482 483 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 484 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 485 } 486 } 487 488 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, 489 unsigned int *num_entries, 490 struct _vcs_dpi_voltage_scaling_st *entry) 491 { 492 int i = 0; 493 int index = 0; 494 float net_bw_of_new_state = 0; 495 496 dc_assert_fp_enabled(); 497 498 get_optimal_ntuple(entry); 499 500 if (*num_entries == 0) { 501 table[0] = *entry; 502 (*num_entries)++; 503 } else { 504 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry); 505 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) { 506 index++; 507 if (index >= *num_entries) 508 break; 509 } 510 511 for (i = *num_entries; i > index; i--) 512 table[i] = table[i - 1]; 513 514 table[index] = *entry; 515 (*num_entries)++; 516 } 517 } 518 519 /** 520 * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream 521 * @dc: current dc state 522 * @context: new dc state 523 * @ref_pipe: Main pipe for the phantom stream 524 * @phantom_stream: target phantom stream state 525 * @pipes: DML pipe params 526 * @pipe_cnt: number of DML pipes 527 * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe) 528 * 529 * Set timing params of the phantom stream based on calculated output from DML. 530 * This function first gets the DML pipe index using the DC pipe index, then 531 * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of 532 * lines required for SubVP MCLK switching and assigns to the phantom stream 533 * accordingly. 534 * 535 * - The number of SubVP lines calculated in DML does not take into account 536 * FW processing delays and required pstate allow width, so we must include 537 * that separately. 538 * 539 * - Set phantom backporch = vstartup of main pipe 540 */ 541 void dcn32_set_phantom_stream_timing(struct dc *dc, 542 struct dc_state *context, 543 struct pipe_ctx *ref_pipe, 544 struct dc_stream_state *phantom_stream, 545 display_e2e_pipe_params_st *pipes, 546 unsigned int pipe_cnt, 547 unsigned int dc_pipe_idx) 548 { 549 unsigned int i, pipe_idx; 550 struct pipe_ctx *pipe; 551 uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; 552 unsigned int num_dpp; 553 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; 554 unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 555 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; 556 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 557 struct dc_stream_state *main_stream = ref_pipe->stream; 558 559 dc_assert_fp_enabled(); 560 561 // Find DML pipe index (pipe_idx) using dc_pipe_idx 562 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 563 pipe = &context->res_ctx.pipe_ctx[i]; 564 565 if (!pipe->stream) 566 continue; 567 568 if (i == dc_pipe_idx) 569 break; 570 571 pipe_idx++; 572 } 573 574 // Calculate lines required for pstate allow width and FW processing delays 575 pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + 576 dc->caps.subvp_pstate_allow_width_us) / 1000000) * 577 (ref_pipe->stream->timing.pix_clk_100hz * 100) / 578 (double)ref_pipe->stream->timing.h_total; 579 580 // Update clks_cfg for calling into recalculate 581 pipes[0].clks_cfg.voltage = vlevel; 582 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 583 pipes[0].clks_cfg.socclk_mhz = socclk; 584 585 // DML calculation for MALL region doesn't take into account FW delay 586 // and required pstate allow width for multi-display cases 587 /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned 588 * to 2 swaths (i.e. 16 lines) 589 */ 590 phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + 591 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines; 592 593 // W/A for DCC corruption with certain high resolution timings. 594 // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive. 595 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; 596 phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0; 597 598 /* dc->debug.subvp_extra_lines 0 by default*/ 599 phantom_vactive += dc->debug.subvp_extra_lines; 600 601 // For backporch of phantom pipe, use vstartup of the main pipe 602 phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 603 604 phantom_stream->dst.y = 0; 605 phantom_stream->dst.height = phantom_vactive; 606 /* When scaling, DML provides the end to end required number of lines for MALL. 607 * dst.height is always correct for this case, but src.height is not which causes a 608 * delta between main and phantom pipe scaling outputs. Need to adjust src.height on 609 * phantom for this case. 610 */ 611 phantom_stream->src.y = 0; 612 phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height; 613 614 phantom_stream->timing.v_addressable = phantom_vactive; 615 phantom_stream->timing.v_front_porch = 1; 616 phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + 617 phantom_stream->timing.v_front_porch + 618 phantom_stream->timing.v_sync_width + 619 phantom_bp; 620 phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing 621 } 622 623 /** 624 * dcn32_get_num_free_pipes - Calculate number of free pipes 625 * @dc: current dc state 626 * @context: new dc state 627 * 628 * This function assumes that a "used" pipe is a pipe that has 629 * both a stream and a plane assigned to it. 630 * 631 * Return: Number of free pipes available in the context 632 */ 633 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) 634 { 635 unsigned int i; 636 unsigned int free_pipes = 0; 637 unsigned int num_pipes = 0; 638 639 for (i = 0; i < dc->res_pool->pipe_count; i++) { 640 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 641 642 if (pipe->stream && !pipe->top_pipe) { 643 while (pipe) { 644 num_pipes++; 645 pipe = pipe->bottom_pipe; 646 } 647 } 648 } 649 650 free_pipes = dc->res_pool->pipe_count - num_pipes; 651 return free_pipes; 652 } 653 654 /** 655 * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP. 656 * @dc: current dc state 657 * @context: new dc state 658 * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned 659 * 660 * We enter this function if we are Sub-VP capable (i.e. enough pipes available) 661 * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if 662 * we are forcing SubVP P-State switching on the current config. 663 * 664 * The number of pipes used for the chosen surface must be less than or equal to the 665 * number of free pipes available. 666 * 667 * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK). 668 * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own 669 * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't 670 * support MCLK switching naturally [i.e. ACTIVE or VBLANK]). 671 * 672 * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false. 673 */ 674 static bool dcn32_assign_subvp_pipe(struct dc *dc, 675 struct dc_state *context, 676 unsigned int *index) 677 { 678 unsigned int i, pipe_idx; 679 unsigned int max_frame_time = 0; 680 bool valid_assignment_found = false; 681 unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context); 682 bool current_assignment_freesync = false; 683 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 684 685 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 686 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 687 unsigned int num_pipes = 0; 688 unsigned int refresh_rate = 0; 689 690 if (!pipe->stream) 691 continue; 692 693 // Round up 694 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 695 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 696 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 697 /* SubVP pipe candidate requirements: 698 * - Refresh rate < 120hz 699 * - Not able to switch in vactive naturally (switching in active means the 700 * DET provides enough buffer to hide the P-State switch latency -- trying 701 * to combine this with SubVP can cause issues with the scheduling). 702 * - Not TMZ surface 703 */ 704 if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) && 705 !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) && 706 (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) && 707 pipe->stream->mall_stream_config.type == SUBVP_NONE && 708 (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) && 709 !pipe->plane_state->address.tmz_surface && 710 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 || 711 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && 712 dcn32_allow_subvp_with_active_margin(pipe)))) { 713 while (pipe) { 714 num_pipes++; 715 pipe = pipe->bottom_pipe; 716 } 717 718 pipe = &context->res_ctx.pipe_ctx[i]; 719 if (num_pipes <= free_pipes) { 720 struct dc_stream_state *stream = pipe->stream; 721 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / 722 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; 723 if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) { 724 *index = i; 725 max_frame_time = frame_us; 726 valid_assignment_found = true; 727 current_assignment_freesync = false; 728 /* For the 2-Freesync display case, still choose the one with the 729 * longest frame time 730 */ 731 } else if (stream->ignore_msa_timing_param && (!valid_assignment_found || 732 (current_assignment_freesync && frame_us > max_frame_time))) { 733 *index = i; 734 valid_assignment_found = true; 735 current_assignment_freesync = true; 736 } 737 } 738 } 739 pipe_idx++; 740 } 741 return valid_assignment_found; 742 } 743 744 /** 745 * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP. 746 * @dc: current dc state 747 * @context: new dc state 748 * 749 * This function returns true if there are enough free pipes 750 * to create the required phantom pipes for any given stream 751 * (that does not already have phantom pipe assigned). 752 * 753 * e.g. For a 2 stream config where the first stream uses one 754 * pipe and the second stream uses 2 pipes (i.e. pipe split), 755 * this function will return true because there is 1 remaining 756 * pipe which can be used as the phantom pipe for the non pipe 757 * split pipe. 758 * 759 * Return: 760 * True if there are enough free pipes to assign phantom pipes to at least one 761 * stream that does not already have phantom pipes assigned. Otherwise false. 762 */ 763 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) 764 { 765 unsigned int i, split_cnt, free_pipes; 766 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 767 bool subvp_possible = false; 768 769 for (i = 0; i < dc->res_pool->pipe_count; i++) { 770 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 771 772 // Find the minimum pipe split count for non SubVP pipes 773 if (pipe->stream && !pipe->top_pipe && 774 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 775 split_cnt = 0; 776 while (pipe) { 777 split_cnt++; 778 pipe = pipe->bottom_pipe; 779 } 780 781 if (split_cnt < min_pipe_split) 782 min_pipe_split = split_cnt; 783 } 784 } 785 786 free_pipes = dcn32_get_num_free_pipes(dc, context); 787 788 // SubVP only possible if at least one pipe is being used (i.e. free_pipes 789 // should not equal to the pipe_count) 790 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) 791 subvp_possible = true; 792 793 return subvp_possible; 794 } 795 796 /** 797 * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable 798 * @dc: current dc state 799 * @context: new dc state 800 * 801 * High level algorithm: 802 * 1. Find longest microschedule length (in us) between the two SubVP pipes 803 * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both 804 * pipes still allows for the maximum microschedule to fit in the active 805 * region for both pipes. 806 * 807 * Return: True if the SubVP + SubVP config is schedulable, false otherwise 808 */ 809 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) 810 { 811 struct pipe_ctx *subvp_pipes[2]; 812 struct dc_stream_state *phantom = NULL; 813 uint32_t microschedule_lines = 0; 814 uint32_t index = 0; 815 uint32_t i; 816 uint32_t max_microschedule_us = 0; 817 int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us; 818 819 for (i = 0; i < dc->res_pool->pipe_count; i++) { 820 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 821 uint32_t time_us = 0; 822 823 /* Loop to calculate the maximum microschedule time between the two SubVP pipes, 824 * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. 825 */ 826 if (pipe->stream && pipe->plane_state && !pipe->top_pipe && 827 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 828 phantom = pipe->stream->mall_stream_config.paired_stream; 829 microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + 830 phantom->timing.v_addressable; 831 832 // Round up when calculating microschedule time (+ 1 at the end) 833 time_us = (microschedule_lines * phantom->timing.h_total) / 834 (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + 835 dc->caps.subvp_prefetch_end_to_mall_start_us + 836 dc->caps.subvp_fw_processing_delay_us + 1; 837 if (time_us > max_microschedule_us) 838 max_microschedule_us = time_us; 839 840 subvp_pipes[index] = pipe; 841 index++; 842 843 // Maximum 2 SubVP pipes 844 if (index == 2) 845 break; 846 } 847 } 848 vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / 849 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 850 vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / 851 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 852 vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * 853 subvp_pipes[0]->stream->timing.h_total) / 854 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 855 vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * 856 subvp_pipes[1]->stream->timing.h_total) / 857 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 858 859 if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && 860 (vactive2_us - vblank1_us) / 2 > max_microschedule_us) 861 return true; 862 863 return false; 864 } 865 866 /** 867 * subvp_drr_schedulable - Determine if SubVP + DRR config is schedulable 868 * @dc: current dc state 869 * @context: new dc state 870 * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config 871 * 872 * High level algorithm: 873 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 874 * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching 875 * (the margin is equal to the MALL region + DRR margin (500us)) 876 * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame)) 877 * then report the configuration as supported 878 * 879 * Return: True if the SubVP + DRR config is schedulable, false otherwise 880 */ 881 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe) 882 { 883 bool schedulable = false; 884 uint32_t i; 885 struct pipe_ctx *pipe = NULL; 886 struct dc_crtc_timing *main_timing = NULL; 887 struct dc_crtc_timing *phantom_timing = NULL; 888 struct dc_crtc_timing *drr_timing = NULL; 889 int16_t prefetch_us = 0; 890 int16_t mall_region_us = 0; 891 int16_t drr_frame_us = 0; // nominal frame time 892 int16_t subvp_active_us = 0; 893 int16_t stretched_drr_us = 0; 894 int16_t drr_stretched_vblank_us = 0; 895 int16_t max_vblank_mallregion = 0; 896 897 // Find SubVP pipe 898 for (i = 0; i < dc->res_pool->pipe_count; i++) { 899 pipe = &context->res_ctx.pipe_ctx[i]; 900 901 // We check for master pipe, but it shouldn't matter since we only need 902 // the pipe for timing info (stream should be same for any pipe splits) 903 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 904 continue; 905 906 // Find the SubVP pipe 907 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 908 break; 909 } 910 911 main_timing = &pipe->stream->timing; 912 phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing; 913 drr_timing = &drr_pipe->stream->timing; 914 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 915 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 916 dc->caps.subvp_prefetch_end_to_mall_start_us; 917 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 918 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 919 drr_frame_us = drr_timing->v_total * drr_timing->h_total / 920 (double)(drr_timing->pix_clk_100hz * 100) * 1000000; 921 // P-State allow width and FW delays already included phantom_timing->v_addressable 922 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 923 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 924 stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 925 drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / 926 (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); 927 max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; 928 929 /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the 930 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis 931 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 932 * and the max of (VBLANK blanking time, MALL region)). 933 */ 934 if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && 935 subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0) 936 schedulable = true; 937 938 return schedulable; 939 } 940 941 942 /** 943 * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable 944 * @dc: current dc state 945 * @context: new dc state 946 * 947 * High level algorithm: 948 * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe 949 * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time)) 950 * then report the configuration as supported 951 * 3. If the VBLANK display is DRR, then take the DRR static schedulability path 952 * 953 * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise 954 */ 955 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) 956 { 957 struct pipe_ctx *pipe = NULL; 958 struct pipe_ctx *subvp_pipe = NULL; 959 bool found = false; 960 bool schedulable = false; 961 uint32_t i = 0; 962 uint8_t vblank_index = 0; 963 uint16_t prefetch_us = 0; 964 uint16_t mall_region_us = 0; 965 uint16_t vblank_frame_us = 0; 966 uint16_t subvp_active_us = 0; 967 uint16_t vblank_blank_us = 0; 968 uint16_t max_vblank_mallregion = 0; 969 struct dc_crtc_timing *main_timing = NULL; 970 struct dc_crtc_timing *phantom_timing = NULL; 971 struct dc_crtc_timing *vblank_timing = NULL; 972 973 /* For SubVP + VBLANK/DRR cases, we assume there can only be 974 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK 975 * is supported, it is either a single VBLANK case or two VBLANK 976 * displays which are synchronized (in which case they have identical 977 * timings). 978 */ 979 for (i = 0; i < dc->res_pool->pipe_count; i++) { 980 pipe = &context->res_ctx.pipe_ctx[i]; 981 982 // We check for master pipe, but it shouldn't matter since we only need 983 // the pipe for timing info (stream should be same for any pipe splits) 984 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 985 continue; 986 987 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) { 988 // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe). 989 vblank_index = i; 990 found = true; 991 } 992 993 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 994 subvp_pipe = pipe; 995 } 996 // Use ignore_msa_timing_param and VRR active, or Freesync flag to identify as DRR On 997 if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param && 998 (context->res_ctx.pipe_ctx[vblank_index].stream->allow_freesync || 999 context->res_ctx.pipe_ctx[vblank_index].stream->vrr_active_variable)) { 1000 // SUBVP + DRR case -- only allowed if run through DRR validation path 1001 schedulable = false; 1002 } else if (found) { 1003 main_timing = &subvp_pipe->stream->timing; 1004 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 1005 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; 1006 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe 1007 // Also include the prefetch end to mallstart delay time 1008 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 1009 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 1010 dc->caps.subvp_prefetch_end_to_mall_start_us; 1011 // P-State allow width and FW delays already included phantom_timing->v_addressable 1012 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 1013 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 1014 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / 1015 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 1016 vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / 1017 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 1018 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 1019 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 1020 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; 1021 1022 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 1023 // and the max of (VBLANK blanking time, MALL region) 1024 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) 1025 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) 1026 schedulable = true; 1027 } 1028 return schedulable; 1029 } 1030 1031 /** 1032 * subvp_validate_static_schedulability - Check which SubVP case is calculated 1033 * and handle static analysis based on the case. 1034 * @dc: current dc state 1035 * @context: new dc state 1036 * @vlevel: Voltage level calculated by DML 1037 * 1038 * Three cases: 1039 * 1. SubVP + SubVP 1040 * 2. SubVP + VBLANK (DRR checked internally) 1041 * 3. SubVP + VACTIVE (currently unsupported) 1042 * 1043 * Return: True if statically schedulable, false otherwise 1044 */ 1045 static bool subvp_validate_static_schedulability(struct dc *dc, 1046 struct dc_state *context, 1047 int vlevel) 1048 { 1049 bool schedulable = true; // true by default for single display case 1050 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1051 uint32_t i, pipe_idx; 1052 uint8_t subvp_count = 0; 1053 uint8_t vactive_count = 0; 1054 1055 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1056 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1057 1058 if (!pipe->stream) 1059 continue; 1060 1061 if (pipe->plane_state && !pipe->top_pipe && 1062 pipe->stream->mall_stream_config.type == SUBVP_MAIN) 1063 subvp_count++; 1064 1065 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE 1066 // switching (SubVP + VACTIVE unsupported). In situations where we force 1067 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count. 1068 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && 1069 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1070 vactive_count++; 1071 } 1072 pipe_idx++; 1073 } 1074 1075 if (subvp_count == 2) { 1076 // Static schedulability check for SubVP + SubVP case 1077 schedulable = subvp_subvp_schedulable(dc, context); 1078 } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) { 1079 // Static schedulability check for SubVP + VBLANK case. Also handle the case where 1080 // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK) 1081 if (vactive_count > 0) 1082 schedulable = false; 1083 else 1084 schedulable = subvp_vblank_schedulable(dc, context); 1085 } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp && 1086 vactive_count > 0) { 1087 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default. 1088 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count. 1089 // SubVP + VACTIVE currently unsupported 1090 schedulable = false; 1091 } 1092 return schedulable; 1093 } 1094 1095 static void dcn32_full_validate_bw_helper(struct dc *dc, 1096 struct dc_state *context, 1097 display_e2e_pipe_params_st *pipes, 1098 int *vlevel, 1099 int *split, 1100 bool *merge, 1101 int *pipe_cnt) 1102 { 1103 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1104 unsigned int dc_pipe_idx = 0; 1105 int i = 0; 1106 bool found_supported_config = false; 1107 struct pipe_ctx *pipe = NULL; 1108 uint32_t non_subvp_pipes = 0; 1109 bool drr_pipe_found = false; 1110 uint32_t drr_pipe_index = 0; 1111 1112 dc_assert_fp_enabled(); 1113 1114 /* 1115 * DML favors voltage over p-state, but we're more interested in 1116 * supporting p-state over voltage. We can't support p-state in 1117 * prefetch mode > 0 so try capping the prefetch mode to start. 1118 * Override present for testing. 1119 */ 1120 if (dc->debug.dml_disallow_alternate_prefetch_modes) 1121 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1122 dm_prefetch_support_uclk_fclk_and_stutter; 1123 else 1124 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1125 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1126 1127 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1128 /* This may adjust vlevel and maxMpcComb */ 1129 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1130 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1131 vba->VoltageLevel = *vlevel; 1132 } 1133 1134 /* Conditions for setting up phantom pipes for SubVP: 1135 * 1. Not force disable SubVP 1136 * 2. Full update (i.e. !fast_validate) 1137 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?) 1138 * 4. Display configuration passes validation 1139 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch) 1140 */ 1141 if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) && 1142 !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && 1143 (*vlevel == context->bw_ctx.dml.soc.num_states || 1144 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || 1145 dc->debug.force_subvp_mclk_switch)) { 1146 1147 dcn32_merge_pipes_for_subvp(dc, context); 1148 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1149 1150 /* to re-initialize viewport after the pipe merge */ 1151 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1152 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1153 1154 if (!pipe_ctx->plane_state || !pipe_ctx->stream) 1155 continue; 1156 1157 resource_build_scaling_params(pipe_ctx); 1158 } 1159 1160 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) && 1161 dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) { 1162 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. 1163 * Adding phantom pipes won't change the validation result, so change the DML input param 1164 * for P-State support before adding phantom pipes and recalculating the DML result. 1165 * However, this case is only applicable for SubVP + DRR cases because the prefetch mode 1166 * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched 1167 * enough to support MCLK switching. 1168 */ 1169 if (*vlevel == context->bw_ctx.dml.soc.num_states && 1170 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final == 1171 dm_prefetch_support_uclk_fclk_and_stutter) { 1172 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1173 dm_prefetch_support_fclk_and_stutter; 1174 /* There are params (such as FabricClock) that need to be recalculated 1175 * after validation fails (otherwise it will be 0). Calculation for 1176 * phantom vactive requires call into DML, so we must ensure all the 1177 * vba params are valid otherwise we'll get incorrect phantom vactive. 1178 */ 1179 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1180 } 1181 1182 dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx); 1183 1184 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1185 // Populate dppclk to trigger a recalculate in dml_get_voltage_level 1186 // so the phantom pipe DLG params can be assigned correctly. 1187 pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); 1188 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1189 1190 /* Check that vlevel requested supports pstate or not 1191 * if not, select the lowest vlevel that supports it 1192 */ 1193 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { 1194 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) { 1195 *vlevel = i; 1196 break; 1197 } 1198 } 1199 1200 if (*vlevel < context->bw_ctx.dml.soc.num_states && 1201 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported 1202 && subvp_validate_static_schedulability(dc, context, *vlevel)) { 1203 found_supported_config = true; 1204 } else if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1205 /* Case where 1 SubVP is added, and DML reports MCLK unsupported or DRR is allowed. 1206 * This handles the case for SubVP + DRR, where the DRR display does not support MCLK 1207 * switch at it's native refresh rate / timing, or DRR is allowed for the non-subvp 1208 * display. 1209 */ 1210 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1211 pipe = &context->res_ctx.pipe_ctx[i]; 1212 if (pipe->stream && pipe->plane_state && !pipe->top_pipe && 1213 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1214 non_subvp_pipes++; 1215 // Use ignore_msa_timing_param flag to identify as DRR 1216 if (pipe->stream->ignore_msa_timing_param && pipe->stream->allow_freesync) { 1217 drr_pipe_found = true; 1218 drr_pipe_index = i; 1219 } 1220 } 1221 } 1222 // If there is only 1 remaining non SubVP pipe that is DRR, check static 1223 // schedulability for SubVP + DRR. 1224 if (non_subvp_pipes == 1 && drr_pipe_found) { 1225 /* find lowest vlevel that supports the config */ 1226 for (i = *vlevel; i >= 0; i--) { 1227 if (vba->ModeSupport[i][vba->maxMpcComb]) { 1228 *vlevel = i; 1229 } else { 1230 break; 1231 } 1232 } 1233 1234 found_supported_config = subvp_drr_schedulable(dc, context, 1235 &context->res_ctx.pipe_ctx[drr_pipe_index]); 1236 } 1237 } 1238 } 1239 1240 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching) 1241 // remove phantom pipes and repopulate dml pipes 1242 if (!found_supported_config) { 1243 dc->res_pool->funcs->remove_phantom_pipes(dc, context, false); 1244 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported; 1245 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1246 1247 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1248 /* This may adjust vlevel and maxMpcComb */ 1249 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1250 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1251 vba->VoltageLevel = *vlevel; 1252 } 1253 } else { 1254 // Most populate phantom DLG params before programming hardware / timing for phantom pipe 1255 dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt); 1256 1257 /* Call validate_apply_pipe_split flags after calling DML getters for 1258 * phantom dlg params, or some of the VBA params indicating pipe split 1259 * can be overwritten by the getters. 1260 * 1261 * When setting up SubVP config, all pipes are merged before attempting to 1262 * add phantom pipes. If pipe split (ODM / MPC) is required, both the main 1263 * and phantom pipes will be split in the regular pipe splitting sequence. 1264 */ 1265 memset(split, 0, MAX_PIPES * sizeof(int)); 1266 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1267 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1268 vba->VoltageLevel = *vlevel; 1269 // Note: We can't apply the phantom pipes to hardware at this time. We have to wait 1270 // until driver has acquired the DMCUB lock to do it safely. 1271 } 1272 } 1273 } 1274 1275 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 1276 { 1277 int i; 1278 1279 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1280 if (!context->res_ctx.pipe_ctx[i].stream) 1281 continue; 1282 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) 1283 return true; 1284 } 1285 return false; 1286 } 1287 1288 static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start) 1289 { 1290 struct dc_crtc_timing patched_crtc_timing; 1291 uint32_t asic_blank_end = 0; 1292 uint32_t asic_blank_start = 0; 1293 uint32_t newVstartup = 0; 1294 1295 patched_crtc_timing = *dc_crtc_timing; 1296 1297 if (patched_crtc_timing.flags.INTERLACE == 1) { 1298 if (patched_crtc_timing.v_front_porch < 2) 1299 patched_crtc_timing.v_front_porch = 2; 1300 } else { 1301 if (patched_crtc_timing.v_front_porch < 1) 1302 patched_crtc_timing.v_front_porch = 1; 1303 } 1304 1305 /* blank_start = frame end - front porch */ 1306 asic_blank_start = patched_crtc_timing.v_total - 1307 patched_crtc_timing.v_front_porch; 1308 1309 /* blank_end = blank_start - active */ 1310 asic_blank_end = asic_blank_start - 1311 patched_crtc_timing.v_border_bottom - 1312 patched_crtc_timing.v_addressable - 1313 patched_crtc_timing.v_border_top; 1314 1315 newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start); 1316 1317 *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start); 1318 } 1319 1320 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, 1321 display_e2e_pipe_params_st *pipes, 1322 int pipe_cnt, int vlevel) 1323 { 1324 int i, pipe_idx, active_hubp_count = 0; 1325 bool usr_retraining_support = false; 1326 bool unbounded_req_enabled = false; 1327 1328 dc_assert_fp_enabled(); 1329 1330 /* Writeback MCIF_WB arbitration parameters */ 1331 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 1332 1333 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 1334 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 1335 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 1336 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 1337 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 1338 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 1339 context->bw_ctx.bw.dcn.clk.p_state_change_support = 1340 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 1341 != dm_dram_clock_change_unsupported; 1342 1343 /* Pstate change might not be supported by hardware, but it might be 1344 * possible with firmware driven vertical blank stretching. 1345 */ 1346 context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; 1347 1348 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1349 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 1350 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; 1351 if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) 1352 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; 1353 else 1354 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; 1355 1356 usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1357 ASSERT(usr_retraining_support); 1358 1359 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 1360 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 1361 1362 unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt); 1363 1364 if (unbounded_req_enabled && pipe_cnt > 1) { 1365 // Unbounded requesting should not ever be used when more than 1 pipe is enabled. 1366 ASSERT(false); 1367 unbounded_req_enabled = false; 1368 } 1369 1370 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; 1371 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; 1372 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; 1373 1374 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1375 if (!context->res_ctx.pipe_ctx[i].stream) 1376 continue; 1377 if (context->res_ctx.pipe_ctx[i].plane_state) 1378 active_hubp_count++; 1379 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, 1380 pipe_idx); 1381 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1382 pipe_idx); 1383 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, 1384 pipe_idx); 1385 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1386 pipe_idx); 1387 1388 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1389 // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests 1390 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; 1391 context->res_ctx.pipe_ctx[i].unbounded_req = false; 1392 } else { 1393 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, 1394 pipe_idx); 1395 context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled; 1396 } 1397 1398 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1399 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1400 if (context->res_ctx.pipe_ctx[i].plane_state) 1401 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1402 else 1403 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; 1404 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 1405 1406 context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1407 1408 /* MALL Allocation Sizes */ 1409 /* count from active, top pipes per plane only */ 1410 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state && 1411 (context->res_ctx.pipe_ctx[i].top_pipe == NULL || 1412 context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) && 1413 context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1414 /* SS: all active surfaces stored in MALL */ 1415 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) { 1416 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1417 1418 if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) { 1419 /* SS PSR On: all active surfaces part of streams not supporting PSR stored in MALL */ 1420 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1421 } 1422 } else { 1423 /* SUBVP: phantom surfaces only stored in MALL */ 1424 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1425 } 1426 } 1427 1428 if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) 1429 dcn20_adjust_freesync_v_startup( 1430 &context->res_ctx.pipe_ctx[i].stream->timing, 1431 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); 1432 1433 pipe_idx++; 1434 } 1435 /* If DCN isn't making memory requests we can allow pstate change and lower clocks */ 1436 if (!active_hubp_count) { 1437 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; 1438 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1439 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; 1440 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; 1441 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; 1442 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; 1443 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 1444 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; 1445 } 1446 /*save a original dppclock copy*/ 1447 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 1448 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 1449 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz 1450 * 1000; 1451 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz 1452 * 1000; 1453 1454 context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context); 1455 1456 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes; 1457 1458 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1459 if (context->res_ctx.pipe_ctx[i].stream) 1460 context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb; 1461 } 1462 1463 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1464 1465 if (!context->res_ctx.pipe_ctx[i].stream) 1466 continue; 1467 1468 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, 1469 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, 1470 pipe_cnt, pipe_idx); 1471 1472 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs, 1473 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1474 pipe_idx++; 1475 } 1476 } 1477 1478 static struct pipe_ctx *dcn32_find_split_pipe( 1479 struct dc *dc, 1480 struct dc_state *context, 1481 int old_index) 1482 { 1483 struct pipe_ctx *pipe = NULL; 1484 int i; 1485 1486 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { 1487 pipe = &context->res_ctx.pipe_ctx[old_index]; 1488 pipe->pipe_idx = old_index; 1489 } 1490 1491 if (!pipe) 1492 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1493 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL 1494 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1495 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1496 pipe = &context->res_ctx.pipe_ctx[i]; 1497 pipe->pipe_idx = i; 1498 break; 1499 } 1500 } 1501 } 1502 1503 /* 1504 * May need to fix pipes getting tossed from 1 opp to another on flip 1505 * Add for debugging transient underflow during topology updates: 1506 * ASSERT(pipe); 1507 */ 1508 if (!pipe) 1509 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1510 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1511 pipe = &context->res_ctx.pipe_ctx[i]; 1512 pipe->pipe_idx = i; 1513 break; 1514 } 1515 } 1516 1517 return pipe; 1518 } 1519 1520 static bool dcn32_split_stream_for_mpc_or_odm( 1521 const struct dc *dc, 1522 struct resource_context *res_ctx, 1523 struct pipe_ctx *pri_pipe, 1524 struct pipe_ctx *sec_pipe, 1525 bool odm) 1526 { 1527 int pipe_idx = sec_pipe->pipe_idx; 1528 const struct resource_pool *pool = dc->res_pool; 1529 1530 DC_LOGGER_INIT(dc->ctx->logger); 1531 1532 if (odm && pri_pipe->plane_state) { 1533 /* ODM + window MPO, where MPO window is on left half only */ 1534 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <= 1535 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1536 1537 DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n", 1538 __func__, 1539 pri_pipe->pipe_idx); 1540 return true; 1541 } 1542 1543 /* ODM + window MPO, where MPO window is on right half only */ 1544 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1545 1546 DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n", 1547 __func__, 1548 pri_pipe->pipe_idx); 1549 return true; 1550 } 1551 } 1552 1553 *sec_pipe = *pri_pipe; 1554 1555 sec_pipe->pipe_idx = pipe_idx; 1556 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 1557 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 1558 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 1559 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 1560 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 1561 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 1562 sec_pipe->stream_res.dsc = NULL; 1563 if (odm) { 1564 if (pri_pipe->next_odm_pipe) { 1565 ASSERT(pri_pipe->next_odm_pipe != sec_pipe); 1566 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; 1567 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; 1568 } 1569 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { 1570 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; 1571 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; 1572 } 1573 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { 1574 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; 1575 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; 1576 } 1577 pri_pipe->next_odm_pipe = sec_pipe; 1578 sec_pipe->prev_odm_pipe = pri_pipe; 1579 ASSERT(sec_pipe->top_pipe == NULL); 1580 1581 if (!sec_pipe->top_pipe) 1582 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 1583 else 1584 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; 1585 if (sec_pipe->stream->timing.flags.DSC == 1) { 1586 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 1587 ASSERT(sec_pipe->stream_res.dsc); 1588 if (sec_pipe->stream_res.dsc == NULL) 1589 return false; 1590 } 1591 } else { 1592 if (pri_pipe->bottom_pipe) { 1593 ASSERT(pri_pipe->bottom_pipe != sec_pipe); 1594 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; 1595 sec_pipe->bottom_pipe->top_pipe = sec_pipe; 1596 } 1597 pri_pipe->bottom_pipe = sec_pipe; 1598 sec_pipe->top_pipe = pri_pipe; 1599 1600 ASSERT(pri_pipe->plane_state); 1601 } 1602 1603 return true; 1604 } 1605 1606 bool dcn32_internal_validate_bw(struct dc *dc, 1607 struct dc_state *context, 1608 display_e2e_pipe_params_st *pipes, 1609 int *pipe_cnt_out, 1610 int *vlevel_out, 1611 bool fast_validate) 1612 { 1613 bool out = false; 1614 bool repopulate_pipes = false; 1615 int split[MAX_PIPES] = { 0 }; 1616 bool merge[MAX_PIPES] = { false }; 1617 bool newly_split[MAX_PIPES] = { false }; 1618 int pipe_cnt, i, pipe_idx; 1619 int vlevel = context->bw_ctx.dml.soc.num_states; 1620 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1621 1622 dc_assert_fp_enabled(); 1623 1624 ASSERT(pipes); 1625 if (!pipes) 1626 return false; 1627 1628 // For each full update, remove all existing phantom pipes first 1629 dc->res_pool->funcs->remove_phantom_pipes(dc, context, fast_validate); 1630 1631 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1632 1633 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1634 1635 if (!pipe_cnt) { 1636 out = true; 1637 goto validate_out; 1638 } 1639 1640 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1641 context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context); 1642 1643 if (!fast_validate) 1644 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt); 1645 1646 if (fast_validate || 1647 (dc->debug.dml_disallow_alternate_prefetch_modes && 1648 (vlevel == context->bw_ctx.dml.soc.num_states || 1649 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) { 1650 /* 1651 * If dml_disallow_alternate_prefetch_modes is false, then we have already 1652 * tried alternate prefetch modes during full validation. 1653 * 1654 * If mode is unsupported or there is no p-state support, then 1655 * fall back to favouring voltage. 1656 * 1657 * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try 1658 * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2) 1659 */ 1660 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1661 dm_prefetch_support_none; 1662 1663 context->bw_ctx.dml.validate_max_state = fast_validate; 1664 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1665 1666 context->bw_ctx.dml.validate_max_state = false; 1667 1668 if (vlevel < context->bw_ctx.dml.soc.num_states) { 1669 memset(split, 0, sizeof(split)); 1670 memset(merge, 0, sizeof(merge)); 1671 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1672 // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML 1673 vba->VoltageLevel = vlevel; 1674 } 1675 } 1676 1677 dml_log_mode_support_params(&context->bw_ctx.dml); 1678 1679 if (vlevel == context->bw_ctx.dml.soc.num_states) 1680 goto validate_fail; 1681 1682 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1683 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1684 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1685 1686 if (!pipe->stream) 1687 continue; 1688 1689 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1690 && !dc->config.enable_windowed_mpo_odm 1691 && pipe->plane_state && mpo_pipe 1692 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1693 &pipe->plane_res.scl_data.recout, 1694 sizeof(struct rect)) != 0) { 1695 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1696 goto validate_fail; 1697 } 1698 pipe_idx++; 1699 } 1700 1701 /* merge pipes if necessary */ 1702 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1703 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1704 1705 /*skip pipes that don't need merging*/ 1706 if (!merge[i]) 1707 continue; 1708 1709 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 1710 if (pipe->prev_odm_pipe) { 1711 /*split off odm pipe*/ 1712 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 1713 if (pipe->next_odm_pipe) 1714 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 1715 1716 /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/ 1717 if (pipe->bottom_pipe) { 1718 if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) { 1719 /*MPC split rules will handle this case*/ 1720 pipe->bottom_pipe->top_pipe = NULL; 1721 } else { 1722 /* when merging an ODM pipes, the bottom MPC pipe must now point to 1723 * the previous ODM pipe and its associated stream assets 1724 */ 1725 if (pipe->prev_odm_pipe->bottom_pipe) { 1726 /* 3 plane MPO*/ 1727 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe; 1728 pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe; 1729 } else { 1730 /* 2 plane MPO*/ 1731 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe; 1732 pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe; 1733 } 1734 1735 memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource)); 1736 } 1737 } 1738 1739 if (pipe->top_pipe) { 1740 pipe->top_pipe->bottom_pipe = NULL; 1741 } 1742 1743 pipe->bottom_pipe = NULL; 1744 pipe->next_odm_pipe = NULL; 1745 pipe->plane_state = NULL; 1746 pipe->stream = NULL; 1747 pipe->top_pipe = NULL; 1748 pipe->prev_odm_pipe = NULL; 1749 if (pipe->stream_res.dsc) 1750 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 1751 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1752 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1753 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); 1754 repopulate_pipes = true; 1755 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 1756 struct pipe_ctx *top_pipe = pipe->top_pipe; 1757 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 1758 1759 top_pipe->bottom_pipe = bottom_pipe; 1760 if (bottom_pipe) 1761 bottom_pipe->top_pipe = top_pipe; 1762 1763 pipe->top_pipe = NULL; 1764 pipe->bottom_pipe = NULL; 1765 pipe->plane_state = NULL; 1766 pipe->stream = NULL; 1767 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1768 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1769 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); 1770 repopulate_pipes = true; 1771 } else 1772 ASSERT(0); /* Should never try to merge master pipe */ 1773 1774 } 1775 1776 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1777 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1778 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1779 struct pipe_ctx *hsplit_pipe = NULL; 1780 bool odm; 1781 int old_index = -1; 1782 1783 if (!pipe->stream || newly_split[i]) 1784 continue; 1785 1786 pipe_idx++; 1787 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; 1788 1789 if (!pipe->plane_state && !odm) 1790 continue; 1791 1792 if (split[i]) { 1793 if (odm) { 1794 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe) 1795 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1796 else if (old_pipe->next_odm_pipe) 1797 old_index = old_pipe->next_odm_pipe->pipe_idx; 1798 } else { 1799 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1800 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1801 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1802 else if (old_pipe->bottom_pipe && 1803 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1804 old_index = old_pipe->bottom_pipe->pipe_idx; 1805 } 1806 hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index); 1807 ASSERT(hsplit_pipe); 1808 if (!hsplit_pipe) 1809 goto validate_fail; 1810 1811 if (!dcn32_split_stream_for_mpc_or_odm( 1812 dc, &context->res_ctx, 1813 pipe, hsplit_pipe, odm)) 1814 goto validate_fail; 1815 1816 newly_split[hsplit_pipe->pipe_idx] = true; 1817 repopulate_pipes = true; 1818 } 1819 if (split[i] == 4) { 1820 struct pipe_ctx *pipe_4to1; 1821 1822 if (odm && old_pipe->next_odm_pipe) 1823 old_index = old_pipe->next_odm_pipe->pipe_idx; 1824 else if (!odm && old_pipe->bottom_pipe && 1825 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1826 old_index = old_pipe->bottom_pipe->pipe_idx; 1827 else 1828 old_index = -1; 1829 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1830 ASSERT(pipe_4to1); 1831 if (!pipe_4to1) 1832 goto validate_fail; 1833 if (!dcn32_split_stream_for_mpc_or_odm( 1834 dc, &context->res_ctx, 1835 pipe, pipe_4to1, odm)) 1836 goto validate_fail; 1837 newly_split[pipe_4to1->pipe_idx] = true; 1838 1839 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe 1840 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe) 1841 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1842 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1843 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && 1844 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1845 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1846 else 1847 old_index = -1; 1848 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1849 ASSERT(pipe_4to1); 1850 if (!pipe_4to1) 1851 goto validate_fail; 1852 if (!dcn32_split_stream_for_mpc_or_odm( 1853 dc, &context->res_ctx, 1854 hsplit_pipe, pipe_4to1, odm)) 1855 goto validate_fail; 1856 newly_split[pipe_4to1->pipe_idx] = true; 1857 } 1858 if (odm) 1859 dcn20_build_mapped_resource(dc, context, pipe->stream); 1860 } 1861 1862 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1863 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1864 1865 if (pipe->plane_state) { 1866 if (!resource_build_scaling_params(pipe)) 1867 goto validate_fail; 1868 } 1869 } 1870 1871 /* Actual dsc count per stream dsc validation*/ 1872 if (!dcn20_validate_dsc(dc, context)) { 1873 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; 1874 goto validate_fail; 1875 } 1876 1877 if (repopulate_pipes) { 1878 int flag_max_mpc_comb = vba->maxMpcComb; 1879 int flag_vlevel = vlevel; 1880 int i; 1881 1882 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1883 1884 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case 1885 * we have to re-calculate the DET allocation and run through DML once more to 1886 * ensure all the params are calculated correctly. We do not need to run the 1887 * pipe split check again after this call (pipes are already split / merged). 1888 * */ 1889 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1890 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1891 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1892 if (vlevel == context->bw_ctx.dml.soc.num_states) { 1893 /* failed after DET size changes */ 1894 goto validate_fail; 1895 } else if (flag_max_mpc_comb == 0 && 1896 flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) { 1897 /* check the context constructed with pipe split flags is still valid*/ 1898 bool flags_valid = false; 1899 for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { 1900 if (vba->ModeSupport[i][flag_max_mpc_comb]) { 1901 vba->maxMpcComb = flag_max_mpc_comb; 1902 vba->VoltageLevel = i; 1903 vlevel = i; 1904 flags_valid = true; 1905 } 1906 } 1907 1908 /* this should never happen */ 1909 if (!flags_valid) 1910 goto validate_fail; 1911 } 1912 } 1913 *vlevel_out = vlevel; 1914 *pipe_cnt_out = pipe_cnt; 1915 1916 out = true; 1917 goto validate_out; 1918 1919 validate_fail: 1920 out = false; 1921 1922 validate_out: 1923 return out; 1924 } 1925 1926 1927 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 1928 display_e2e_pipe_params_st *pipes, 1929 int pipe_cnt, 1930 int vlevel) 1931 { 1932 int i, pipe_idx, vlevel_temp = 0; 1933 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 1934 double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1935 double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation; 1936 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 1937 dm_dram_clock_change_unsupported; 1938 unsigned int dummy_latency_index = 0; 1939 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 1940 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 1941 bool subvp_in_use = dcn32_subvp_in_use(dc, context); 1942 unsigned int min_dram_speed_mts_margin; 1943 bool need_fclk_lat_as_dummy = false; 1944 bool is_subvp_p_drr = false; 1945 struct dc_stream_state *fpo_candidate_stream = NULL; 1946 1947 dc_assert_fp_enabled(); 1948 1949 /* need to find dummy latency index for subvp */ 1950 if (subvp_in_use) { 1951 /* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */ 1952 if (!pstate_en) { 1953 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; 1954 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter; 1955 pstate_en = true; 1956 is_subvp_p_drr = true; 1957 } 1958 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 1959 context, pipes, pipe_cnt, vlevel); 1960 1961 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so prefetch is 1962 * scheduled correctly to account for dummy pstate. 1963 */ 1964 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { 1965 need_fclk_lat_as_dummy = true; 1966 context->bw_ctx.dml.soc.fclk_change_latency_us = 1967 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 1968 } 1969 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 1970 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 1971 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 1972 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 1973 if (is_subvp_p_drr) { 1974 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; 1975 } 1976 } 1977 1978 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1979 for (i = 0; i < context->stream_count; i++) { 1980 if (context->streams[i]) 1981 context->streams[i]->fpo_in_use = false; 1982 } 1983 1984 if (!pstate_en || (!dc->debug.disable_fpo_optimizations && 1985 pstate_en && vlevel != 0)) { 1986 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */ 1987 fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context); 1988 if (fpo_candidate_stream) { 1989 fpo_candidate_stream->fpo_in_use = true; 1990 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; 1991 } 1992 1993 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 1994 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 1995 context, pipes, pipe_cnt, vlevel); 1996 1997 /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch 1998 * we reinstate the original dram_clock_change_latency_us on the context 1999 * and all variables that may have changed up to this point, except the 2000 * newly found dummy_latency_index 2001 */ 2002 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2003 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2004 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so 2005 * prefetch is scheduled correctly to account for dummy pstate. 2006 */ 2007 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { 2008 need_fclk_lat_as_dummy = true; 2009 context->bw_ctx.dml.soc.fclk_change_latency_us = 2010 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2011 } 2012 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false); 2013 if (vlevel_temp < vlevel) { 2014 vlevel = vlevel_temp; 2015 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 2016 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2017 pstate_en = true; 2018 } else { 2019 /* Restore FCLK latency and re-run validation to go back to original validation 2020 * output if we find that enabling FPO does not give us any benefit (i.e. lower 2021 * voltage level) 2022 */ 2023 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 2024 for (i = 0; i < context->stream_count; i++) { 2025 if (context->streams[i]) 2026 context->streams[i]->fpo_in_use = false; 2027 } 2028 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; 2029 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 2030 } 2031 } 2032 } 2033 2034 /* Set B: 2035 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present, 2036 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark 2037 * calculations to cover bootup clocks. 2038 * DCFCLK: soc.clock_limits[2] when available 2039 * UCLK: soc.clock_limits[2] when available 2040 */ 2041 if (dcn3_2_soc.num_states > 2) { 2042 vlevel_temp = 2; 2043 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; 2044 } else 2045 dcfclk = 615; //DCFCLK Vmin_lv 2046 2047 pipes[0].clks_cfg.voltage = vlevel_temp; 2048 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2049 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 2050 2051 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 2052 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 2053 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us; 2054 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 2055 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 2056 } 2057 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2058 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2059 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2060 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2061 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2062 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2063 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2064 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2065 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2066 context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2067 2068 /* Set D: 2069 * All clocks min. 2070 * DCFCLK: Min, as reported by PM FW when available 2071 * UCLK : Min, as reported by PM FW when available 2072 * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr) 2073 */ 2074 2075 /* 2076 if (dcn3_2_soc.num_states > 2) { 2077 vlevel_temp = 0; 2078 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; 2079 } else 2080 dcfclk = 615; //DCFCLK Vmin_lv 2081 2082 pipes[0].clks_cfg.voltage = vlevel_temp; 2083 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2084 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 2085 2086 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 2087 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 2088 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us; 2089 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 2090 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 2091 } 2092 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2093 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2094 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2095 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2096 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2097 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2098 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2099 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2100 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2101 context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2102 */ 2103 2104 /* Set C, for Dummy P-State: 2105 * All clocks min. 2106 * DCFCLK: Min, as reported by PM FW, when available 2107 * UCLK : Min, as reported by PM FW, when available 2108 * pstate latency as per UCLK state dummy pstate latency 2109 */ 2110 2111 // For Set A and Set C use values from validation 2112 pipes[0].clks_cfg.voltage = vlevel; 2113 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation; 2114 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2115 2116 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2117 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching; 2118 } 2119 2120 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 2121 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 2122 min_dram_speed_mts_margin = 160; 2123 2124 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2125 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; 2126 2127 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == 2128 dm_dram_clock_change_unsupported) { 2129 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1; 2130 2131 min_dram_speed_mts = 2132 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; 2133 } 2134 2135 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) { 2136 /* find largest table entry that is lower than dram speed, 2137 * but lower than DPM0 still uses DPM0 2138 */ 2139 for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--) 2140 if (min_dram_speed_mts + min_dram_speed_mts_margin > 2141 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) 2142 break; 2143 } 2144 2145 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2146 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2147 2148 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us; 2149 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 2150 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 2151 } 2152 2153 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2154 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2155 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2156 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2157 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2158 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2159 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2160 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2161 /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state. 2162 * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM 2163 * value. 2164 */ 2165 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2166 context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2167 2168 if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { 2169 /* The only difference between A and C is p-state latency, if p-state is not supported 2170 * with full p-state latency we want to calculate DLG based on dummy p-state latency, 2171 * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30. 2172 */ 2173 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; 2174 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; 2175 /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case 2176 * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported 2177 */ 2178 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2179 } else { 2180 /* Set A: 2181 * All clocks min. 2182 * DCFCLK: Min, as reported by PM FW, when available 2183 * UCLK: Min, as reported by PM FW, when available 2184 */ 2185 2186 /* For set A set the correct latency values (i.e. non-dummy values) unconditionally 2187 */ 2188 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2189 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 2190 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 2191 2192 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2193 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2194 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2195 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2196 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2197 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2198 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2199 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2200 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2201 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2202 } 2203 2204 /* Make set D = set A since we do not optimized watermarks for MALL */ 2205 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 2206 2207 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2208 if (!context->res_ctx.pipe_ctx[i].stream) 2209 continue; 2210 2211 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 2212 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 2213 2214 if (dc->config.forced_clocks) { 2215 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2216 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2217 } 2218 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 2219 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2220 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2221 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2222 2223 pipe_idx++; 2224 } 2225 2226 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; 2227 2228 /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */ 2229 if (need_fclk_lat_as_dummy) 2230 context->bw_ctx.dml.soc.fclk_change_latency_us = 2231 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2232 2233 dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2234 2235 if (!pstate_en) 2236 /* Restore full p-state latency */ 2237 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2238 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2239 2240 /* revert fclk lat changes if required */ 2241 if (need_fclk_lat_as_dummy) 2242 context->bw_ctx.dml.soc.fclk_change_latency_us = 2243 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; 2244 } 2245 2246 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 2247 unsigned int *optimal_dcfclk, 2248 unsigned int *optimal_fclk) 2249 { 2250 double bw_from_dram, bw_from_dram1, bw_from_dram2; 2251 2252 bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans * 2253 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); 2254 bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans * 2255 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); 2256 2257 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 2258 2259 if (optimal_fclk) 2260 *optimal_fclk = bw_from_dram / 2261 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2262 2263 if (optimal_dcfclk) 2264 *optimal_dcfclk = bw_from_dram / 2265 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2266 } 2267 2268 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 2269 unsigned int index) 2270 { 2271 int i; 2272 2273 if (*num_entries == 0) 2274 return; 2275 2276 for (i = index; i < *num_entries - 1; i++) { 2277 table[i] = table[i + 1]; 2278 } 2279 memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 2280 } 2281 2282 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params) 2283 { 2284 int i; 2285 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 2286 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 2287 2288 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2289 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2290 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2291 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 2292 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2293 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 2294 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2295 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2296 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2297 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2298 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2299 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2300 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2301 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 2302 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2303 } 2304 2305 /* Scan through clock values we currently have and if they are 0, 2306 * then populate it with dcn3_2_soc.clock_limits[] value. 2307 * 2308 * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being 2309 * 0, will cause it to skip building the clock table. 2310 */ 2311 if (max_dcfclk_mhz == 0) 2312 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2313 if (max_dispclk_mhz == 0) 2314 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2315 if (max_dtbclk_mhz == 0) 2316 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; 2317 if (max_uclk_mhz == 0) 2318 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16; 2319 } 2320 2321 static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 2322 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2323 { 2324 int i, j; 2325 struct _vcs_dpi_voltage_scaling_st entry = {0}; 2326 2327 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 2328 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 2329 2330 unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 2331 2332 static const unsigned int num_dcfclk_stas = 5; 2333 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2334 2335 unsigned int num_uclk_dpms = 0; 2336 unsigned int num_fclk_dpms = 0; 2337 unsigned int num_dcfclk_dpms = 0; 2338 2339 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2340 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2341 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2342 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 2343 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2344 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 2345 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2346 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2347 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2348 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2349 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2350 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2351 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2352 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 2353 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2354 2355 if (bw_params->clk_table.entries[i].memclk_mhz > 0) 2356 num_uclk_dpms++; 2357 if (bw_params->clk_table.entries[i].fclk_mhz > 0) 2358 num_fclk_dpms++; 2359 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) 2360 num_dcfclk_dpms++; 2361 } 2362 2363 if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz) 2364 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; 2365 2366 if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz) 2367 return -1; 2368 2369 if (max_dppclk_mhz == 0) 2370 max_dppclk_mhz = max_dispclk_mhz; 2371 2372 if (max_fclk_mhz == 0) 2373 max_fclk_mhz = max_dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / dcn3_2_soc.pct_ideal_fabric_bw_after_urgent; 2374 2375 if (max_phyclk_mhz == 0) 2376 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2377 2378 *num_entries = 0; 2379 entry.dispclk_mhz = max_dispclk_mhz; 2380 entry.dscclk_mhz = max_dispclk_mhz / 3; 2381 entry.dppclk_mhz = max_dppclk_mhz; 2382 entry.dtbclk_mhz = max_dtbclk_mhz; 2383 entry.phyclk_mhz = max_phyclk_mhz; 2384 entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2385 entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2386 2387 // Insert all the DCFCLK STAs 2388 for (i = 0; i < num_dcfclk_stas; i++) { 2389 entry.dcfclk_mhz = dcfclk_sta_targets[i]; 2390 entry.fabricclk_mhz = 0; 2391 entry.dram_speed_mts = 0; 2392 2393 insert_entry_into_table_sorted(table, num_entries, &entry); 2394 } 2395 2396 // Insert the max DCFCLK 2397 entry.dcfclk_mhz = max_dcfclk_mhz; 2398 entry.fabricclk_mhz = 0; 2399 entry.dram_speed_mts = 0; 2400 2401 insert_entry_into_table_sorted(table, num_entries, &entry); 2402 2403 // Insert the UCLK DPMS 2404 for (i = 0; i < num_uclk_dpms; i++) { 2405 entry.dcfclk_mhz = 0; 2406 entry.fabricclk_mhz = 0; 2407 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 2408 2409 insert_entry_into_table_sorted(table, num_entries, &entry); 2410 } 2411 2412 // If FCLK is coarse grained, insert individual DPMs. 2413 if (num_fclk_dpms > 2) { 2414 for (i = 0; i < num_fclk_dpms; i++) { 2415 entry.dcfclk_mhz = 0; 2416 entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2417 entry.dram_speed_mts = 0; 2418 2419 insert_entry_into_table_sorted(table, num_entries, &entry); 2420 } 2421 } 2422 // If FCLK fine grained, only insert max 2423 else { 2424 entry.dcfclk_mhz = 0; 2425 entry.fabricclk_mhz = max_fclk_mhz; 2426 entry.dram_speed_mts = 0; 2427 2428 insert_entry_into_table_sorted(table, num_entries, &entry); 2429 } 2430 2431 // At this point, the table contains all "points of interest" based on 2432 // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 2433 // ratios (by derate, are exact). 2434 2435 // Remove states that require higher clocks than are supported 2436 for (i = *num_entries - 1; i >= 0 ; i--) { 2437 if (table[i].dcfclk_mhz > max_dcfclk_mhz || 2438 table[i].fabricclk_mhz > max_fclk_mhz || 2439 table[i].dram_speed_mts > max_uclk_mhz * 16) 2440 remove_entry_from_table_at_index(table, num_entries, i); 2441 } 2442 2443 // At this point, the table only contains supported points of interest 2444 // it could be used as is, but some states may be redundant due to 2445 // coarse grained nature of some clocks, so we want to round up to 2446 // coarse grained DPMs and remove duplicates. 2447 2448 // Round up UCLKs 2449 for (i = *num_entries - 1; i >= 0 ; i--) { 2450 for (j = 0; j < num_uclk_dpms; j++) { 2451 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 2452 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 2453 break; 2454 } 2455 } 2456 } 2457 2458 // If FCLK is coarse grained, round up to next DPMs 2459 if (num_fclk_dpms > 2) { 2460 for (i = *num_entries - 1; i >= 0 ; i--) { 2461 for (j = 0; j < num_fclk_dpms; j++) { 2462 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 2463 table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 2464 break; 2465 } 2466 } 2467 } 2468 } 2469 // Otherwise, round up to minimum. 2470 else { 2471 for (i = *num_entries - 1; i >= 0 ; i--) { 2472 if (table[i].fabricclk_mhz < min_fclk_mhz) { 2473 table[i].fabricclk_mhz = min_fclk_mhz; 2474 } 2475 } 2476 } 2477 2478 // Round DCFCLKs up to minimum 2479 for (i = *num_entries - 1; i >= 0 ; i--) { 2480 if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 2481 table[i].dcfclk_mhz = min_dcfclk_mhz; 2482 } 2483 } 2484 2485 // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 2486 i = 0; 2487 while (i < *num_entries - 1) { 2488 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 2489 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 2490 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 2491 remove_entry_from_table_at_index(table, num_entries, i + 1); 2492 else 2493 i++; 2494 } 2495 2496 // Fix up the state indicies 2497 for (i = *num_entries - 1; i >= 0 ; i--) { 2498 table[i].state = i; 2499 } 2500 2501 return 0; 2502 } 2503 2504 /* 2505 * dcn32_update_bw_bounding_box 2506 * 2507 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from 2508 * spreadsheet with actual values as per dGPU SKU: 2509 * - with passed few options from dc->config 2510 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might 2511 * need to get it from PM FW) 2512 * - with passed latency values (passed in ns units) in dc-> bb override for 2513 * debugging purposes 2514 * - with passed latencies from VBIOS (in 100_ns units) if available for 2515 * certain dGPU SKU 2516 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU 2517 * of the same ASIC) 2518 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM 2519 * FW for different clocks (which might differ for certain dGPU SKU of the 2520 * same ASIC) 2521 */ 2522 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 2523 { 2524 dc_assert_fp_enabled(); 2525 2526 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2527 /* Overrides from dc->config options */ 2528 dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 2529 2530 /* Override from passed dc->bb_overrides if available*/ 2531 if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 2532 && dc->bb_overrides.sr_exit_time_ns) { 2533 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 2534 } 2535 2536 if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000) 2537 != dc->bb_overrides.sr_enter_plus_exit_time_ns 2538 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 2539 dcn3_2_soc.sr_enter_plus_exit_time_us = 2540 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 2541 } 2542 2543 if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 2544 && dc->bb_overrides.urgent_latency_ns) { 2545 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2546 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2547 } 2548 2549 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) 2550 != dc->bb_overrides.dram_clock_change_latency_ns 2551 && dc->bb_overrides.dram_clock_change_latency_ns) { 2552 dcn3_2_soc.dram_clock_change_latency_us = 2553 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 2554 } 2555 2556 if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000) 2557 != dc->bb_overrides.fclk_clock_change_latency_ns 2558 && dc->bb_overrides.fclk_clock_change_latency_ns) { 2559 dcn3_2_soc.fclk_change_latency_us = 2560 dc->bb_overrides.fclk_clock_change_latency_ns / 1000; 2561 } 2562 2563 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) 2564 != dc->bb_overrides.dummy_clock_change_latency_ns 2565 && dc->bb_overrides.dummy_clock_change_latency_ns) { 2566 dcn3_2_soc.dummy_pstate_latency_us = 2567 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 2568 } 2569 2570 /* Override from VBIOS if VBIOS bb_info available */ 2571 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 2572 struct bp_soc_bb_info bb_info = {0}; 2573 2574 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 2575 if (bb_info.dram_clock_change_latency_100ns > 0) 2576 dcn3_2_soc.dram_clock_change_latency_us = 2577 bb_info.dram_clock_change_latency_100ns * 10; 2578 2579 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 2580 dcn3_2_soc.sr_enter_plus_exit_time_us = 2581 bb_info.dram_sr_enter_exit_latency_100ns * 10; 2582 2583 if (bb_info.dram_sr_exit_latency_100ns > 0) 2584 dcn3_2_soc.sr_exit_time_us = 2585 bb_info.dram_sr_exit_latency_100ns * 10; 2586 } 2587 } 2588 2589 /* Override from VBIOS for num_chan */ 2590 if (dc->ctx->dc_bios->vram_info.num_chans) { 2591 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 2592 dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc, 2593 dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); 2594 } 2595 2596 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 2597 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 2598 } 2599 2600 /* DML DSC delay factor workaround */ 2601 dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; 2602 2603 dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0; 2604 2605 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 2606 dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2607 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2608 2609 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 2610 if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { 2611 if (dc->debug.use_legacy_soc_bb_mechanism) { 2612 unsigned int i = 0, j = 0, num_states = 0; 2613 2614 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 2615 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 2616 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 2617 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 2618 unsigned int min_dcfclk = UINT_MAX; 2619 /* Set 199 as first value in STA target array to have a minimum DCFCLK value. 2620 * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */ 2621 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2622 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 2623 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 2624 2625 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2626 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2627 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2628 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 && 2629 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk) 2630 min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz; 2631 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2632 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2633 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2634 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2635 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2636 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2637 } 2638 if (min_dcfclk > dcfclk_sta_targets[0]) 2639 dcfclk_sta_targets[0] = min_dcfclk; 2640 if (!max_dcfclk_mhz) 2641 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2642 if (!max_dispclk_mhz) 2643 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2644 if (!max_dppclk_mhz) 2645 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; 2646 if (!max_phyclk_mhz) 2647 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2648 2649 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2650 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2651 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 2652 num_dcfclk_sta_targets++; 2653 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2654 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2655 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2656 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 2657 dcfclk_sta_targets[i] = max_dcfclk_mhz; 2658 break; 2659 } 2660 } 2661 // Update size of array since we "removed" duplicates 2662 num_dcfclk_sta_targets = i + 1; 2663 } 2664 2665 num_uclk_states = bw_params->clk_table.num_entries; 2666 2667 // Calculate optimal dcfclk for each uclk 2668 for (i = 0; i < num_uclk_states; i++) { 2669 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2670 &optimal_dcfclk_for_uclk[i], NULL); 2671 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 2672 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 2673 } 2674 } 2675 2676 // Calculate optimal uclk for each dcfclk sta target 2677 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2678 for (j = 0; j < num_uclk_states; j++) { 2679 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 2680 optimal_uclk_for_dcfclk_sta_targets[i] = 2681 bw_params->clk_table.entries[j].memclk_mhz * 16; 2682 break; 2683 } 2684 } 2685 } 2686 2687 i = 0; 2688 j = 0; 2689 // create the final dcfclk and uclk table 2690 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2691 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 2692 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2693 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2694 } else { 2695 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2696 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2697 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2698 } else { 2699 j = num_uclk_states; 2700 } 2701 } 2702 } 2703 2704 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 2705 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2706 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2707 } 2708 2709 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2710 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2711 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2712 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2713 } 2714 2715 dcn3_2_soc.num_states = num_states; 2716 for (i = 0; i < dcn3_2_soc.num_states; i++) { 2717 dcn3_2_soc.clock_limits[i].state = i; 2718 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 2719 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 2720 2721 /* Fill all states with max values of all these clocks */ 2722 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 2723 dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 2724 dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 2725 dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 2726 2727 /* Populate from bw_params for DTBCLK, SOCCLK */ 2728 if (i > 0) { 2729 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 2730 dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; 2731 } else { 2732 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2733 } 2734 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 2735 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2736 } 2737 2738 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 2739 dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; 2740 else 2741 dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 2742 2743 if (!dram_speed_mts[i] && i > 0) 2744 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; 2745 else 2746 dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 2747 2748 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ 2749 /* PHYCLK_D18, PHYCLK_D32 */ 2750 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2751 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2752 } 2753 } else { 2754 build_synthetic_soc_states(bw_params, dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states); 2755 } 2756 2757 /* Re-init DML with updated bb */ 2758 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2759 if (dc->current_state) 2760 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2761 } 2762 } 2763 2764 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, 2765 int pipe_cnt) 2766 { 2767 dc_assert_fp_enabled(); 2768 2769 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 2770 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 2771 } 2772 2773 bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) 2774 { 2775 bool allow = false; 2776 uint32_t refresh_rate = 0; 2777 2778 /* Allow subvp on displays that have active margin for 2560x1440@60hz displays 2779 * only for now. There must be no scaling as well. 2780 * 2781 * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs 2782 * for p-state switching. 2783 */ 2784 if (pipe->stream && pipe->plane_state) { 2785 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 2786 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 2787 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 2788 if (pipe->stream->timing.v_addressable == 1440 && 2789 pipe->stream->timing.h_addressable == 2560 && 2790 refresh_rate >= 55 && refresh_rate <= 65 && 2791 pipe->plane_state->src_rect.height == 1440 && 2792 pipe->plane_state->src_rect.width == 2560 && 2793 pipe->plane_state->dst_rect.height == 1440 && 2794 pipe->plane_state->dst_rect.width == 2560) 2795 allow = true; 2796 } 2797 return allow; 2798 } 2799 2800 /** 2801 * ************************************************************************************************ 2802 * dcn32_allow_subvp_high_refresh_rate: Determine if the high refresh rate config will allow subvp 2803 * 2804 * @param [in]: dc: Current DC state 2805 * @param [in]: context: New DC state to be programmed 2806 * @param [in]: pipe: Pipe to be considered for use in subvp 2807 * 2808 * On high refresh rate display configs, we will allow subvp under the following conditions: 2809 * 1. Resolution is 3840x2160, 3440x1440, or 2560x1440 2810 * 2. Refresh rate is between 120hz - 165hz 2811 * 3. No scaling 2812 * 4. Freesync is inactive 2813 * 5. For single display cases, freesync must be disabled 2814 * 2815 * @return: True if pipe can be used for subvp, false otherwise 2816 * 2817 * ************************************************************************************************ 2818 */ 2819 bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe) 2820 { 2821 bool allow = false; 2822 uint32_t refresh_rate = 0; 2823 uint32_t min_refresh = subvp_high_refresh_list.min_refresh; 2824 uint32_t max_refresh = subvp_high_refresh_list.max_refresh; 2825 uint32_t i; 2826 2827 if (!dc->debug.disable_subvp_high_refresh && pipe->stream && 2828 pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) { 2829 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 2830 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 2831 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 2832 if (refresh_rate >= min_refresh && refresh_rate <= max_refresh) { 2833 for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) { 2834 uint32_t width = subvp_high_refresh_list.res[i].width; 2835 uint32_t height = subvp_high_refresh_list.res[i].height; 2836 2837 if (dcn32_check_native_scaling_for_res(pipe, width, height)) { 2838 if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) { 2839 allow = true; 2840 break; 2841 } 2842 } 2843 } 2844 } 2845 } 2846 return allow; 2847 } 2848 2849 /** 2850 * ******************************************************************************************* 2851 * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy 2852 * 2853 * @param [in]: dc: Current DC state 2854 * @param [in]: context: New DC state to be programmed 2855 * 2856 * @return: Max vratio for prefetch 2857 * 2858 * ******************************************************************************************* 2859 */ 2860 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context) 2861 { 2862 double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4 2863 int i; 2864 2865 /* For single display MPO configs, allow the max vratio to be 8 2866 * if any plane is YUV420 format 2867 */ 2868 if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) { 2869 for (i = 0; i < context->stream_status[0].plane_count; i++) { 2870 if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr || 2871 context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) { 2872 max_vratio_pre = __DML_MAX_VRATIO_PRE__; 2873 } 2874 } 2875 } 2876 return max_vratio_pre; 2877 } 2878 2879 /** 2880 * dcn32_assign_fpo_vactive_candidate - Assign the FPO stream candidate for FPO + VActive case 2881 * 2882 * This function chooses the FPO candidate stream for FPO + VActive cases (2 stream config). 2883 * For FPO + VAtive cases, the assumption is that one display has ActiveMargin > 0, and the 2884 * other display has ActiveMargin <= 0. This function will choose the pipe/stream that has 2885 * ActiveMargin <= 0 to be the FPO stream candidate if found. 2886 * 2887 * 2888 * @param [in]: dc - current dc state 2889 * @param [in]: context - new dc state 2890 * @param [out]: fpo_candidate_stream - pointer to FPO stream candidate if one is found 2891 * 2892 * Return: void 2893 */ 2894 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream) 2895 { 2896 unsigned int i, pipe_idx; 2897 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 2898 2899 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2900 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2901 2902 if (!pipe->stream) 2903 continue; 2904 2905 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) { 2906 *fpo_candidate_stream = pipe->stream; 2907 break; 2908 } 2909 pipe_idx++; 2910 } 2911 } 2912 2913 /** 2914 * dcn32_find_vactive_pipe - Determines if the config has a pipe that can switch in VACTIVE 2915 * 2916 * @param [in]: dc - current dc state 2917 * @param [in]: context - new dc state 2918 * @param [in]: vactive_margin_req_us - The vactive marign required for a vactive pipe to be 2919 * considered "found" 2920 * 2921 * Return: True if VACTIVE display is found, false otherwise 2922 */ 2923 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us) 2924 { 2925 unsigned int i, pipe_idx; 2926 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 2927 bool vactive_found = false; 2928 unsigned int blank_us = 0; 2929 2930 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2931 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2932 2933 if (!pipe->stream) 2934 continue; 2935 2936 blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total / 2937 (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000; 2938 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] >= vactive_margin_req_us && 2939 !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed) && blank_us < dc->debug.fpo_vactive_max_blank_us) { 2940 vactive_found = true; 2941 break; 2942 } 2943 pipe_idx++; 2944 } 2945 return vactive_found; 2946 } 2947 2948 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb) 2949 { 2950 dc_assert_fp_enabled(); 2951 dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0; 2952 } 2953 2954 void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context) 2955 { 2956 // WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue) 2957 if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) && 2958 dc->dml.soc.num_chans <= 8) { 2959 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; 2960 2961 if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 && 2962 num_mclk_levels > 1) { 2963 context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16; 2964 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 2965 } 2966 } 2967 } 2968