Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2 |
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#
e97cc04f |
| 15-Feb-2023 |
Josip Pavic <Josip.Pavic@amd.com> |
drm/amd/display: refactor dmub commands into single function
[Why & How] Consolidate dmub access to a single interface. This makes it easier to add code in the future that needs to run every time a
drm/amd/display: refactor dmub commands into single function
[Why & How] Consolidate dmub access to a single interface. This makes it easier to add code in the future that needs to run every time a dmub command is requested (e.g. instrumentation, locking etc).
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8 |
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#
240e6d25 |
| 08-Dec-2021 |
Isabella Basso <isabbasso@riseup.net> |
drm/amd/display: fix function scopes
This turns previously global functions into static, thus removing compile-time warnings such as:
warning: no previous prototype for 'get_highest_allowed_voltag
drm/amd/display: fix function scopes
This turns previously global functions into static, thus removing compile-time warnings such as:
warning: no previous prototype for 'get_highest_allowed_voltage_level' [-Wmissing-prototypes] 742 | unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ warning: no previous prototype for 'rv1_vbios_smu_send_msg_with_param' [-Wmissing-prototypes] 102 | int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Changes since v1: - As suggested by Rodrigo Siqueira: 1. Rewrite function signatures to make them more readable. 2. Get rid of unused functions in order to remove 'defined but not used' warnings.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Isabella Basso <isabbasso@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46 |
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#
98e95e4f |
| 21-Jun-2021 |
Josip Pavic <Josip.Pavic@amd.com> |
drm/amd/display: log additional register state for debug
[Why & How] Extend existing state collection functions to add some additional registers useful for debug, and add state collection function f
drm/amd/display: log additional register state for debug
[Why & How] Extend existing state collection functions to add some additional registers useful for debug, and add state collection function for DC hubbub
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18 |
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#
0c66824b |
| 19-Feb-2021 |
Qingqing Zhuo <qingqing.zhuo@amd.com> |
drm/amd/display: Enable pflip interrupt upon pipe enable
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP complianc
drm/amd/display: Enable pflip interrupt upon pipe enable
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP compliance tests
[How] Enable pflip interrupt upon pipe enablement
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7afa0033 |
| 19-Feb-2021 |
Qingqing Zhuo <qingqing.zhuo@amd.com> |
drm/amd/display: Enable pflip interrupt upon pipe enable
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP complianc
drm/amd/display: Enable pflip interrupt upon pipe enable
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP compliance tests
[How] Enable pflip interrupt upon pipe enablement
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40 |
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#
429b9db8 |
| 08-May-2020 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Remove nv12 work around
[Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove.
[How] Removed wa from dal side.
Signed-off-by: Yongqiang S
drm/amd/display: Remove nv12 work around
[Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove.
[How] Removed wa from dal side.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35 |
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#
0ed3bcc4 |
| 22-Apr-2020 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Pass command instead of header into DMUB service
[Why] We read memory that we shouldn't be touching if the struct isn't a full union dmub_rb_cmd.
[How] Fix up all the callers and f
drm/amd/display: Pass command instead of header into DMUB service
[Why] We read memory that we shouldn't be touching if the struct isn't a full union dmub_rb_cmd.
[How] Fix up all the callers and functions that take in the dmub_cmd_header to use the dmub_rb_cmd instead.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22 |
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#
0943629c |
| 21-Feb-2020 |
YueHaibing <yuehaibing@huawei.com> |
drm/amd/display: remove set but not used variable 'mc_vm_apt_default'
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.c: In function hubp21_set_vm_system_aperture_settings: drivers/gpu/dr
drm/amd/display: remove set but not used variable 'mc_vm_apt_default'
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.c: In function hubp21_set_vm_system_aperture_settings: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.c:343:23: warning: variable mc_vm_apt_default set but not used [-Wunused-but-set-variable]
It is never used, so remove it.
Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16 |
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#
85e148fb |
| 28-Jan-2020 |
Tony Cheng <tony.cheng@amd.com> |
drm/amd/display: fix workaround for incorrect double buffer register for DLG ADL and TTU
[Why] these registers should have been double buffered. SW workaround we will have SW program the more aggres
drm/amd/display: fix workaround for incorrect double buffer register for DLG ADL and TTU
[Why] these registers should have been double buffered. SW workaround we will have SW program the more aggressive (lower) values whenever we are upating this register, so we will not have underflow at expense of less optimzal request pattern.
[How] there is a driver bug where we don't check for 0, which is uninitialzed HW default. since 0 is smaller than any value we need to program, driver end up with not programming these registers
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9 |
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#
022205ff |
| 09-Jan-2020 |
Brandon Syu <Brandon.Syu@amd.com> |
drm/amd/display: fix rotation_angle to use enum values
[Why] Hardcoded fixed values are not proper.
[How] Use enum values instead of fixed numbers.
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
drm/amd/display: fix rotation_angle to use enum values
[Why] Hardcoded fixed values are not proper.
[How] Use enum values instead of fixed numbers.
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.8, v5.4.7, v5.4.6 |
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#
bae9c49b |
| 18-Dec-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Only program surface flip for video plane via dmcub
Only need to do surface flip for video plane via dmcub.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony C
drm/amd/display: Only program surface flip for video plane via dmcub
Only need to do surface flip for video plane via dmcub.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.5 |
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#
22aa5614 |
| 17-Dec-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Refactor surface flip programming
Rework surface programming for RN to separate preparing parameters and register programming.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
drm/amd/display: Refactor surface flip programming
Rework surface programming for RN to separate preparing parameters and register programming.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.4 |
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#
8c019253 |
| 16-Dec-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: programing surface flip by dmcub.
Programming surface flip addresses via dmcub uC for optimizing the data flush.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: T
drm/amd/display: programing surface flip by dmcub.
Programming surface flip addresses via dmcub uC for optimizing the data flush.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.3 |
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#
93a8955b |
| 09-Dec-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: fix chroma vp wa corner case
[Why] Previous implementation we may have residual chroma address offset if transition from wa enable -> wa disable.
[How] Clear address offset cache w
drm/amd/display: fix chroma vp wa corner case
[Why] Previous implementation we may have residual chroma address offset if transition from wa enable -> wa disable.
[How] Clear address offset cache when viewport updates. Also update the vp size check condition to account for rotation angle
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12 |
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#
cf27a6d1 |
| 18-Nov-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: update chroma viewport wa
[Why] Need previously implemented chroma vp wa to work for rotation cases.
[How] Implement rotation specific wa.
Signed-off-by: Eric Yang <Eric.Yang2@amd
drm/amd/display: update chroma viewport wa
[Why] Need previously implemented chroma vp wa to work for rotation cases.
[How] Implement rotation specific wa.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ddba7627 |
| 15-Nov-2019 |
Anthony Koo <Anthony.Koo@amd.com> |
drm/amd/display: Limit NV12 chroma workaround
[Why] It is causing green Line at the bottom of SDR 480p MPO playback
[How] Limit workaround to vertical > 512
Signed-off-by: Anthony Koo <Anthony.Koo
drm/amd/display: Limit NV12 chroma workaround
[Why] It is causing green Line at the bottom of SDR 480p MPO playback
[How] Limit workaround to vertical > 512
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.11 |
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#
1ba2a483 |
| 10-Nov-2019 |
Michael Strauss <michael.strauss@amd.com> |
drm/amd/display: Disable chroma viewport w/a when rotated 180 degrees
[WHY] Previous Renoir chroma viewport workaround fixed an MPO flicker by increasing the chroma viewport size. However, when the
drm/amd/display: Disable chroma viewport w/a when rotated 180 degrees
[WHY] Previous Renoir chroma viewport workaround fixed an MPO flicker by increasing the chroma viewport size. However, when the MPO plane is rotated 180 degrees, the viewport is read in reverse. Since the workaround increases viewport size, when reading in reverse it causes a vertical chroma offset.
[HOW] Pass rotation value to viewport set functions Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees
Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.10 |
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#
a4cea116 |
| 07-Nov-2019 |
Jaehyun Chung <jaehyun.chung@amd.com> |
drm/amd/display: Wrong ifdef guards were used around DML validation
[Why] Wrong guards were causing the debug option not to run.
[How] Changed the guard to the correct one, matching the rq, ttu, dl
drm/amd/display: Wrong ifdef guards were used around DML validation
[Why] Wrong guards were causing the debug option not to run.
[How] Changed the guard to the correct one, matching the rq, ttu, dlg regs struct members that need to be guarded. Also log a message when validation starts.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.9 |
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#
b9fe5151 |
| 31-Oct-2019 |
Jaehyun Chung <jaehyun.chung@amd.com> |
drm/amd/display: DML Validation Dump/Check with Logging
[Why] Need validation that we are programming the expected values (rq, ttu, dlg) from DML. This debug feature will output logs if we are progr
drm/amd/display: DML Validation Dump/Check with Logging
[Why] Need validation that we are programming the expected values (rq, ttu, dlg) from DML. This debug feature will output logs if we are programming incorrect values and may help differentiate DAL issues from HW issues.
[How] Dump relevant registers for each pipe with active stream. Compare current reg values with the converted DML output. Log mismatches when found.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.8 |
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#
db8ff9d3 |
| 24-Oct-2019 |
Joseph Gravenor <joseph.gravenor@amd.com> |
drm/amd/display: Renoir chroma viewport WA Read the correct register
[why] Before we were reading registers specific to luma size, which caused a black line to appear on the screen from time to time
drm/amd/display: Renoir chroma viewport WA Read the correct register
[why] Before we were reading registers specific to luma size, which caused a black line to appear on the screen from time to time, as although the luma row height is generally the same as the chroma row height for the video case, it will sometimes be one more
[how] Read the register specific for the chroma size
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.7 |
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#
e6b268dd |
| 17-Oct-2019 |
Joseph Gravenor <joseph.gravenor@amd.com> |
drm/amd/display: Renoir chroma viewport WA change formula
[why] we want to increase the pte row plus 1 line if chroma viewport height is integer multiple of the pte row height
[how] instead of ceil
drm/amd/display: Renoir chroma viewport WA change formula
[why] we want to increase the pte row plus 1 line if chroma viewport height is integer multiple of the pte row height
[how] instead of ceiling viewport height, we floor it. this allows us to accommodate both cases: those where the chroma viewport height is integer multiple of the pte row height and those where it is not
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1cad8ff7 |
| 11-Oct-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: Renoir chroma viewport WA
[Why] For unknown reason, immediate flip with host VM translation on NV12 surface will underflow on last row of PTE.
[How] Hack chroma viewport height to
drm/amd/display: Renoir chroma viewport WA
[Why] For unknown reason, immediate flip with host VM translation on NV12 surface will underflow on last row of PTE.
[How] Hack chroma viewport height to make fetch one more row of PTE. Note that this will cause hubp underflow on all video underlay cases, but the underflow is not user visible since it is in blank region.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
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02981b28 |
| 02-Oct-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: use dcn10 version of program tiling on Renoir
[Why] Renoir is gfx9, same as dcn10, not dcn20.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet
drm/amd/display: use dcn10 version of program tiling on Renoir
[Why] Renoir is gfx9, same as dcn10, not dcn20.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3 |
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eced51f9 |
| 25-Jul-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Add hubp block for Renoir (v2)
This provides the interface to memory for the display hw.
v2: minor cleanup (Alex)
Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
drm/amd/display: Add hubp block for Renoir (v2)
This provides the interface to memory for the display hw.
v2: minor cleanup (Alex)
Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40 |
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429b9db8 |
| 08-May-2020 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Remove nv12 work around [Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove. [How] Removed wa from dal side.
drm/amd/display: Remove nv12 work around [Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove. [How] Removed wa from dal side. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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