1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn10/dcn10_hubp.h" 27 #include "dcn21_hubp.h" 28 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 32 #define DC_LOGGER_INIT(logger) 33 34 #define REG(reg)\ 35 hubp21->hubp_regs->reg 36 37 #define CTX \ 38 hubp21->base.ctx 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 43 44 /* 45 * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 46 * As a result, if S/W updates any of these registers during a mode change, 47 * the current frame before the mode change will use the new value right away 48 * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 49 * 50 * REFCYC_PER_VM_GROUP_FLIP[22:0] 51 * REFCYC_PER_VM_GROUP_VBLANK[22:0] 52 * REFCYC_PER_VM_REQ_FLIP[22:0] 53 * REFCYC_PER_VM_REQ_VBLANK[22:0] 54 * 55 * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 56 * when flipping to a new surface 57 * 58 * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 59 * during prefetch period of a frame. The prefetch starts at a pre-determined 60 * number of lines before the display active per frame 61 * 62 * DCN may underflow due to incorrectly programming these registers 63 * during VM stage of prefetch/iflip. First lines of display active 64 * or a sub-region of active using a new surface will be corrupted 65 * until the VM data returns at flip/mode change transitions 66 * 67 * Work around: 68 * workaround is always opt to use the more aggressive settings. 69 * On any mode switch, if the new reg values are smaller than the current values, 70 * then update the regs with the new values. 71 * 72 * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 73 * 74 */ 75 void apply_DEDCN21_142_wa_for_hostvm_deadline( 76 struct hubp *hubp, 77 struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 78 { 79 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 80 uint32_t cur_value; 81 82 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); 83 if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) 84 REG_SET(VBLANK_PARAMETERS_5, 0, 85 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 86 87 REG_GET(VBLANK_PARAMETERS_6, 88 REFCYC_PER_VM_REQ_VBLANK, 89 &cur_value); 90 if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) 91 REG_SET(VBLANK_PARAMETERS_6, 0, 92 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 93 94 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); 95 if (cur_value > dlg_attr->refcyc_per_vm_group_flip) 96 REG_SET(FLIP_PARAMETERS_3, 0, 97 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 98 99 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); 100 if (cur_value > dlg_attr->refcyc_per_vm_req_flip) 101 REG_SET(FLIP_PARAMETERS_4, 0, 102 REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 103 104 REG_SET(FLIP_PARAMETERS_5, 0, 105 REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 106 REG_SET(FLIP_PARAMETERS_6, 0, 107 REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 108 } 109 110 void hubp21_program_deadline( 111 struct hubp *hubp, 112 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 113 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 114 { 115 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 116 117 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 118 } 119 120 void hubp21_program_requestor( 121 struct hubp *hubp, 122 struct _vcs_dpi_display_rq_regs_st *rq_regs) 123 { 124 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 125 126 REG_UPDATE(HUBPRET_CONTROL, 127 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 128 REG_SET_4(DCN_EXPANSION_MODE, 0, 129 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 130 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 131 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 132 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 133 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 134 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 135 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 136 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 137 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 138 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 139 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 140 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 141 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 142 REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 143 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 144 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 145 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 146 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 147 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 148 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 149 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 150 } 151 152 static void hubp21_setup( 153 struct hubp *hubp, 154 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 155 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 156 struct _vcs_dpi_display_rq_regs_st *rq_regs, 157 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 158 { 159 /* otg is locked when this func is called. Register are double buffered. 160 * disable the requestors is not needed 161 */ 162 163 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 164 hubp21_program_requestor(hubp, rq_regs); 165 hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 166 167 } 168 169 void hubp21_set_viewport( 170 struct hubp *hubp, 171 const struct rect *viewport, 172 const struct rect *viewport_c, 173 enum dc_rotation_angle rotation) 174 { 175 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 176 int patched_viewport_height = 0; 177 struct dc_debug_options *debug = &hubp->ctx->dc->debug; 178 179 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 180 PRI_VIEWPORT_WIDTH, viewport->width, 181 PRI_VIEWPORT_HEIGHT, viewport->height); 182 183 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 184 PRI_VIEWPORT_X_START, viewport->x, 185 PRI_VIEWPORT_Y_START, viewport->y); 186 187 /*for stereo*/ 188 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 189 SEC_VIEWPORT_WIDTH, viewport->width, 190 SEC_VIEWPORT_HEIGHT, viewport->height); 191 192 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 193 SEC_VIEWPORT_X_START, viewport->x, 194 SEC_VIEWPORT_Y_START, viewport->y); 195 196 /* 197 * Work around for underflow issue with NV12 + rIOMMU translation 198 * + immediate flip. This will cause hubp underflow, but will not 199 * be user visible since underflow is in blank region 200 * Disable w/a when rotated 180 degrees, causes vertical chroma offset 201 */ 202 patched_viewport_height = viewport_c->height; 203 if (debug->nv12_iflip_vm_wa && viewport_c->height > 512 && 204 rotation != ROTATION_ANGLE_180) { 205 int pte_row_height = 0; 206 int pte_rows = 0; 207 208 REG_GET(DCHUBP_REQ_SIZE_CONFIG_C, 209 PTE_ROW_HEIGHT_LINEAR_C, &pte_row_height); 210 211 pte_row_height = 1 << (pte_row_height + 3); 212 pte_rows = (viewport_c->height / pte_row_height) + 1; 213 patched_viewport_height = pte_rows * pte_row_height + 1; 214 } 215 216 217 /* DC supports NV12 only at the moment */ 218 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 219 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 220 PRI_VIEWPORT_HEIGHT_C, patched_viewport_height); 221 222 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 223 PRI_VIEWPORT_X_START_C, viewport_c->x, 224 PRI_VIEWPORT_Y_START_C, viewport_c->y); 225 226 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 227 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 228 SEC_VIEWPORT_HEIGHT_C, patched_viewport_height); 229 230 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 231 SEC_VIEWPORT_X_START_C, viewport_c->x, 232 SEC_VIEWPORT_Y_START_C, viewport_c->y); 233 } 234 235 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 236 struct vm_system_aperture_param *apt) 237 { 238 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 239 240 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 241 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 242 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 243 244 // The format of default addr is 48:12 of the 48 bit addr 245 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 246 247 // The format of high/low are 48:18 of the 48 bit addr 248 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 249 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 250 251 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 252 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 253 254 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 255 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 256 257 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 258 ENABLE_L1_TLB, 1, 259 SYSTEM_ACCESS_MODE, 0x3); 260 } 261 262 void hubp21_validate_dml_output(struct hubp *hubp, 263 struct dc_context *ctx, 264 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 265 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 266 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 267 { 268 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 269 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 270 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 271 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 272 DC_LOGGER_INIT(ctx->logger); 273 DC_LOG_DEBUG("DML Validation | Running Validation"); 274 275 /* Requester - Per hubp */ 276 REG_GET(HUBPRET_CONTROL, 277 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 278 REG_GET_4(DCN_EXPANSION_MODE, 279 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 280 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 281 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 282 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 283 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 284 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 285 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 286 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 287 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 288 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 289 VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 290 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 291 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 292 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 293 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 294 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 295 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 296 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 297 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 298 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 299 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 300 301 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 302 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 303 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 304 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 305 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 306 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 307 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 308 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 309 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 310 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 311 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 312 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 313 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 314 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 315 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 316 317 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 318 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 319 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 320 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 321 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 322 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 323 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 324 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 325 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 326 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 327 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 328 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 329 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 330 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 331 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 332 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 333 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 334 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 335 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 336 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 337 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 338 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 339 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 340 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 341 342 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 343 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 344 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 345 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 346 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 347 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 348 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 349 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 350 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 351 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 352 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 353 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 354 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 355 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 356 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 357 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 358 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 359 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 360 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 361 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 362 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 363 364 365 /* DLG - Per hubp */ 366 REG_GET_2(BLANK_OFFSET_0, 367 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 368 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 369 REG_GET(BLANK_OFFSET_1, 370 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 371 REG_GET(DST_DIMENSIONS, 372 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 373 REG_GET_2(DST_AFTER_SCALER, 374 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 375 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 376 REG_GET(REF_FREQ_TO_PIX_FREQ, 377 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 378 379 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 380 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 381 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 382 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 383 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 384 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 385 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 386 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 387 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 388 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 389 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 390 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 391 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 392 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 393 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 394 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 395 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 396 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 397 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 398 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 399 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 400 401 /* DLG - Per luma/chroma */ 402 REG_GET(VBLANK_PARAMETERS_1, 403 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 404 if (REG(NOM_PARAMETERS_0)) 405 REG_GET(NOM_PARAMETERS_0, 406 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 407 if (REG(NOM_PARAMETERS_1)) 408 REG_GET(NOM_PARAMETERS_1, 409 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 410 REG_GET(NOM_PARAMETERS_4, 411 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 412 REG_GET(NOM_PARAMETERS_5, 413 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 414 REG_GET_2(PER_LINE_DELIVERY, 415 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 416 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 417 REG_GET_2(PER_LINE_DELIVERY_PRE, 418 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 419 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 420 REG_GET(VBLANK_PARAMETERS_2, 421 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 422 if (REG(NOM_PARAMETERS_2)) 423 REG_GET(NOM_PARAMETERS_2, 424 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 425 if (REG(NOM_PARAMETERS_3)) 426 REG_GET(NOM_PARAMETERS_3, 427 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 428 REG_GET(NOM_PARAMETERS_6, 429 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 430 REG_GET(NOM_PARAMETERS_7, 431 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 432 REG_GET(VBLANK_PARAMETERS_3, 433 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 434 REG_GET(VBLANK_PARAMETERS_4, 435 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 436 437 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 438 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 439 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 440 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 441 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 442 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 443 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 444 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 445 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 446 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 447 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 448 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 449 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 450 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 451 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 452 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 453 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 454 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 455 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 456 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 457 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 458 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 459 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 460 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 461 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 462 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 463 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 464 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 465 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 466 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 467 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 468 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 469 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 470 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 471 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 472 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 473 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 474 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 475 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 476 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 477 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 478 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 479 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 480 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 481 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 482 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 483 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 484 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 485 486 /* TTU - per hubp */ 487 REG_GET_2(DCN_TTU_QOS_WM, 488 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 489 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 490 491 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 492 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 493 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 494 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 495 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 496 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 497 498 /* TTU - per luma/chroma */ 499 /* Assumed surf0 is luma and 1 is chroma */ 500 REG_GET_3(DCN_SURF0_TTU_CNTL0, 501 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 502 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 503 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 504 REG_GET_3(DCN_SURF1_TTU_CNTL0, 505 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 506 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 507 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 508 REG_GET_3(DCN_CUR0_TTU_CNTL0, 509 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 510 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 511 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 512 REG_GET(FLIP_PARAMETERS_1, 513 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 514 REG_GET(DCN_CUR0_TTU_CNTL1, 515 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 516 REG_GET(DCN_CUR1_TTU_CNTL1, 517 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 518 REG_GET(DCN_SURF0_TTU_CNTL1, 519 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 520 REG_GET(DCN_SURF1_TTU_CNTL1, 521 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 522 523 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 524 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 525 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 526 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 527 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 528 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 529 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 530 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 531 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 532 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 533 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 534 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 535 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 536 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 537 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 538 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 539 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 540 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 541 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 542 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 543 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 544 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 545 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 546 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 547 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 548 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 549 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 550 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 551 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 552 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 553 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 554 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 555 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 556 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 557 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 558 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 559 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 560 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 561 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 562 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 563 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 564 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 565 566 /* Host VM deadline regs */ 567 REG_GET(VBLANK_PARAMETERS_5, 568 REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 569 REG_GET(VBLANK_PARAMETERS_6, 570 REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 571 REG_GET(FLIP_PARAMETERS_3, 572 REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 573 REG_GET(FLIP_PARAMETERS_4, 574 REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 575 REG_GET(FLIP_PARAMETERS_5, 576 REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 577 REG_GET(FLIP_PARAMETERS_6, 578 REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 579 REG_GET(FLIP_PARAMETERS_2, 580 REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 581 582 if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 583 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 584 dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 585 if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 586 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 587 dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 588 if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 589 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 590 dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 591 if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 592 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 593 dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 594 if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 595 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 596 dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 597 if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 598 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 599 dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 600 if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 601 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 602 dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 603 } 604 605 void hubp21_init(struct hubp *hubp) 606 { 607 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 608 // This is a chicken bit to enable the ECO fix. 609 610 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 611 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 612 REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 613 } 614 static struct hubp_funcs dcn21_hubp_funcs = { 615 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 616 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 617 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 618 .hubp_program_surface_config = hubp1_program_surface_config, 619 .hubp_is_flip_pending = hubp1_is_flip_pending, 620 .hubp_setup = hubp21_setup, 621 .hubp_setup_interdependent = hubp2_setup_interdependent, 622 .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 623 .set_blank = hubp1_set_blank, 624 .dcc_control = hubp1_dcc_control, 625 .mem_program_viewport = hubp21_set_viewport, 626 .set_cursor_attributes = hubp2_cursor_set_attributes, 627 .set_cursor_position = hubp1_cursor_set_position, 628 .hubp_clk_cntl = hubp1_clk_cntl, 629 .hubp_vtg_sel = hubp1_vtg_sel, 630 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 631 .dmdata_load = hubp2_dmdata_load, 632 .dmdata_status_done = hubp2_dmdata_status_done, 633 .hubp_read_state = hubp1_read_state, 634 .hubp_clear_underflow = hubp1_clear_underflow, 635 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 636 .hubp_init = hubp21_init, 637 .validate_dml_output = hubp21_validate_dml_output, 638 }; 639 640 bool hubp21_construct( 641 struct dcn21_hubp *hubp21, 642 struct dc_context *ctx, 643 uint32_t inst, 644 const struct dcn_hubp2_registers *hubp_regs, 645 const struct dcn_hubp2_shift *hubp_shift, 646 const struct dcn_hubp2_mask *hubp_mask) 647 { 648 hubp21->base.funcs = &dcn21_hubp_funcs; 649 hubp21->base.ctx = ctx; 650 hubp21->hubp_regs = hubp_regs; 651 hubp21->hubp_shift = hubp_shift; 652 hubp21->hubp_mask = hubp_mask; 653 hubp21->base.inst = inst; 654 hubp21->base.opp_id = OPP_ID_INVALID; 655 hubp21->base.mpcc_id = 0xf; 656 657 return true; 658 } 659