Revision tags: v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6 |
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#
aadeb608 |
| 28-Mar-2019 |
David Francis <David.Francis@amd.com> |
Revert "drm/amd/display: skip dsc config for navi10 bring up"
This reverts commit 9e14d4f17e23ce46d346a6a22a295b4a65b9d918.
optc dsc config was causing warnings due to missing register definitions.
Revert "drm/amd/display: skip dsc config for navi10 bring up"
This reverts commit 9e14d4f17e23ce46d346a6a22a295b4a65b9d918.
optc dsc config was causing warnings due to missing register definitions. With the registers restored, the function can be re-enabled
The reverted commit also disabled sanity checks and dsc power gating. The sanity check warnings are not associated with dsc, and power gating on dsc still has an issue on non-dsc monitors where the dsc hardware block is never init and so cannot respond to power gating requests. Therefore, those are left as is
Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2b162fd3 |
| 19-Jul-2019 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: update optc odm interface for more than 2 opps
Current optc odm interface only accepts 2 opps, we need to expand this to allow 4 to 1 odm combine.
Signed-off-by: Dmytro Laktyushkin
drm/amd/display: update optc odm interface for more than 2 opps
Current optc odm interface only accepts 2 opps, we need to expand this to allow 4 to 1 odm combine.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5ec43eda |
| 17-Jul-2019 |
Martin Leung <martin.leung@amd.com> |
drm/amd/display: enabling seamless boot sequence for dcn2
[Why] Seamless boot (building SW state inheriting BIOS-initialized timing) was enabled on DCN2, including fixes
[How] Includes fixes for MP
drm/amd/display: enabling seamless boot sequence for dcn2
[Why] Seamless boot (building SW state inheriting BIOS-initialized timing) was enabled on DCN2, including fixes
[How] Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/ Pixel clock.
This is part 2 of 2 for seamless boot NV10
Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7e647296 |
| 21-Jun-2019 |
Fatemeh Darbehani <fatemeh.darbehani@amd.com> |
drm/amd/display: Change min_h_sync_width from 8 to 4
[Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which
drm/amd/display: Change min_h_sync_width from 8 to 4
[Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which eventually will result in wrong set mode. This was set to 8 as per HW team's request for no valid reason.
[How] Changing min_h_sync_width to 4 will let us validate timing for preffered mode and light up the headset. This change was made to Vega 10 before for a similar issue.
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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09fc26c1 |
| 21-Jun-2019 |
Fatemeh Darbehani <fatemeh.darbehani@amd.com> |
drm/amd/display: Change min_h_sync_width from 8 to 4
[Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which
drm/amd/display: Change min_h_sync_width from 8 to 4
[Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which eventually will result in wrong set mode. This was set to 8 as per HW team's request for no valid reason.
[How] Changing min_h_sync_width to 4 will let us validate timing for preffered mode and light up the headset. This change was made to Vega 10 before for a similar issue.
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ce768985 |
| 18-Apr-2019 |
Nikola Cornij <nikola.cornij@amd.com> |
drm/amd/display: Do a reg update instead of set when writing ODM color format
[why] If a set is done, DSC settings are zeroed out, leading to no DSC for the modes that require ODM, such as 8k60.
Th
drm/amd/display: Do a reg update instead of set when writing ODM color format
[why] If a set is done, DSC settings are zeroed out, leading to no DSC for the modes that require ODM, such as 8k60.
This was a regression introduced by 5a4f26295176bbfc776c75aaf0f6dd8ccf806958.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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fbc9ca67 |
| 09-Apr-2019 |
Ilya Bakoulin <Ilya.Bakoulin@amd.com> |
drm/amd/display: Fix ODM combine data format
[Why] OPTC data format was left at its default value (444) when enabling ODM combine. This caused issues with FPGA capture.
[How] Write the OPTC_DATA_FO
drm/amd/display: Fix ODM combine data format
[Why] OPTC data format was left at its default value (444) when enabling ODM combine. This caused issues with FPGA capture.
[How] Write the OPTC_DATA_FORMAT field when enabling ODM combine.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1 |
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6c5be4ac |
| 05-Mar-2019 |
Wenjing Liu <Wenjing.Liu@amd.com> |
drm/amd/display: add global master update lock for DCN2
[why] when an update programming sequence requires both front end and back end pipe to be updated synchronously, a global update lock needs to
drm/amd/display: add global master update lock for DCN2
[why] when an update programming sequence requires both front end and back end pipe to be updated synchronously, a global update lock needs to be set to ensure that we don't get a frame with only front end update but not the back end update.
[how] setup global lock parameters on enable_stream_timing. enable global lock when pipe_control_lock_global is called. disable global lock when pipe_control_lock is called.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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db5378c1 |
| 28-Mar-2019 |
Wenjing Liu <Wenjing.Liu@amd.com> |
drm/amd/display: isolate global double buffer lock programming
[why] Global optic double buffer lock is currently disabled due to incorrect programming sequence that affects non global lock.
[how]
drm/amd/display: isolate global double buffer lock programming
[why] Global optic double buffer lock is currently disabled due to incorrect programming sequence that affects non global lock.
[how] Isolate global lock programming sequence out of non global lock programming sequence, so it can be enabled without affecting non global lock.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9e14d4f1 |
| 13-Mar-2019 |
hersen wu <hersenxs.wu@amd.com> |
drm/amd/display: skip dsc config for navi10 bring up
[why] we meet a bug when program dsc register even dsc mode is not enabled. disable dsc config for now. we will re-visit this issue.
Signed-off-
drm/amd/display: skip dsc config for navi10 bring up
[why] we meet a bug when program dsc register even dsc mode is not enabled. disable dsc config for now. we will re-visit this issue.
Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ae8f4258 |
| 23-Apr-2019 |
Eryk Brol <eryk.brol@amd.com> |
drm/amd/display: Ensure DRR triggers in BP
[Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until
drm/amd/display: Ensure DRR triggers in BP
[Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP.
[How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete
Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3972c350 |
| 29-Apr-2019 |
Joshua Aberback <joshua.aberback@amd.com> |
drm/amd/display: Program VTG params after programming Global Sync for DCN2
[Why] VTG has a parameter FP2, which is defined as: if VSTARTUP is before VSYNC: FP2 = number of lines in betwe
drm/amd/display: Program VTG params after programming Global Sync for DCN2
[Why] VTG has a parameter FP2, which is defined as: if VSTARTUP is before VSYNC: FP2 = number of lines in between VSTARTUP and VSYNC else FP2 = 0 Currently, FP2 is only programmed during "program_timing". However, the position of VSTARTUP is affected by the prefetching requirements on all pipes, so the position might change when we do memory request control on another pipe, so we need to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP.
[How] - refactor VTG_CONTROL programming into a new function "set_vtg_params" - call it after calling "program_global_sync" - make sure it's called after because it relies on the cached dlg params
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.19.27, v5.0, v4.19.26 |
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97bda032 |
| 25-Feb-2019 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Add DSC support for Navi (v2)
Add support for DCN2 DSC (Display Stream Compression)
HW Blocks:
+--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +----
drm/amd/display: Add DSC support for Navi (v2)
Add support for DCN2 DSC (Display Stream Compression)
HW Blocks:
+--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+
v2: rebase (Alex)
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.19.25 |
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2d78b3a1 |
| 22-Feb-2019 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Add DCN2 OPTC
Add support for programming the DCN2 OPTC (Output Timing Controller)
HW Blocks:
+--------+ | OPTC | +--------+ | v +--------+
drm/amd/display: Add DCN2 OPTC
Add support for programming the DCN2 OPTC (Output Timing Controller)
HW Blocks:
+--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dcc8c5fb |
| 19-Jul-2021 |
Bing Guo <bing.guo@amd.com> |
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X [ Upstream commit 06050a0f01dbac2ca33145ef19a72041206ea983 ] Why: In DCN2x, HW doesn't automatically divide MASTER_
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X [ Upstream commit 06050a0f01dbac2ca33145ef19a72041206ea983 ] Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined. How: Set MASTER_UPDATE_LOCK_DB_X to the value that is adjusted by the number of pipes ODM Combined. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bing Guo <bing.guo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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dd7a595a |
| 16-Sep-2020 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: Fix OPTC_DATA_FORMAT programming This should be programmed with timing rather than with odm. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acke
drm/amd/display: Fix OPTC_DATA_FORMAT programming This should be programmed with timing rather than with odm. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.30, v5.4.29 |
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a8665946 |
| 31-Mar-2020 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: add optc get crc support for timings with ODM/DSC [why] Optc needs to know if timing is enabled with ODM or DSC before computing crc. Otherwise value computed will
drm/amd/display: add optc get crc support for timings with ODM/DSC [why] Optc needs to know if timing is enabled with ODM or DSC before computing crc. Otherwise value computed will be inaccurate. Before this change, the CRC computed without ODM is not equal to the CRC computed with ODM for the same timing. This is unexpected as we are driving the same timing despite of the underlaying hardware setup to achieve it. This is caused by missing hardware programming sequence to support it. [how] Add the new programming sequence based on hardware guide. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3 |
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830806c5 |
| 04-Dec-2019 |
Aric Cyr <aric.cyr@amd.com> |
drm/amd/display: Fix manual trigger source for DCN2 Fix manual trigger source correctly be TRIGA for DCN2 rather than MANUAL_FLOW. Signed-off-by: Aric Cyr <aric.cyr@amd.com>
drm/amd/display: Fix manual trigger source for DCN2 Fix manual trigger source correctly be TRIGA for DCN2 rather than MANUAL_FLOW. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.15, v5.4.2, v5.4.1, v5.3.14 |
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ec5b356c |
| 26-Nov-2019 |
Nikola Cornij <nikola.cornij@amd.com> |
drm/amd/display: Map ODM memory correctly when doing ODM combine [why] Up to 4 ODM memory pieces are required per ODM combine and cannot overlap, i.e. each ODM "session" has to use i
drm/amd/display: Map ODM memory correctly when doing ODM combine [why] Up to 4 ODM memory pieces are required per ODM combine and cannot overlap, i.e. each ODM "session" has to use its own memory pieces. The ODM-memory mapping is currently broken for generic case. The maximum number of memory pieces is ASIC-dependent, but it's always big enough to satisfy maximum number of ODM combines. Memory pieces are mapped as a bit-map, i.e. one memory piece corresponds to one bit. The OPTC doing ODM needs to select memory pieces by setting the corresponding bits, making sure there's no overlap with other OPTC instances that might be doing ODM. The current mapping works only for OPTC instance indexes smaller than 3. For instance indexes 3 and up it practically maps no ODM memory, causing black, gray or white screen in display configs that include ODM on OPTC instance 3 or up. [how] Statically map two unique ODM memory pieces for each OPTC instance and piece them together when programming ODM combine mode. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4, v5.3.13, v5.3.12 |
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ad51b4ac |
| 18-Nov-2019 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Extend DMCUB offload testing into dcn20/21 [Why] To quickly validate whether DMCUB is running and accepting commands for offload testing we want to intercept a commo
drm/amd/display: Extend DMCUB offload testing into dcn20/21 [Why] To quickly validate whether DMCUB is running and accepting commands for offload testing we want to intercept a common sequence as part of modeset programming. [How] OTG enable will cause the most impact in terms of golden register changes and it's a single register write. This approach was previously done in dcn10 code when it was shared with dcn20 but it wasn't ported over to the dcn20 code. Port over start, execute and wait sequence into dcn20_optc. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.11, v5.3.10, v5.3.9 |
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#
78c77382 |
| 29-Oct-2019 |
Anthony Koo <Anthony.Koo@amd.com> |
drm/amd/display: cleanup of function pointer tables [Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions [How] 1.
drm/amd/display: cleanup of function pointer tables [Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions [How] 1. Make function pointer table init in its own init.c file 2. Remove other scenarios in hwseq.c file that need to include headers of other DCN versions. (If needed, it should have been done via the function pointers) Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1da37801 |
| 06-Nov-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED [Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED [Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1 |
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#
93c2340b |
| 17-Sep-2019 |
Martin Leung <martin.leung@amd.com> |
drm/amd/display: add more checks to validate seamless boot timing [why] we found using an active DP to HDMI panel that we weren't validating dp_pixel_format and hardware timing v_fro
drm/amd/display: add more checks to validate seamless boot timing [why] we found using an active DP to HDMI panel that we weren't validating dp_pixel_format and hardware timing v_front_porch, causing screen to blank and/or corrupt while attempting a seamless boot. [how] added checks during dc_validate_seamless_boot_timing for these values Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11 |
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#
2fef0faa |
| 28-Aug-2019 |
Nikola Cornij <nikola.cornij@amd.com> |
drm/amd/display: Set number of pipes to 1 if the second pipe was disabled [why] Some ODM-related register settings are inconsistently updated by VBIOS, causing the state in DC to be
drm/amd/display: Set number of pipes to 1 if the second pipe was disabled [why] Some ODM-related register settings are inconsistently updated by VBIOS, causing the state in DC to be invalid, which would then end up crashing in certain use-cases (such as disable/enable device). [how] Check the enabled status of the second pipe when determining the number of OPTC sources. If the second pipe is disabled, set the number of sources to 1 regardless of other settings (that may not be updated correctly). Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5 |
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4c3cfe14 |
| 23-May-2019 |
David Francis <David.Francis@amd.com> |
Revert "drm/amd/display: add global master update lock for DCN2" This reverts commit 6c5be4ac630805d3a3b20157a0c6421ef815fe78. This commit was accidentally promoted twice S
Revert "drm/amd/display: add global master update lock for DCN2" This reverts commit 6c5be4ac630805d3a3b20157a0c6421ef815fe78. This commit was accidentally promoted twice Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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