#
bebc0762 |
| 23-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to new amdgpu_nbio structure
no functional change, just switch to new structures
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher
drm/amdgpu: switch to new amdgpu_nbio structure
no functional change, just switch to new structures
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
989b6a05 |
| 10-Jul-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance
add vcn nbio doorbell range setting for 2nd vcn instance
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.
drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance
add vcn nbio doorbell range setting for 2nd vcn instance
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
39a5053f |
| 09-Jul-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add vcn doorbell range function to nbio7.4 (v2)
To setup the aperture for VCN2.5
v2: setup vcn doorbells in vcn2.5 hw_init (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by:
drm/amdgpu: add vcn doorbell range function to nbio7.4 (v2)
To setup the aperture for VCN2.5
v2: setup vcn doorbells in vcn2.5 hw_init (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9 |
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#
3d81f67a |
| 19-Sep-2018 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: support sdma 2~7 doorbell range register offset
Update the doorbell range registers to support additional SDMA rings.
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Ha
drm/amdgpu: support sdma 2~7 doorbell range register offset
Update the doorbell range registers to support additional SDMA rings.
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0fe6a7b4 |
| 10-Sep-2018 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: support hdp flush for more sdma instances
The bit RSVD_ENG0 to RSVD_ENG5 in GPU_HDP_FLUSH_REQ/GPU_HDP_FLUSH_DONE can be leveraged for sdma instance 2~7 to poll register/memory.
Signed-o
drm/amdgpu: support hdp flush for more sdma instances
The bit RSVD_ENG0 to RSVD_ENG5 in GPU_HDP_FLUSH_REQ/GPU_HDP_FLUSH_DONE can be leveraged for sdma instance 2~7 to poll register/memory.
Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
88807dc8 |
| 04-Apr-2019 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Remap hdp coherency registers
Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL to an empty page in mmio space. We will later map this page to process space so applicat
drm/amdgpu: Remap hdp coherency registers
Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL to an empty page in mmio space. We will later map this page to process space so application can flush hdp. This can't be done properly at those registers' original location because it will expose more than desired registers to process space.
v2: Use explicit register hole location v3: Moved remapped hdp registers into adev struct v4: Use more generic name for remapped page Expose register offset in kfd_ioctl.h v5: Move hdp register remap function to nbio ip function v6: Fixed operator precedence issue and other bugs
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b49c197 |
| 12-Feb-2019 |
Colin Ian King <colin.king@canonical.com> |
drm/amdgpu: fix several indentation issues
There are several statements that are incorrectly indented. Fix these.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Colin Ian Ki
drm/amdgpu: fix several indentation issues
There are several statements that are incorrectly indented. Fix these.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
12292519 |
| 30-Jan-2019 |
Jay Cornwall <Jay.Cornwall@amd.com> |
drm/amdgpu: Implement doorbell self-ring for NBIO 7.4
Fixes doorbell reflection on Vega20.
Change-Id: I0495139d160a9032dff5977289b1eec11c16f781 Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Re
drm/amdgpu: Implement doorbell self-ring for NBIO 7.4
Fixes doorbell reflection on Vega20.
Change-Id: I0495139d160a9032dff5977289b1eec11c16f781 Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8987e2e2 |
| 17-Dec-2018 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Fix sdma doorbell range setting
Different ASIC has different SDMA queue number so different SDMA doorbell range. Introduce an extra parameter to sdma_doorbell_range function and set sdma
drm/amdgpu: Fix sdma doorbell range setting
Different ASIC has different SDMA queue number so different SDMA doorbell range. Introduce an extra parameter to sdma_doorbell_range function and set sdma doorbell range correctly.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a0bb79e2 |
| 07-Jan-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add NBIO SMN headers v2
We need these offsets for PCIE perf counters, so include them as well as the the previously-used defines from the nbio_*.c files
v2: Return NBIF definitions back
drm/amdgpu: Add NBIO SMN headers v2
We need these offsets for PCIE perf counters, so include them as well as the the previously-used defines from the nbio_*.c files
v2: Return NBIF definitions back to previous files
Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e01f2d41 |
| 19-Dec-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nbio7.4: add hw bug workaround for vega20
Configure PCIE_CI_CNTL to work around a hw bug that affects some multi-GPU compute workloads.
Acked-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-b
drm/amdgpu/nbio7.4: add hw bug workaround for vega20
Configure PCIE_CI_CNTL to work around a hw bug that affects some multi-GPU compute workloads.
Acked-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17 |
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#
a2045ee6 |
| 26-Apr-2018 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: add vega20 sriov capability detection
Add sriov capability detection for vega20, then can check if device is virtual device.
Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by:
drm/amdgpu: add vega20 sriov capability detection
Add sriov capability detection for vega20, then can check if device is virtual device.
Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
52de2ea7 |
| 21-Aug-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix sdma doorbell range setting
Use the old doorbell range setting until the driver is able to support more sdma queues.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawkin
drm/amdgpu: fix sdma doorbell range setting
Use the old doorbell range setting until the driver is able to support more sdma queues.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.16 |
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#
fe3c9489 |
| 23-Mar-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Add nbio 7.4 support for vega20 (v3)
Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20.
v2: fix doorbell range for sdma (Alex) v3: squ
drm/amdgpu: Add nbio 7.4 support for vega20 (v3)
Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20.
v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f75e94d8 |
| 04-Aug-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: bypass querying ras error count registers Once ras recovery is issued by ras sync flood interrupt or ras controller interrupt, add this guard to bypass or execute ras err
drm/amdgpu: bypass querying ras error count registers Once ras recovery is issued by ras sync flood interrupt or ras controller interrupt, add this guard to bypass or execute ras error count register harvest of all IPs. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6952e99c |
| 10-Apr-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: refine ras related message print Prefix ras related kernel message logging with PCI device info by replacing DRM_INFO/WARN/ERROR with dev_info/warn/err. This can clearly
drm/amdgpu: refine ras related message print Prefix ras related kernel message logging with PCI device info by replacing DRM_INFO/WARN/ERROR with dev_info/warn/err. This can clearly tell user about GPU device information where ras is. And add some other ras message printing to make it more clear and friendly as well. Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b635ae87 |
| 18-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: ih doorbell size of range changed for nbio v7.4 [Why] nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per register. [How] Change ih doorbel
drm/amdgpu: ih doorbell size of range changed for nbio v7.4 [Why] nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per register. [How] Change ih doorbell size from 2 to 4. This means two Dwords per ring. Current configuration uses two ih rings. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3aa0115d |
| 04-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup all virtualization detection routine we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE
drm/amdgpu: cleanup all virtualization detection routine we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3cd4f618 |
| 13-Feb-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: record non-zero error counter info in NBIO before resetting GPU When NBIO's RAS error happens, before trigging GPU reset, it's needed to record error counter information, whi
drm/amdgpu: record non-zero error counter info in NBIO before resetting GPU When NBIO's RAS error happens, before trigging GPU reset, it's needed to record error counter information, which can correct the error counter value missed issue when reading from debugfs. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8831fa6e |
| 24-Dec-2019 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: simplify function return logic Former return logic is redundant. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-b
drm/amdgpu: simplify function return logic Former return logic is redundant. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
61934624 |
| 13-Dec-2019 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: drop useless BACO arg in amdgpu_ras_reset_gpu BACO reset mode strategy is determined by latter func when calling amdgpu_ras_reset_gpu. So not to confuse audience, drop it
drm/amdgpu: drop useless BACO arg in amdgpu_ras_reset_gpu BACO reset mode strategy is determined by latter func when calling amdgpu_ras_reset_gpu. So not to confuse audience, drop it. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5c39d600 |
| 22-Nov-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: clear uncorrectable parity error status bit This should be cleared during every nbif uncorrectable error cleanup work. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-
drm/amdgpu: clear uncorrectable parity error status bit This should be cleared during every nbif uncorrectable error cleanup work. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
28f87950 |
| 22-Nov-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: clear ras controller status registers when interrupt occurs To fix issue that ras controller interrupt cannot be triggered anymore after one time nbif uncorrectable error. An
drm/amdgpu: clear ras controller status registers when interrupt occurs To fix issue that ras controller interrupt cannot be triggered anymore after one time nbif uncorrectable error. And error count is stored in nbif ras object for query. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.11, v5.3.10, v5.3.9, v5.3.8 |
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#
4a2d9356 |
| 21-Oct-2019 |
Le Ma <Le.Ma@amd.com> |
drm/amdgpu: remove ras global recovery handling from ras_controller_int handler v2: add notification when ras controller interrupt generates Signed-off-by: Le Ma <Le.Ma@amd.com>
drm/amdgpu: remove ras global recovery handling from ras_controller_int handler v2: add notification when ras controller interrupt generates Signed-off-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.7, v5.3.6 |
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#
956f6705 |
| 11-Oct-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu/soc15: disable doorbell interrupt as part of BACO entry sequence Workaround to make RAS recovery work in BACO reset. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by:
drm/amdgpu/soc15: disable doorbell interrupt as part of BACO entry sequence Workaround to make RAS recovery work in BACO reset. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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