1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_4.h" 26 27 #include "nbio/nbio_7_4_offset.h" 28 #include "nbio/nbio_7_4_sh_mask.h" 29 #include "nbio/nbio_7_4_0_smn.h" 30 31 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 32 33 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 34 { 35 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 36 37 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 38 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 39 40 return tmp; 41 } 42 43 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 44 { 45 if (enable) 46 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 47 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 48 else 49 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 50 } 51 52 static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev, 53 struct amdgpu_ring *ring) 54 { 55 if (!ring || !ring->funcs->emit_wreg) 56 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 57 else 58 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 59 NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0); 60 } 61 62 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 63 { 64 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 65 } 66 67 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 68 bool use_doorbell, int doorbell_index) 69 { 70 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 71 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 72 73 u32 doorbell_range = RREG32(reg); 74 75 if (use_doorbell) { 76 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 77 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); 78 } else 79 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 80 81 WREG32(reg, doorbell_range); 82 } 83 84 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 85 bool enable) 86 { 87 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 88 } 89 90 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 91 bool enable) 92 { 93 94 } 95 96 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 97 bool use_doorbell, int doorbell_index) 98 { 99 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 100 101 if (use_doorbell) { 102 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 103 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 104 } else 105 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 106 107 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 108 } 109 110 111 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 112 bool enable) 113 { 114 //TODO: Add support for v7.4 115 } 116 117 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 118 bool enable) 119 { 120 uint32_t def, data; 121 122 def = data = RREG32_PCIE(smnPCIE_CNTL2); 123 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 124 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 125 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 126 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 127 } else { 128 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 129 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 130 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 131 } 132 133 if (def != data) 134 WREG32_PCIE(smnPCIE_CNTL2, data); 135 } 136 137 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 138 u32 *flags) 139 { 140 int data; 141 142 /* AMD_CG_SUPPORT_BIF_MGCG */ 143 data = RREG32_PCIE(smnCPM_CONTROL); 144 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 145 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 146 147 /* AMD_CG_SUPPORT_BIF_LS */ 148 data = RREG32_PCIE(smnPCIE_CNTL2); 149 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 150 *flags |= AMD_CG_SUPPORT_BIF_LS; 151 } 152 153 static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 154 { 155 u32 interrupt_cntl; 156 157 /* setup interrupt control */ 158 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 159 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 160 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 161 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 162 */ 163 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 164 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 165 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 166 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 167 } 168 169 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 170 { 171 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 172 } 173 174 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 175 { 176 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 177 } 178 179 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 180 { 181 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 182 } 183 184 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 185 { 186 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 187 } 188 189 static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 190 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 191 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 192 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 193 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 194 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 195 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 196 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 197 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 198 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 199 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 200 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 201 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 202 }; 203 204 static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) 205 { 206 uint32_t reg; 207 208 reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); 209 if (reg & 1) 210 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 211 212 if (reg & 0x80000000) 213 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 214 215 if (!reg) { 216 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 217 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 218 } 219 } 220 221 static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 222 { 223 uint32_t def, data; 224 225 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); 226 data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); 227 228 if (def != data) 229 WREG32_PCIE(smnPCIE_CI_CNTL, data); 230 } 231 232 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 233 .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg, 234 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 235 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 236 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 237 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 238 .get_rev_id = nbio_v7_4_get_rev_id, 239 .mc_access_enable = nbio_v7_4_mc_access_enable, 240 .hdp_flush = nbio_v7_4_hdp_flush, 241 .get_memsize = nbio_v7_4_get_memsize, 242 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 243 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 244 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 245 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 246 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 247 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 248 .get_clockgating_state = nbio_v7_4_get_clockgating_state, 249 .ih_control = nbio_v7_4_ih_control, 250 .init_registers = nbio_v7_4_init_registers, 251 .detect_hw_virt = nbio_v7_4_detect_hw_virt, 252 }; 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