1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_4.h" 26 27 #include "nbio/nbio_7_4_offset.h" 28 #include "nbio/nbio_7_4_sh_mask.h" 29 30 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 31 32 #define smnCPM_CONTROL 0x11180460 33 #define smnPCIE_CNTL2 0x11180070 34 35 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 36 { 37 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 38 39 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 40 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 41 42 return tmp; 43 } 44 45 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 46 { 47 if (enable) 48 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 49 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 50 else 51 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 52 } 53 54 static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev, 55 struct amdgpu_ring *ring) 56 { 57 if (!ring || !ring->funcs->emit_wreg) 58 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 59 else 60 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 61 NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0); 62 } 63 64 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 65 { 66 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 67 } 68 69 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 70 bool use_doorbell, int doorbell_index) 71 { 72 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 73 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 74 75 u32 doorbell_range = RREG32(reg); 76 77 if (use_doorbell) { 78 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 79 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); 80 } else 81 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 82 83 WREG32(reg, doorbell_range); 84 } 85 86 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 87 bool enable) 88 { 89 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 90 } 91 92 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 93 bool enable) 94 { 95 96 } 97 98 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 99 bool use_doorbell, int doorbell_index) 100 { 101 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 102 103 if (use_doorbell) { 104 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 105 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 106 } else 107 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 108 109 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 110 } 111 112 113 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 114 bool enable) 115 { 116 //TODO: Add support for v7.4 117 } 118 119 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 120 bool enable) 121 { 122 uint32_t def, data; 123 124 def = data = RREG32_PCIE(smnPCIE_CNTL2); 125 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 126 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 127 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 128 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 129 } else { 130 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 131 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 132 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 133 } 134 135 if (def != data) 136 WREG32_PCIE(smnPCIE_CNTL2, data); 137 } 138 139 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 140 u32 *flags) 141 { 142 int data; 143 144 /* AMD_CG_SUPPORT_BIF_MGCG */ 145 data = RREG32_PCIE(smnCPM_CONTROL); 146 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 147 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 148 149 /* AMD_CG_SUPPORT_BIF_LS */ 150 data = RREG32_PCIE(smnPCIE_CNTL2); 151 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 152 *flags |= AMD_CG_SUPPORT_BIF_LS; 153 } 154 155 static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 156 { 157 u32 interrupt_cntl; 158 159 /* setup interrupt control */ 160 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 161 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 162 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 163 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 164 */ 165 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 166 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 167 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 168 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 169 } 170 171 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 172 { 173 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 174 } 175 176 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 177 { 178 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 179 } 180 181 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 182 { 183 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 184 } 185 186 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 187 { 188 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 189 } 190 191 static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 192 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 193 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 194 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 195 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 196 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 197 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 198 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 199 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 200 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 201 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 202 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 203 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 204 }; 205 206 static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) 207 { 208 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 209 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 210 } 211 212 static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 213 { 214 215 } 216 217 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 218 .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg, 219 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 220 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 221 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 222 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 223 .get_rev_id = nbio_v7_4_get_rev_id, 224 .mc_access_enable = nbio_v7_4_mc_access_enable, 225 .hdp_flush = nbio_v7_4_hdp_flush, 226 .get_memsize = nbio_v7_4_get_memsize, 227 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 228 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 229 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 230 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 231 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 232 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 233 .get_clockgating_state = nbio_v7_4_get_clockgating_state, 234 .ih_control = nbio_v7_4_ih_control, 235 .init_registers = nbio_v7_4_init_registers, 236 .detect_hw_virt = nbio_v7_4_detect_hw_virt, 237 }; 238