1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/of.h> 13 14 #include "clk.h" 15 #include <dt-bindings/clock/exynos7-clk.h> 16 17 /* Register Offset definitions for CMU_TOPC (0x10570000) */ 18 #define CC_PLL_LOCK 0x0000 19 #define BUS0_PLL_LOCK 0x0004 20 #define BUS1_DPLL_LOCK 0x0008 21 #define MFC_PLL_LOCK 0x000C 22 #define AUD_PLL_LOCK 0x0010 23 #define CC_PLL_CON0 0x0100 24 #define BUS0_PLL_CON0 0x0110 25 #define BUS1_DPLL_CON0 0x0120 26 #define MFC_PLL_CON0 0x0130 27 #define AUD_PLL_CON0 0x0140 28 #define MUX_SEL_TOPC0 0x0200 29 #define MUX_SEL_TOPC1 0x0204 30 #define MUX_SEL_TOPC2 0x0208 31 #define MUX_SEL_TOPC3 0x020C 32 #define DIV_TOPC0 0x0600 33 #define DIV_TOPC1 0x0604 34 #define DIV_TOPC3 0x060C 35 #define ENABLE_ACLK_TOPC0 0x0800 36 #define ENABLE_ACLK_TOPC1 0x0804 37 #define ENABLE_SCLK_TOPC1 0x0A04 38 39 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), 41 FFACTOR(0, "ffac_topc_bus0_pll_div4", 42 "ffac_topc_bus0_pll_div2", 1, 2, 0), 43 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), 44 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), 45 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), 46 }; 47 48 /* List of parent clocks for Muxes in CMU_TOPC */ 49 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 50 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 51 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 52 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 53 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 54 55 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", 56 "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", 57 "mout_topc_mfc_pll_half" }; 58 59 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", 60 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 61 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", 62 "ffac_topc_bus1_pll_div2"}; 63 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", 64 "ffac_topc_cc_pll_div2"}; 65 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", 66 "ffac_topc_mfc_pll_div2"}; 67 68 69 PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", 70 "ffac_topc_bus0_pll_div2"}; 71 72 static unsigned long topc_clk_regs[] __initdata = { 73 CC_PLL_LOCK, 74 BUS0_PLL_LOCK, 75 BUS1_DPLL_LOCK, 76 MFC_PLL_LOCK, 77 AUD_PLL_LOCK, 78 CC_PLL_CON0, 79 BUS0_PLL_CON0, 80 BUS1_DPLL_CON0, 81 MFC_PLL_CON0, 82 AUD_PLL_CON0, 83 MUX_SEL_TOPC0, 84 MUX_SEL_TOPC1, 85 MUX_SEL_TOPC2, 86 MUX_SEL_TOPC3, 87 DIV_TOPC0, 88 DIV_TOPC1, 89 DIV_TOPC3, 90 }; 91 92 static struct samsung_mux_clock topc_mux_clks[] __initdata = { 93 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, 94 MUX_SEL_TOPC0, 0, 1), 95 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, 96 MUX_SEL_TOPC0, 4, 1), 97 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, 98 MUX_SEL_TOPC0, 8, 1), 99 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, 100 MUX_SEL_TOPC0, 12, 1), 101 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, 102 MUX_SEL_TOPC0, 16, 2), 103 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, 104 MUX_SEL_TOPC0, 20, 1), 105 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, 106 MUX_SEL_TOPC0, 24, 1), 107 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, 108 MUX_SEL_TOPC0, 28, 1), 109 110 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, 111 MUX_SEL_TOPC1, 0, 1), 112 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, 113 MUX_SEL_TOPC1, 16, 1), 114 115 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 116 117 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 118 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 119 }; 120 121 static struct samsung_div_clock topc_div_clks[] __initdata = { 122 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 123 DIV_TOPC0, 4, 4), 124 125 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 126 DIV_TOPC1, 20, 4), 127 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 128 DIV_TOPC1, 24, 4), 129 130 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", 131 DIV_TOPC3, 0, 4), 132 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", 133 DIV_TOPC3, 8, 4), 134 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", 135 DIV_TOPC3, 12, 4), 136 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", 137 DIV_TOPC3, 16, 4), 138 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", 139 DIV_TOPC3, 28, 4), 140 }; 141 142 static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { 143 PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 144 {}, 145 }; 146 147 static struct samsung_gate_clock topc_gate_clks[] __initdata = { 148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", 149 ENABLE_ACLK_TOPC0, 4, 0, 0), 150 151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 152 ENABLE_ACLK_TOPC1, 20, 0, 0), 153 154 GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", 155 ENABLE_ACLK_TOPC1, 24, 0, 0), 156 157 GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", 158 ENABLE_SCLK_TOPC1, 20, 0, 0), 159 GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", 160 ENABLE_SCLK_TOPC1, 17, 0, 0), 161 GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", 162 ENABLE_SCLK_TOPC1, 16, 0, 0), 163 GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", 164 ENABLE_SCLK_TOPC1, 13, 0, 0), 165 GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", 166 ENABLE_SCLK_TOPC1, 12, 0, 0), 167 GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", 168 ENABLE_SCLK_TOPC1, 5, 0, 0), 169 GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", 170 ENABLE_SCLK_TOPC1, 4, 0, 0), 171 GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", 172 ENABLE_SCLK_TOPC1, 1, 0, 0), 173 GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", 174 ENABLE_SCLK_TOPC1, 0, 0, 0), 175 }; 176 177 static struct samsung_pll_clock topc_pll_clks[] __initdata = { 178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 179 BUS0_PLL_CON0, NULL), 180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 181 CC_PLL_CON0, NULL), 182 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 183 BUS1_DPLL_CON0, NULL), 184 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 185 MFC_PLL_CON0, NULL), 186 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 187 AUD_PLL_CON0, pll1460x_24mhz_tbl), 188 }; 189 190 static struct samsung_cmu_info topc_cmu_info __initdata = { 191 .pll_clks = topc_pll_clks, 192 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 193 .mux_clks = topc_mux_clks, 194 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 195 .div_clks = topc_div_clks, 196 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 197 .gate_clks = topc_gate_clks, 198 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 199 .fixed_factor_clks = topc_fixed_factor_clks, 200 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 201 .nr_clk_ids = TOPC_NR_CLK, 202 .clk_regs = topc_clk_regs, 203 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 204 }; 205 206 static void __init exynos7_clk_topc_init(struct device_node *np) 207 { 208 samsung_cmu_register_one(np, &topc_cmu_info); 209 } 210 211 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 212 exynos7_clk_topc_init); 213 214 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 215 #define MUX_SEL_TOP00 0x0200 216 #define MUX_SEL_TOP01 0x0204 217 #define MUX_SEL_TOP03 0x020C 218 #define MUX_SEL_TOP0_PERIC0 0x0230 219 #define MUX_SEL_TOP0_PERIC1 0x0234 220 #define MUX_SEL_TOP0_PERIC2 0x0238 221 #define MUX_SEL_TOP0_PERIC3 0x023C 222 #define DIV_TOP03 0x060C 223 #define DIV_TOP0_PERIC0 0x0630 224 #define DIV_TOP0_PERIC1 0x0634 225 #define DIV_TOP0_PERIC2 0x0638 226 #define DIV_TOP0_PERIC3 0x063C 227 #define ENABLE_ACLK_TOP03 0x080C 228 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 229 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 230 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 231 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 232 233 /* List of parent clocks for Muxes in CMU_TOP0 */ 234 PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" }; 235 PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" }; 236 PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" }; 237 PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" }; 238 PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" }; 239 240 PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user", 241 "ffac_top0_bus0_pll_div2"}; 242 PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user", 243 "ffac_top0_bus1_pll_div2"}; 244 PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user", 245 "ffac_top0_cc_pll_div2"}; 246 PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user", 247 "ffac_top0_mfc_pll_div2"}; 248 249 PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half", 250 "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half", 251 "mout_top0_mfc_pll_half"}; 252 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 253 "ioclk_audiocdclk1", "ioclk_spdif_extclk", 254 "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half", 255 "mout_top0_bus1_pll_half"}; 256 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", 257 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; 258 259 static unsigned long top0_clk_regs[] __initdata = { 260 MUX_SEL_TOP00, 261 MUX_SEL_TOP01, 262 MUX_SEL_TOP03, 263 MUX_SEL_TOP0_PERIC0, 264 MUX_SEL_TOP0_PERIC1, 265 MUX_SEL_TOP0_PERIC2, 266 MUX_SEL_TOP0_PERIC3, 267 DIV_TOP03, 268 DIV_TOP0_PERIC0, 269 DIV_TOP0_PERIC1, 270 DIV_TOP0_PERIC2, 271 DIV_TOP0_PERIC3, 272 ENABLE_SCLK_TOP0_PERIC0, 273 ENABLE_SCLK_TOP0_PERIC1, 274 ENABLE_SCLK_TOP0_PERIC2, 275 ENABLE_SCLK_TOP0_PERIC3, 276 }; 277 278 static struct samsung_mux_clock top0_mux_clks[] __initdata = { 279 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, 280 MUX_SEL_TOP00, 0, 1), 281 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, 282 MUX_SEL_TOP00, 4, 1), 283 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p, 284 MUX_SEL_TOP00, 8, 1), 285 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p, 286 MUX_SEL_TOP00, 12, 1), 287 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p, 288 MUX_SEL_TOP00, 16, 1), 289 290 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p, 291 MUX_SEL_TOP01, 4, 1), 292 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p, 293 MUX_SEL_TOP01, 8, 1), 294 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p, 295 MUX_SEL_TOP01, 12, 1), 296 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p, 297 MUX_SEL_TOP01, 16, 1), 298 299 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 300 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 301 302 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 303 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 304 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 305 306 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 307 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), 308 309 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), 310 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), 311 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 312 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 313 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 314 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 315 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 316 }; 317 318 static struct samsung_div_clock top0_div_clks[] __initdata = { 319 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 320 DIV_TOP03, 12, 6), 321 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 322 DIV_TOP03, 20, 6), 323 324 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 325 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 326 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 327 328 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 329 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 330 331 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), 332 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), 333 334 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 335 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 336 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 337 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 338 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 339 }; 340 341 static struct samsung_gate_clock top0_gate_clks[] __initdata = { 342 GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", 343 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), 344 GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", 345 ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0), 346 347 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 348 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 349 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 350 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 351 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 352 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 353 354 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 355 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 356 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", 357 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 358 359 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", 360 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), 361 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", 362 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), 363 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 364 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 365 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 366 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 367 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 368 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 369 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 370 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 371 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", 372 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 373 }; 374 375 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 376 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", 377 1, 2, 0), 378 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", 379 1, 2, 0), 380 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0), 381 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), 382 }; 383 384 static struct samsung_cmu_info top0_cmu_info __initdata = { 385 .mux_clks = top0_mux_clks, 386 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 387 .div_clks = top0_div_clks, 388 .nr_div_clks = ARRAY_SIZE(top0_div_clks), 389 .gate_clks = top0_gate_clks, 390 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 391 .fixed_factor_clks = top0_fixed_factor_clks, 392 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 393 .nr_clk_ids = TOP0_NR_CLK, 394 .clk_regs = top0_clk_regs, 395 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 396 }; 397 398 static void __init exynos7_clk_top0_init(struct device_node *np) 399 { 400 samsung_cmu_register_one(np, &top0_cmu_info); 401 } 402 403 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 404 exynos7_clk_top0_init); 405 406 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 407 #define MUX_SEL_TOP10 0x0200 408 #define MUX_SEL_TOP11 0x0204 409 #define MUX_SEL_TOP13 0x020C 410 #define MUX_SEL_TOP1_FSYS0 0x0224 411 #define MUX_SEL_TOP1_FSYS1 0x0228 412 #define MUX_SEL_TOP1_FSYS11 0x022C 413 #define DIV_TOP13 0x060C 414 #define DIV_TOP1_FSYS0 0x0624 415 #define DIV_TOP1_FSYS1 0x0628 416 #define DIV_TOP1_FSYS11 0x062C 417 #define ENABLE_ACLK_TOP13 0x080C 418 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 419 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 420 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C 421 422 /* List of parent clocks for Muxes in CMU_TOP1 */ 423 PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" }; 424 PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" }; 425 PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" }; 426 PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" }; 427 428 PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user", 429 "ffac_top1_bus0_pll_div2"}; 430 PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user", 431 "ffac_top1_bus1_pll_div2"}; 432 PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user", 433 "ffac_top1_cc_pll_div2"}; 434 PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user", 435 "ffac_top1_mfc_pll_div2"}; 436 437 PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half", 438 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", 439 "mout_top1_mfc_pll_half"}; 440 441 static unsigned long top1_clk_regs[] __initdata = { 442 MUX_SEL_TOP10, 443 MUX_SEL_TOP11, 444 MUX_SEL_TOP13, 445 MUX_SEL_TOP1_FSYS0, 446 MUX_SEL_TOP1_FSYS1, 447 MUX_SEL_TOP1_FSYS11, 448 DIV_TOP13, 449 DIV_TOP1_FSYS0, 450 DIV_TOP1_FSYS1, 451 DIV_TOP1_FSYS11, 452 ENABLE_ACLK_TOP13, 453 ENABLE_SCLK_TOP1_FSYS0, 454 ENABLE_SCLK_TOP1_FSYS1, 455 ENABLE_SCLK_TOP1_FSYS11, 456 }; 457 458 static struct samsung_mux_clock top1_mux_clks[] __initdata = { 459 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, 460 MUX_SEL_TOP10, 4, 1), 461 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, 462 MUX_SEL_TOP10, 8, 1), 463 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p, 464 MUX_SEL_TOP10, 12, 1), 465 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p, 466 MUX_SEL_TOP10, 16, 1), 467 468 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p, 469 MUX_SEL_TOP11, 4, 1), 470 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p, 471 MUX_SEL_TOP11, 8, 1), 472 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p, 473 MUX_SEL_TOP11, 12, 1), 474 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p, 475 MUX_SEL_TOP11, 16, 1), 476 477 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 478 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 479 480 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), 481 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, 482 MUX_SEL_TOP1_FSYS0, 28, 2), 483 484 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), 485 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), 486 }; 487 488 static struct samsung_div_clock top1_div_clks[] __initdata = { 489 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 490 DIV_TOP13, 24, 4), 491 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 492 DIV_TOP13, 28, 4), 493 494 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 495 DIV_TOP1_FSYS0, 16, 10), 496 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", 497 DIV_TOP1_FSYS0, 28, 4), 498 499 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 500 DIV_TOP1_FSYS11, 0, 10), 501 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 502 DIV_TOP1_FSYS11, 12, 10), 503 }; 504 505 static struct samsung_gate_clock top1_gate_clks[] __initdata = { 506 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 507 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 508 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 509 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), 510 511 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 512 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), 513 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 514 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 515 516 GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", 517 ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), 518 GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", 519 ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), 520 }; 521 522 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 523 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", 524 1, 2, 0), 525 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", 526 1, 2, 0), 527 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0), 528 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), 529 }; 530 531 static struct samsung_cmu_info top1_cmu_info __initdata = { 532 .mux_clks = top1_mux_clks, 533 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 534 .div_clks = top1_div_clks, 535 .nr_div_clks = ARRAY_SIZE(top1_div_clks), 536 .gate_clks = top1_gate_clks, 537 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 538 .fixed_factor_clks = top1_fixed_factor_clks, 539 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 540 .nr_clk_ids = TOP1_NR_CLK, 541 .clk_regs = top1_clk_regs, 542 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 543 }; 544 545 static void __init exynos7_clk_top1_init(struct device_node *np) 546 { 547 samsung_cmu_register_one(np, &top1_cmu_info); 548 } 549 550 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 551 exynos7_clk_top1_init); 552 553 /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 554 #define MUX_SEL_CCORE 0x0200 555 #define DIV_CCORE 0x0600 556 #define ENABLE_ACLK_CCORE0 0x0800 557 #define ENABLE_ACLK_CCORE1 0x0804 558 #define ENABLE_PCLK_CCORE 0x0900 559 560 /* 561 * List of parent clocks for Muxes in CMU_CCORE 562 */ 563 PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; 564 565 static unsigned long ccore_clk_regs[] __initdata = { 566 MUX_SEL_CCORE, 567 ENABLE_PCLK_CCORE, 568 }; 569 570 static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 571 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, 572 MUX_SEL_CCORE, 1, 1), 573 }; 574 575 static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 576 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 577 ENABLE_PCLK_CCORE, 8, 0, 0), 578 }; 579 580 static struct samsung_cmu_info ccore_cmu_info __initdata = { 581 .mux_clks = ccore_mux_clks, 582 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 583 .gate_clks = ccore_gate_clks, 584 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 585 .nr_clk_ids = CCORE_NR_CLK, 586 .clk_regs = ccore_clk_regs, 587 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 588 }; 589 590 static void __init exynos7_clk_ccore_init(struct device_node *np) 591 { 592 samsung_cmu_register_one(np, &ccore_cmu_info); 593 } 594 595 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 596 exynos7_clk_ccore_init); 597 598 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 599 #define MUX_SEL_PERIC0 0x0200 600 #define ENABLE_PCLK_PERIC0 0x0900 601 #define ENABLE_SCLK_PERIC0 0x0A00 602 603 /* List of parent clocks for Muxes in CMU_PERIC0 */ 604 PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" }; 605 PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" }; 606 607 static unsigned long peric0_clk_regs[] __initdata = { 608 MUX_SEL_PERIC0, 609 ENABLE_PCLK_PERIC0, 610 ENABLE_SCLK_PERIC0, 611 }; 612 613 static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 614 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p, 615 MUX_SEL_PERIC0, 0, 1), 616 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p, 617 MUX_SEL_PERIC0, 16, 1), 618 }; 619 620 static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 621 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 622 ENABLE_PCLK_PERIC0, 8, 0, 0), 623 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 624 ENABLE_PCLK_PERIC0, 9, 0, 0), 625 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 626 ENABLE_PCLK_PERIC0, 10, 0, 0), 627 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 628 ENABLE_PCLK_PERIC0, 11, 0, 0), 629 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 630 ENABLE_PCLK_PERIC0, 12, 0, 0), 631 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 632 ENABLE_PCLK_PERIC0, 13, 0, 0), 633 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 634 ENABLE_PCLK_PERIC0, 14, 0, 0), 635 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 636 ENABLE_PCLK_PERIC0, 16, 0, 0), 637 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 638 ENABLE_PCLK_PERIC0, 20, 0, 0), 639 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 640 ENABLE_PCLK_PERIC0, 21, 0, 0), 641 642 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 643 ENABLE_SCLK_PERIC0, 16, 0, 0), 644 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 645 }; 646 647 static struct samsung_cmu_info peric0_cmu_info __initdata = { 648 .mux_clks = peric0_mux_clks, 649 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 650 .gate_clks = peric0_gate_clks, 651 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 652 .nr_clk_ids = PERIC0_NR_CLK, 653 .clk_regs = peric0_clk_regs, 654 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 655 }; 656 657 static void __init exynos7_clk_peric0_init(struct device_node *np) 658 { 659 samsung_cmu_register_one(np, &peric0_cmu_info); 660 } 661 662 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 663 #define MUX_SEL_PERIC10 0x0200 664 #define MUX_SEL_PERIC11 0x0204 665 #define MUX_SEL_PERIC12 0x0208 666 #define ENABLE_PCLK_PERIC1 0x0900 667 #define ENABLE_SCLK_PERIC10 0x0A00 668 669 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 670 exynos7_clk_peric0_init); 671 672 /* List of parent clocks for Muxes in CMU_PERIC1 */ 673 PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" }; 674 PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" }; 675 PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" }; 676 PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" }; 677 PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" }; 678 PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" }; 679 PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" }; 680 PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; 681 PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; 682 683 static unsigned long peric1_clk_regs[] __initdata = { 684 MUX_SEL_PERIC10, 685 MUX_SEL_PERIC11, 686 MUX_SEL_PERIC12, 687 ENABLE_PCLK_PERIC1, 688 ENABLE_SCLK_PERIC10, 689 }; 690 691 static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 692 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, 693 MUX_SEL_PERIC10, 0, 1), 694 695 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p, 696 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), 697 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p, 698 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), 699 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p, 700 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), 701 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p, 702 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), 703 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p, 704 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), 705 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p, 706 MUX_SEL_PERIC11, 20, 1), 707 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p, 708 MUX_SEL_PERIC11, 24, 1), 709 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p, 710 MUX_SEL_PERIC11, 28, 1), 711 }; 712 713 static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 714 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 715 ENABLE_PCLK_PERIC1, 4, 0, 0), 716 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 717 ENABLE_PCLK_PERIC1, 5, 0, 0), 718 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 719 ENABLE_PCLK_PERIC1, 6, 0, 0), 720 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 721 ENABLE_PCLK_PERIC1, 7, 0, 0), 722 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 723 ENABLE_PCLK_PERIC1, 8, 0, 0), 724 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 725 ENABLE_PCLK_PERIC1, 9, 0, 0), 726 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 727 ENABLE_PCLK_PERIC1, 10, 0, 0), 728 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 729 ENABLE_PCLK_PERIC1, 11, 0, 0), 730 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", 731 ENABLE_PCLK_PERIC1, 12, 0, 0), 732 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", 733 ENABLE_PCLK_PERIC1, 13, 0, 0), 734 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", 735 ENABLE_PCLK_PERIC1, 14, 0, 0), 736 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", 737 ENABLE_PCLK_PERIC1, 15, 0, 0), 738 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 739 ENABLE_PCLK_PERIC1, 16, 0, 0), 740 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 741 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 742 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 743 ENABLE_PCLK_PERIC1, 18, 0, 0), 744 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 745 ENABLE_PCLK_PERIC1, 19, 0, 0), 746 747 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 748 ENABLE_SCLK_PERIC10, 9, 0, 0), 749 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 750 ENABLE_SCLK_PERIC10, 10, 0, 0), 751 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 752 ENABLE_SCLK_PERIC10, 11, 0, 0), 753 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", 754 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), 755 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", 756 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), 757 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", 758 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), 759 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", 760 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 761 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 762 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 763 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 764 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 765 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 766 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 767 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 768 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 769 }; 770 771 static struct samsung_cmu_info peric1_cmu_info __initdata = { 772 .mux_clks = peric1_mux_clks, 773 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 774 .gate_clks = peric1_gate_clks, 775 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 776 .nr_clk_ids = PERIC1_NR_CLK, 777 .clk_regs = peric1_clk_regs, 778 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 779 }; 780 781 static void __init exynos7_clk_peric1_init(struct device_node *np) 782 { 783 samsung_cmu_register_one(np, &peric1_cmu_info); 784 } 785 786 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 787 exynos7_clk_peric1_init); 788 789 /* Register Offset definitions for CMU_PERIS (0x10040000) */ 790 #define MUX_SEL_PERIS 0x0200 791 #define ENABLE_PCLK_PERIS 0x0900 792 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 793 #define ENABLE_SCLK_PERIS 0x0A00 794 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 795 796 /* List of parent clocks for Muxes in CMU_PERIS */ 797 PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" }; 798 799 static unsigned long peris_clk_regs[] __initdata = { 800 MUX_SEL_PERIS, 801 ENABLE_PCLK_PERIS, 802 ENABLE_PCLK_PERIS_SECURE_CHIPID, 803 ENABLE_SCLK_PERIS, 804 ENABLE_SCLK_PERIS_SECURE_CHIPID, 805 }; 806 807 static struct samsung_mux_clock peris_mux_clks[] __initdata = { 808 MUX(0, "mout_aclk_peris_66_user", 809 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1), 810 }; 811 812 static struct samsung_gate_clock peris_gate_clks[] __initdata = { 813 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 814 ENABLE_PCLK_PERIS, 6, 0, 0), 815 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 816 ENABLE_PCLK_PERIS, 10, 0, 0), 817 818 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 819 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 820 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 821 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 822 823 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 824 }; 825 826 static struct samsung_cmu_info peris_cmu_info __initdata = { 827 .mux_clks = peris_mux_clks, 828 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 829 .gate_clks = peris_gate_clks, 830 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 831 .nr_clk_ids = PERIS_NR_CLK, 832 .clk_regs = peris_clk_regs, 833 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 834 }; 835 836 static void __init exynos7_clk_peris_init(struct device_node *np) 837 { 838 samsung_cmu_register_one(np, &peris_cmu_info); 839 } 840 841 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 842 exynos7_clk_peris_init); 843 844 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 845 #define MUX_SEL_FSYS00 0x0200 846 #define MUX_SEL_FSYS01 0x0204 847 #define MUX_SEL_FSYS02 0x0208 848 #define ENABLE_ACLK_FSYS00 0x0800 849 #define ENABLE_ACLK_FSYS01 0x0804 850 #define ENABLE_SCLK_FSYS01 0x0A04 851 #define ENABLE_SCLK_FSYS02 0x0A08 852 #define ENABLE_SCLK_FSYS04 0x0A10 853 854 /* 855 * List of parent clocks for Muxes in CMU_FSYS0 856 */ 857 PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" }; 858 PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" }; 859 860 PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" }; 861 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll", 862 "phyclk_usbdrd300_udrd30_phyclock" }; 863 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", 864 "phyclk_usbdrd300_udrd30_pipe_pclk" }; 865 866 /* fixed rate clocks used in the FSYS0 block */ 867 struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { 868 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 869 CLK_IS_ROOT, 60000000), 870 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 871 CLK_IS_ROOT, 125000000), 872 }; 873 874 static unsigned long fsys0_clk_regs[] __initdata = { 875 MUX_SEL_FSYS00, 876 MUX_SEL_FSYS01, 877 MUX_SEL_FSYS02, 878 ENABLE_ACLK_FSYS00, 879 ENABLE_ACLK_FSYS01, 880 ENABLE_SCLK_FSYS01, 881 ENABLE_SCLK_FSYS02, 882 ENABLE_SCLK_FSYS04, 883 }; 884 885 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 886 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, 887 MUX_SEL_FSYS00, 24, 1), 888 889 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p, 890 MUX_SEL_FSYS01, 24, 1), 891 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p, 892 MUX_SEL_FSYS01, 28, 1), 893 894 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 895 mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p, 896 MUX_SEL_FSYS02, 24, 1), 897 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", 898 mout_phyclk_usbdrd300_udrd30_phyclk_user_p, 899 MUX_SEL_FSYS02, 28, 1), 900 }; 901 902 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 903 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 904 ENABLE_ACLK_FSYS00, 3, 0, 0), 905 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 906 ENABLE_ACLK_FSYS00, 4, 0, 0), 907 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", 908 "mout_aclk_fsys0_200_user", 909 ENABLE_ACLK_FSYS00, 19, 0, 0), 910 911 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", 912 ENABLE_ACLK_FSYS01, 29, 0, 0), 913 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 914 ENABLE_ACLK_FSYS01, 31, 0, 0), 915 916 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", 917 "mout_sclk_usbdrd300_user", 918 ENABLE_SCLK_FSYS01, 4, 0, 0), 919 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", 920 ENABLE_SCLK_FSYS01, 8, 0, 0), 921 922 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, 923 "phyclk_usbdrd300_udrd30_pipe_pclk_user", 924 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 925 ENABLE_SCLK_FSYS02, 24, 0, 0), 926 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, 927 "phyclk_usbdrd300_udrd30_phyclk_user", 928 "mout_phyclk_usbdrd300_udrd30_phyclk_user", 929 ENABLE_SCLK_FSYS02, 28, 0, 0), 930 931 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", 932 "fin_pll", 933 ENABLE_SCLK_FSYS04, 28, 0, 0), 934 }; 935 936 static struct samsung_cmu_info fsys0_cmu_info __initdata = { 937 .fixed_clks = fixed_rate_clks_fsys0, 938 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0), 939 .mux_clks = fsys0_mux_clks, 940 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 941 .gate_clks = fsys0_gate_clks, 942 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 943 .nr_clk_ids = FSYS0_NR_CLK, 944 .clk_regs = fsys0_clk_regs, 945 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 946 }; 947 948 static void __init exynos7_clk_fsys0_init(struct device_node *np) 949 { 950 samsung_cmu_register_one(np, &fsys0_cmu_info); 951 } 952 953 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 954 exynos7_clk_fsys0_init); 955 956 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 957 #define MUX_SEL_FSYS10 0x0200 958 #define MUX_SEL_FSYS11 0x0204 959 #define ENABLE_ACLK_FSYS1 0x0800 960 961 /* 962 * List of parent clocks for Muxes in CMU_FSYS1 963 */ 964 PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" }; 965 PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" }; 966 PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" }; 967 968 static unsigned long fsys1_clk_regs[] __initdata = { 969 MUX_SEL_FSYS10, 970 MUX_SEL_FSYS11, 971 ENABLE_ACLK_FSYS1, 972 }; 973 974 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 975 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p, 976 MUX_SEL_FSYS10, 28, 1), 977 978 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p, 979 MUX_SEL_FSYS11, 24, 1), 980 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p, 981 MUX_SEL_FSYS11, 28, 1), 982 }; 983 984 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 985 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 986 ENABLE_ACLK_FSYS1, 29, 0, 0), 987 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 988 ENABLE_ACLK_FSYS1, 30, 0, 0), 989 }; 990 991 static struct samsung_cmu_info fsys1_cmu_info __initdata = { 992 .mux_clks = fsys1_mux_clks, 993 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 994 .gate_clks = fsys1_gate_clks, 995 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 996 .nr_clk_ids = FSYS1_NR_CLK, 997 .clk_regs = fsys1_clk_regs, 998 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 999 }; 1000 1001 static void __init exynos7_clk_fsys1_init(struct device_node *np) 1002 { 1003 samsung_cmu_register_one(np, &fsys1_cmu_info); 1004 } 1005 1006 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 1007 exynos7_clk_fsys1_init); 1008 1009 #define MUX_SEL_MSCL 0x0200 1010 #define DIV_MSCL 0x0600 1011 #define ENABLE_ACLK_MSCL 0x0800 1012 #define ENABLE_PCLK_MSCL 0x0900 1013 1014 /* List of parent clocks for Muxes in CMU_MSCL */ 1015 PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 1016 1017 static unsigned long mscl_clk_regs[] __initdata = { 1018 MUX_SEL_MSCL, 1019 DIV_MSCL, 1020 ENABLE_ACLK_MSCL, 1021 ENABLE_PCLK_MSCL, 1022 }; 1023 1024 static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 1025 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 1026 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 1027 }; 1028 static struct samsung_div_clock mscl_div_clks[] __initdata = { 1029 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 1030 DIV_MSCL, 0, 3), 1031 }; 1032 static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 1033 1034 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 1035 ENABLE_ACLK_MSCL, 31, 0, 0), 1036 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 1037 ENABLE_ACLK_MSCL, 30, 0, 0), 1038 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 1039 ENABLE_ACLK_MSCL, 29, 0, 0), 1040 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 1041 ENABLE_ACLK_MSCL, 28, 0, 0), 1042 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 1043 "usermux_aclk_mscl_532", 1044 ENABLE_ACLK_MSCL, 27, 0, 0), 1045 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 1046 "usermux_aclk_mscl_532", 1047 ENABLE_ACLK_MSCL, 26, 0, 0), 1048 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 1049 ENABLE_ACLK_MSCL, 25, 0, 0), 1050 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 1051 ENABLE_ACLK_MSCL, 24, 0, 0), 1052 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 1053 "usermux_aclk_mscl_532", 1054 ENABLE_ACLK_MSCL, 23, 0, 0), 1055 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 1056 ENABLE_ACLK_MSCL, 22, 0, 0), 1057 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 1058 ENABLE_ACLK_MSCL, 21, 0, 0), 1059 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 1060 ENABLE_ACLK_MSCL, 20, 0, 0), 1061 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 1062 ENABLE_ACLK_MSCL, 19, 0, 0), 1063 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 1064 ENABLE_ACLK_MSCL, 18, 0, 0), 1065 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 1066 ENABLE_ACLK_MSCL, 17, 0, 0), 1067 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 1068 ENABLE_ACLK_MSCL, 16, 0, 0), 1069 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 1070 "usermux_aclk_mscl_532", 1071 ENABLE_ACLK_MSCL, 15, 0, 0), 1072 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 1073 "usermux_aclk_mscl_532", 1074 ENABLE_ACLK_MSCL, 14, 0, 0), 1075 1076 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 1077 ENABLE_PCLK_MSCL, 31, 0, 0), 1078 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 1079 ENABLE_PCLK_MSCL, 30, 0, 0), 1080 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 1081 ENABLE_PCLK_MSCL, 29, 0, 0), 1082 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 1083 ENABLE_PCLK_MSCL, 28, 0, 0), 1084 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 1085 ENABLE_PCLK_MSCL, 27, 0, 0), 1086 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 1087 ENABLE_PCLK_MSCL, 26, 0, 0), 1088 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 1089 ENABLE_PCLK_MSCL, 25, 0, 0), 1090 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 1091 ENABLE_PCLK_MSCL, 24, 0, 0), 1092 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 1093 ENABLE_PCLK_MSCL, 23, 0, 0), 1094 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 1095 ENABLE_PCLK_MSCL, 22, 0, 0), 1096 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 1097 ENABLE_PCLK_MSCL, 21, 0, 0), 1098 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 1099 ENABLE_PCLK_MSCL, 20, 0, 0), 1100 }; 1101 1102 static struct samsung_cmu_info mscl_cmu_info __initdata = { 1103 .mux_clks = mscl_mux_clks, 1104 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 1105 .div_clks = mscl_div_clks, 1106 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 1107 .gate_clks = mscl_gate_clks, 1108 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 1109 .nr_clk_ids = MSCL_NR_CLK, 1110 .clk_regs = mscl_clk_regs, 1111 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 1112 }; 1113 1114 static void __init exynos7_clk_mscl_init(struct device_node *np) 1115 { 1116 samsung_cmu_register_one(np, &mscl_cmu_info); 1117 } 1118 1119 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 1120 exynos7_clk_mscl_init); 1121 1122 /* Register Offset definitions for CMU_AUD (0x114C0000) */ 1123 #define MUX_SEL_AUD 0x0200 1124 #define DIV_AUD0 0x0600 1125 #define DIV_AUD1 0x0604 1126 #define ENABLE_ACLK_AUD 0x0800 1127 #define ENABLE_PCLK_AUD 0x0900 1128 #define ENABLE_SCLK_AUD 0x0A00 1129 1130 /* 1131 * List of parent clocks for Muxes in CMU_AUD 1132 */ 1133 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 1134 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 1135 1136 static unsigned long aud_clk_regs[] __initdata = { 1137 MUX_SEL_AUD, 1138 DIV_AUD0, 1139 DIV_AUD1, 1140 ENABLE_ACLK_AUD, 1141 ENABLE_PCLK_AUD, 1142 ENABLE_SCLK_AUD, 1143 }; 1144 1145 static struct samsung_mux_clock aud_mux_clks[] __initdata = { 1146 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 1147 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 1148 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 1149 }; 1150 1151 static struct samsung_div_clock aud_div_clks[] __initdata = { 1152 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 1153 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 1154 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 1155 1156 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 1157 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 1158 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 1159 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 1160 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 1161 }; 1162 1163 static struct samsung_gate_clock aud_gate_clks[] __initdata = { 1164 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 1165 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1166 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 1167 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 1168 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 1169 GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 1170 ENABLE_SCLK_AUD, 30, 0, 0), 1171 1172 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1173 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1174 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1175 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1176 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1177 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1178 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 1179 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1180 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 1181 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1182 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 1183 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 1184 1185 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 1186 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 1187 ENABLE_ACLK_AUD, 28, 0, 0), 1188 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 1189 }; 1190 1191 static struct samsung_cmu_info aud_cmu_info __initdata = { 1192 .mux_clks = aud_mux_clks, 1193 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 1194 .div_clks = aud_div_clks, 1195 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 1196 .gate_clks = aud_gate_clks, 1197 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 1198 .nr_clk_ids = AUD_NR_CLK, 1199 .clk_regs = aud_clk_regs, 1200 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 1201 }; 1202 1203 static void __init exynos7_clk_aud_init(struct device_node *np) 1204 { 1205 samsung_cmu_register_one(np, &aud_cmu_info); 1206 } 1207 1208 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 1209 exynos7_clk_aud_init); 1210